NSC 100331F

100331
Low Power Triple D Flip-Flop
General Description
Features
The 100331 contains three D-type, edge-triggered master/
slave flip-flops with true and complement outputs, a Common Clock (CPC), and Master Set (MS) and Master Reset
(MR) inputs. Each flip-flop has individual Clock (CPn), Direct
Set (SDn) and Direct Clear (CDn) inputs. Data enters a master when both CPn and CPC are LOW and transfers to a
slave when CPn or CPC (or both) go HIGH. The Master Set,
Master Reset and individual CDn and SDn inputs override
the Clock inputs. All inputs have 50 kΩ pull-down resistors.
n
n
n
n
n
n
Logic Symbol
35% power reduction of the 100131
2000V ESD protection
Pin/function compatible with 100131
Voltage compensated operating range = −4.2V to −5.7V
Available to industrial grade temperature range
Available to Standard Microcircuit Drawing (SMD)
5962-9153601
Pin Names
Description
CP0–CP2
Individual Clock Inputs
CPC
Common Clock Input
D0–D2
Data Inputs
CD0–CD2
Individual Direct Clear Inputs
SDn
Individual Direct Set Inputs
MR
Master Reset Input
MS
Master Set Input
Q0-Q2
Data Outputs
Q0–Q2
Complementary Data Outputs
DS100300-1
Connection Diagrams
24-Pin DIP
24-Pin Quad Cerpak
DS100300-3
DS100300-2
© 1998 National Semiconductor Corporation
DS100300
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100331 Low Power Triple D Flip-Flop
August 1998
Logic Diagram
DS100300-5
Asynchronous Operation
Truth Tables
(Each Flip-Flop)
Inputs
Synchronous Operation
(Each Flip-Flop)
Inputs
Dn
CPn
CPC
MS
MR
CDn
Qn(t + 1)
L
N
L
L
L
L
H
N
L
L
L
H
L
L
N
L
L
L
H
L
N
L
L
H
Qn(t)
X
L
L
L
L
X
H
X
L
L
Qn(t)
X
X
H
L
L
Qn(t)
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
U = Undefined
t = Time before CP Positive Transition
t + 1 = Time after CP Positive Transition
N = LOW to HIGH Transition
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CPn
CPC
X
X
X
H
L
X
X
X
L
H
L
X
X
X
H
H
U
Outputs
SDn
2
Outputs
Dn
MS
MR
SDn
CDn
Qn(t + 1)
H
Absolute Maximum Ratings (Note 1)
Input Voltage (DC)
Output Current
(DC Output HIGH)
ESD (Note 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Above which the useful life may be impaired
−65˚C to +150˚C
Storage Temperature (TSTG)
Maximum Junction Temperature (TJ)
Ceramic
+175˚C
Pin Potential to
−7.0V to +0.5V
Ground Pin (VEE)
VEE to +0.5V
−50 mA
≤ 2000V
Recommended Operating
Conditions
Case Temperature (TC)
Military
Supply Voltage (VEE)
−55˚C to +125˚C
−5.7V to −4.2V
Note 1: Absolute maximum ratings are those values beyond which the device may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: ESD testing conforms to MIL-STD-883, Method 3015.
Military Version
DC Electrical Characteristics
VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = −55˚C to +125˚C
Symbol
VOH
Parameter
Min
Max
Units
TC
Output HIGH Voltage
−1025
−870
mV
0˚C to
−1085
−870
mV
−55˚C
−1830
−1620
mV
0˚C to
−1830
−1555
mV
−55˚C
mV
0˚C to
+125˚C
VOL
Output LOW Voltage
Conditions
Notes
VIN = VIH
(Max)
or VIL (Min)
Loading with
50Ω to −2.0V
(Notes 3,
4, 5)
VIN = VIH
(Min)
or VIL (Max)
Loading with
50Ω to −2.0V
(Notes 3,
4, 5)
+125˚C
VOHC
Output HIGH Voltage
−1035
+125˚C
−1085
VOLC
Output LOW Voltage
mV
−55˚C
−1610
mV
0˚C to
−1555
mV
−55˚C
−870
mV
−55˚C to
+125˚C
VIH
Input HIGH Voltage
−1165
+125˚C
VIL
Input LOW Voltage
−1830
−1475
mV
−55˚C to
+125˚C
IIL
Input LOW Current
0.50
µA
−55˚C to
+125˚C
IIH
Input HIGH Current
240
µA
0˚C to
+125˚C
IEE
Power Supply Current
−130
340
µA
−55˚C
−50
mA
−55˚C to
Guaranteed HIGH Signal
for all Inputs
Guaranteed LOW Signal
for all Inputs
VEE = −4.2V
VIN = VIL (Min)
VEE = −5.7V
VIN = VIH (Max)
Inputs Open
+125˚C
(Notes 3,
4, 5, 6)
(Notes 3,
4, 5, 6)
(Notes 3,
4, 5)
(Notes 3,
4, 5)
(Notes 3,
4, 5)
Note 3: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals −55˚C), then testing immediately
without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides “cold start” specs which can be considered a worst case
condition at cold temperatures.
Note 4: Screen tested 100% on each device at −55˚C, +25˚C, and +125˚C, Subgroups, 1, 2, 3, 7 and 8.
Note 5: Sampled tested (Method 5005, Table I) on each manufactured lot at −55˚C, +25˚C, and +125˚C, Subgroups A1, 2, 3, 7 and 8.
Note 6: Guaranteed by applying specified input condition and testing VOH/VOL.
3
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AC Electrical Characteristics
VEE = −4.2V to −5.7V, VCC = VCCA = GND
Symbol
Parameter
TC = −55˚C
TC = +25˚C
TC = +125˚C
Min
Min
Min
Max
Max
fmax
Toggle Frequency
400
tPLH
Propagation Delay
0.50
2.20
0.60
2.00
0.50
2.40
ns
tPHL
CPC to Output
tPLH
Propagation Delay
0.50
2.20
0.60
2.00
0.50
2.40
ns
0.50
2.20
0.60
2.00
0.50
2.40
tPHL
CPn to Output
tPLH
Propagation Delay
tPHL
CDn, SDn to Output
tPLH
400
Units
Conditions
Notes
Max
400
MHz
Figures 2, 3
(Note
10)
Figures 1, 3
CPn, CPC = L
ns
0.50
2.40
0.60
2.10
0.50
2.50
0.70
2.70
0.80
2.60
0.80
2.90
Figures
1, 4
CPn, CPC = H
(Notes
7, 8,
9)
tPHL
tPLH
Propagation Delay
tPHL
MS, MR to Output
tPLH
CPn, CPC = L
ns
0.70
2.90
0.80
2.80
0.80
3.10
0.20
1.40
0.20
1.40
0.20
1.40
CPn, CPC = H
tPHL
tTLH
Transition Time
tTHL
20% to 80%, 80% to 20%
ts
Setup Time
1.00
0.80
0.90
CDn, SDn (Release Time)
1.50
1.30
1.60
MS, MR (Release Time)
Hold Time Dn
tpw(H)
Pulse Width HIGH
CPn, CPC, CDn,
Figures 1, 3, 4
Figure 5
Dn
th
ns
ns
Figure 4
2.50
2.30
2.50
1.50
1.30
1.60
ns
Figure 5
2.00
2.00
2.00
ns
Figures 3, 4
(Note
10)
SDn, MR, MS
Note 7: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals −55˚C), then testing immediately
without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides “cold start” specs which can be considered a worst case
condition at cold temperatures.
Note 8: Screen tested 100% on each device at +25˚C. Temperature only, Subgroup A9.
Note 9: Sample tested (Method 5005, Table I) on each Mfg. lot at +25˚C, Subgroup A9, and at +125˚C, and −55˚C Temp., Subgroups A10 and A11.
Note 10: Not tested at +25˚C, +125˚C and −55˚C Temperature (design characterization data).
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4
Test Circuits
DS100300-6
FIGURE 1. AC Test Circuit
DS100300-7
Notes:
VCC, VCCA = +2V, VEE = −2.5V
L1 and L2 = Equal length 50Ω impedance lines
RT = 50Ω terminator internal to scope
Decoupling 0.1 µF from GND to VCC and VEE
All unused outputs are loaded with 50Ω to GND
CL = Fixture and stray capacitance ≤ 3 pF
FIGURE 2. Toggle Frequency Test Circuit
5
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Switching Waveforms
DS100300-8
FIGURE 3. Propagation Delay (Clock) and Transition Times
DS100300-9
FIGURE 4. Propagation Delay (Resets)
DS100300-10
FIGURE 5. Data Setup and Hold Time
Note 11: ts is the minimum time before the transition of the clock that information must be present at the data input.
Note 12: th is the minimum time after the transition of the clock that information must remain unchanged at the data input.
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6
Physical Dimensions
inches (millimeters) unless otherwise noted
24-Lead Ceramic Dual-In-Line Package (0.400" Wide) (D)
NS Package Number J24E
24-Lead Quad Cerpak (F)
NS Package Number W24B
7
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100331 Low Power Triple D Flip-Flop
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1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into
sonably expected to cause the failure of the life support
the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness.
ure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
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