LH5316P00B FEATURES • 2,097,152 × 8 bit organization (Byte mode: BYTE = VIL) 1,048,576 × 16 bit organization (Word mode: BYTE = VIH) CMOS 16M (2M × 8/1M × 16) MROM PIN CONNECTIONS 44-PIN SOP TOP VIEW NC 1 44 NC A18 2 43 A19 A17 3 42 A8 A7 4 41 A9 • Supply current: – Operating: 70 mA (MAX.) – Standby: 100 µA (MAX.) A6 5 40 A10 A5 6 39 A11 A4 7 38 A12 A3 8 37 A13 • TTL compatible I/O A2 9 36 A14 • Three-state output A1 10 35 A15 A0 11 34 A16 CE 12 33 BYTE GND 13 32 GND OE 14 31 D15/A-1 (NOTE) • Access time: 120 ns (MAX.) • Single +5 V power supply • Static operation • Package: 44-pin, 600-mil SOP D0 15 30 D7 D8 16 29 D14 D1 17 28 D6 • Item related with COCOM regulation: – Non programmable – Not designed or rated as radiation hardened – CMOS process (P type silicon substrate) D9 18 27 D13 D2 19 26 D5 D10 20 25 D12 D3 21 24 D4 D11 22 23 VCC DESCRIPTION The LH5316P00B is a 16M-bit mask-programmable ROM organized as 2,097,152 × 8 bits (Byte mode) or 1,048,576 × 16 bits (Word mode) that can be selected by a BYTE input pin. It is fabricated using silicon-gate CMOS process technology. NOTE: The D15/A-1 pin becomes LSB address input (A-1) when the BYTE pin is set to be LOW in byte mode and data output (D15) when set to be HIGH in word mode. The input state of BYTE pin can not be changed during operation. The BYTE pin must be set to either GND or VCC. 5316P00B-1 Figure 1. Pin Connections 1 LH5316P00B CMOS 16M (2M x 8/1M x 16) MROM A19 43 A18 2 A17 3 A16 34 A15 35 A10 40 A9 41 A8 42 A7 4 A6 5 A5 6 A4 7 A3 8 DATA SELECTOR/OUTPUT BUFFER A12 38 A11 39 MEMORY MATRIX (2,097,152 x 8) (1,048,576 x 16) ADDRESS DECODER ADDRESS BUFFER A14 36 A13 37 COLUMN SELECTOR A2 9 A1 10 A0 11 CE 12 CE BUFFER OE 14 OE BUFFER BYTE 33 BYTE/WORD SWITCHOVER CIRCUIT TIMING GENERATOR 31 29 27 25 D15 D14 D13 D12 22 D11 20 D10 18 D9 16 D8 30 D7 28 D6 26 24 21 19 17 15 D5 D4 D3 D2 D1 D0 SENSE AMPLIFIER ADDRESS BUFFER 31 A-1 23 VCC 13 32 GND 5316P00B-2 Figure 2. LH5316P00B Block Diagram PIN DESCRIPTION SIGNAL 2 PIN NAME A-1 - A19 Address input D0 - D15 SIGNAL PIN NAME OE Output enable input Data output VCC Power supply GND Ground BYTE ×8bit / ×16 bit (Byte/word) mode select input CE Chip enable input NC No connection CMOS 16M (2M x 8/1M x 16) MROM LH5316P00B TRUTH TABLE CE OE DATA OUTPUT A-1 (D15) BYTE ADDRESS INPUT D0 - D7 D8 - D15 LSB MSB SUPPLY CURRENT H X X X High-Z High-Z Standby (ISB) L H X X High-Z High-Z Operating L L H D 0 - D7 D8 - D15 A0 A19 Operating L L L L D0 - D7 High-Z A-1 A19 Operating L L L H D8 - D15 High-Z A-1 A19 Operating NOTES: X = Don’t care; High-Z = High-impedance ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING UNIT Supply voltage VCC -0.3 to +7.0 V Input voltage VIN -0.3 to VCC + 0.3 V Output voltage VOUT -0.3 to VCC + 0.3 V Operating temperature TOPR 0 to +70 °C Storage temperature TSTG -65 to +150 °C RECOMMENDED OPERATING CONDITIONS (TA = 0 to +70°C) PARAMETER SYMBOL MIN. TYP. MAX. UNIT VCC 4.5 5.0 5.5 V Supply voltage DC ELECTICAL CHARACTERISTICS (VCC = 5 V ±10%, TA = 0 to +70°C) PARAMETER SYMBOL CONDITIONS MIN. MAX. UNIT NOTE Input ‘High’ voltage V IH 2.2 VCC + 0.3 V Input ‘Low’ voltage VIL -0.3 0.8 V Output ‘High’ voltage VOH I OH = -400 µA 2.4 V Output ‘Low’ voltage VOL I OL = 2.0 mA 0.4 V Input leakage current | ILI | V IN = 0 V to VCC 10 µA Output leakage current | ILO | V OUT = 0 V to VCC 10 µA 1 ICC1 t RC = 120 ns 70 t RC = 1 µs mA 2 ICC2 55 ISB1 CE = VIH 2 mA ISB2 CE = VCC - 0.2 V 100 µA 10 pF 10 pF Operating current Standby current Input capacitance Output capacitance CIN COUT f = 1 MHz, t A = 25°C NOTES: 1. CE = VIH, OE = VIH, output is open 2. VIN = VIH, VIL, CE = VIL, output is open 3 LH5316P00B CMOS 16M (2M x 8/1M x 16) MROM AC ELECTICAL CHARACTERISTICS (VCC = 5 V ±10%, TA = 0 to +70°C) PARAMETER SYMBOL MIN. MAX. UNIT NOTE Read cycle time tRC 120 ns Address access time tAA 120 ns Chip enable access time tACE 120 ns Output enable delay time tOE 60 ns Output hold time tOH 5 ns tCHZ 60 ns tOHZ 60 ns Output floating time 1 NOTE: 1. Determined by the time for the output to be opened. (Irrespective of output voltage) AC TEST CONDITIONS PARAMETER Input voltage amplitude RATING 0.6 V to 2.4 V Input rise/fall time 10 ns Input signal fall time 10 ns Input reference level 1.5 V Output reference level 1.5 V Output load condition 1TTL + 100 pF CAUTION It is recommended that a decoupling capacitor be connected between VCC and GND-Pin. 4 CMOS 16M (2M x 8/1M x 16) MROM LH5316P00B tRC A-1 - A19 tAA (NOTE) CE tCHZ tACE (NOTE) OE tOHZ tOE (NOTE) D0 - D7 tOH DATA VALID NOTE: The output data becomes valid when the last intervals, tAA, tACE, or tOE, have concluded. 5316P00B-3 Figure 3. Byte Mode (BYTE = VIL) tRC A0 - A19 tAA (NOTE) CE tCHZ tACE (NOTE) OE tOE (NOTE) (D0 - D15) tOHZ tOH DATA VALID NOTE: The output data becomes valid when the last intervals, tAA, tACE, or tOE, have concluded. 5316P00B-4 Figure 4. Word Mode (BYTE = VIH) 5 LH5316P00B CMOS 16M (2M x 8/1M x 16) MROM PACKAGE DIAGRAM 44SOP (SOP044-P-0600) 1.27 [0.050] TYP. 0.50 [0.020] 0.30 [0.012] 44 23 13.40 [0.528] 13.00 [0.512] 1 16.40 [0.646] 15.60 [0.614] 14.40 [0.567] SEE DETAIL 22 0.20 [0.008] 0.10 [0.004] 28.40 [1.118] 28.00 [1.102] 2.9 [0.114] 2.5 [0.098] DETAIL 1.275 [0.050] 0.15 [0.006] 1.275 [0.050] 0.25 [0.010] 0.05 [0.002] 2.9 [0.114] 2.5 [0.098] 3.25 [0.128] 2.45 [0.096] 0.25 [0.010] 0.05 [0.002] 1.275 [0.050] DIMENSIONS IN MM [INCHES] 0 - 10° 0.80 [0.031] MAXIMUM LIMIT MINIMUM LIMIT 44SOP ORDERING INFORMATION LH5316P00B Device Type N Package 44-pin, 600-mil SOP (SOP044-P-600) CMOS 16M (2M x 8 or 1M x 16) Mask-Programmable ROM Example: LH5316P00N (CMOS 16M (2M x 8 or 1M x 16) Mask-Programmable ROM, 44-pin, 600-mil SOP) 5316P00B-5 6