MA-COM MRF174

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by MRF174/D
SEMICONDUCTOR TECHNICAL DATA
The RF MOSFET Line
RF Power Field Effect Transistor
MRF174
N–Channel Enhancement–Mode
Designed primarily for wideband large–signal output and driver stages up to
200 MHz frequency range.
• Guaranteed Performance at 150 MHz, 28 Vdc
Output Power = 125 Watts
Minimum Gain = 9.0 dB
Efficiency = 50% (Min)
• Excellent Thermal Stability, Ideally Suited For Class A
Operation
• Facilitates Manual Gain Control, ALC and Modulation
Techniques
• 100% Tested For Load Mismatch At All Phase Angles
With 30:1 VSWR
• Low Noise Figure — 3.0 dB Typ at 2.0 A, 150 MHz
125 W, to 200 MHz
N–CHANNEL MOS
BROADBAND RF POWER
FET
D
G
S
CASE 211–11, STYLE 2
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Drain–Source Voltage
VDSS
65
Vdc
Drain–Gate Voltage
(RGS = 1.0 MΩ)
VDGR
65
Vdc
VGS
± 40
Vdc
Drain Current — Continuous
ID
13
Adc
Total Device Dissipation @ TC = 25°C
Derate above 25°C
PD
270
1.54
Watts
W/°C
Storage Temperature Range
Tstg
– 65 to +150
°C
TJ
200
°C
Symbol
Max
Unit
RθJC
0.65
°C/W
Gate–Source Voltage
Operating Junction Temperature
THERMAL CHARACTERISTICS
Characteristic
Thermal Resistance, Junction to Case
Handling and Packaging — MOS devices are susceptible to damage from electrostatic charge. Reasonable precautions in handling and
packaging MOS devices should be observed.
REV 7
1
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted.)
Characteristic
Symbol
Min
Typ
Max
Unit
Drain–Source Breakdown Voltage (VGS = 0, ID = 50 mA)
V(BR)DSS
65
—
—
Vdc
Zero Gate Voltage Drain Current (VDS = 28 V, VGS = 0)
IDSS
—
—
10
mAdc
Gate–Source Leakage Current (VGS = 20 V, VDS = 0)
IGSS
—
—
1.0
µAdc
Gate Threshold Voltage (VDS = 10 V, ID = 100 mA)
VGS(th)
1.0
3.0
6.0
Vdc
Forward Transconductance (VDS = 10 V, ID = 3.0 A)
gfs
1.75
2.5
—
mhos
Input Capacitance (VDS = 28 V, VGS = 0, f = 1.0 MHz)
Ciss
—
175
—
pF
Output Capacitance (VDS = 28 V, VGS = 0, f = 1.0 MHz)
Coss
—
190
—
pF
Reverse Transfer Capacitance (VDS = 28 V, VGS = 0, f = 1.0 MHz)
Crss
—
40
—
pF
Noise Figure
(VDD = 28 Vdc, ID = 2.0 A, f = 150 MHz)
NF
—
3.0
—
dB
Common Source Power Gain
(VDD = 28 Vdc, Pout = 125 W, f = 150 MHz, IDQ = 100 mA)
Gps
9.0
11.8
—
dB
Drain Efficiency
(VDD = 28 Vdc, Pout = 125 W, f = 150 MHz, IDQ = 100 mA)
η
50
60
—
%
Electrical Ruggedness
(VDD = 28 Vdc, Pout = 125 W, f = 150 MHz, IDQ = 100 mA,
VSWR 30:1 at all Phase Angles)
ψ
OFF CHARACTERISTICS
ON CHARACTERISTICS
DYNAMIC CHARACTERISTICS
FUNCTIONAL CHARACTERISTICS (Figure 1)
No Degradation in Output Power
L4
R2
BIAS
ADJUST
R3
+
C9
–
C12
C13
R1
C10 D1
C14
C11
+
VDD = 28 V
–
RFC1
R4
C3
RF INPUT
C1
C2
C8
L1
L2
C4
C5
RF OUTPUT
L3
DUT
C1 — 15 pF Unelco
C2 — Arco 462, 5.0 – 80 pF
C3 — 100 pF Unelco
C4 — 25 pF Unelco
C6 — 40 pF Unelco
C7 — Arco 461, 2.7 – 30 pF
C5, C8 — Arco 463, 9.0 – 180 pF
C9, C11, C14 — 0.1 µF Erie Redcap
C10 — 50 µF, 50 V
C12, C13 — 680 pF Feedthru
D1 — 1N5925A Motorola Zener
C6
L1 — #16 AWG, 1–1/4 Turns, 0.213″ ID
L2 — #16 AWG, Hairpin
2
0.25″
0.062″
0.47″
0.2″
L4 — 10 Turns #16 AWG Enameled Wire on R1
RFC1 — 18 Turns #16 AWG Enameled Wire, 0.3″ ID
R1 — 10 Ω, 2.0 W
R2 — 1.8 kΩ, 1/2 W
R3 — 10 kΩ, 10 Turn Bourns
R4 — 10 kΩ, 1/4 W
L3 — #14 AWG, Hairpin
Figure 1. 150 MHz Test Circuit
REV 7
C7
140
80
150 MHz
f = 100 MHz
120
Pout , OUTPUT POWER (WATTS)
Pout , OUTPUT POWER (WATTS)
f = 100 MHz
200 MHz
100
80
60
40
VDD = 28 V
IDQ = 100 mA
20
0
4
2
6
8
10
12
40
30
VDD = 13.5 V
IDQ = 100 mA
20
0
4
2
6
8
10
12
14
Pin, INPUT POWER (WATTS)
Pin, INPUT POWER (WATTS)
Figure 2. Output Power versus Input Power
Figure 3. Output Power versus Input Power
16
160
IDQ = 100 mA
f = 100 MHz
140
Pin = 6 W
Pout , OUTPUT POWER (WATTS)
Pout , OUTPUT POWER (WATTS)
200 MHz
50
0
14
160
120
4W
100
80
2W
60
40
20
140
IDQ = 100 mA
f = 150 MHz
Pin = 12 W
120
8W
100
80
4W
60
40
20
0
0
12
14
16
18
20
22
24
26
28
12
14
16
18
20
22
24
26
VDD, SUPPLY VOLTAGE (VOLTS)
VDD, SUPPLY VOLTAGE (VOLTS)
Figure 4. Output Power versus Supply Voltage
Figure 5. Output Power versus Supply Voltage
160
28
22
140
IDQ = 100 mA
f = 200 MHz
20
120
Pin = 16 W
100
12 W
80
8W
Pout = 125 W
VDD = 28 V
IDQ = 100 mA
18
G PS , POWER GAIN (dB)
Pout , OUTPUT POWER (WATTS)
60
10
0
60
40
16
14
12
10
8
6
20
4
0
12
REV 7
3
150 MHz
70
14
16
18
20
22
24
26
28
2
20
40
60
80
100
120
140
160
180
200
VDD, SUPPLY VOLTAGE (VOLTS)
f, FREQUENCY (MHz)
Figure 6. Output Power versus Supply Voltage
Figure 7. Power Gain versus Frequency
220
5
f = 150 MHz
Pin = CONSTANT
IDQ = 100 mA
VDD = 28 V
140
120
I D, DRAIN CURRENT (AMPS)
Pout , OUTPUT POWER (WATTS)
160
100
80
60
40
4
VDS = 10 V
3
2
TYPICAL DEVICE SHOWN, VGS(th) = 3 V
1
20
TYPICAL DEVICE SHOWN, VGS(th) = 3 V
–12
–10
–8
–6
–4
–2
2
0
4
0
6
1
2
3
4
5
6
VGS, GATE–SOURCE VOLTAGE (VOLTS)
VGS, GATE–SOURCE VOLTAGE (VOLTS)
Figure 8. Output Power versus Gate Voltage
Figure 9. Drain Current versus Gate Voltage
(Transfer Characteristics)
1000
1.2
900
VDD = 28 V
ID = 4 A
1
3A
2A
0.9
100 mA
0.8
– 25
0
25
50
75
100
125
VGS = 0 V
f = 1 MHz
800
C, CAPACITANCE (pF)
1.1
150
175
TC, CASE TEMPERATURE (°C)
Figure 10. Gate–Source Voltage versus
Case Temperature
700
600
500
400
300
Coss
200
Ciss
100
Crss
0
0
4
8
12
16
20
VDS, DRAIN–SOURCE VOLTAGE (VOLTS)
10
6
4
TC = 25°C
2
1
0.6
0.4
0.2
1
2
4
6
10
20
40
VDS, DRAIN–SOURCE VOLTAGE (VOLTS)
Figure 12. DC Safe Operating Area
REV 7
4
24
Figure 11. Capacitance versus Drain Voltage
20
I D, DRAIN CURRENT (AMPS)
VGS, GATE-SOURCE VOLTAGE (NORMALIZED)
0
–14
60
100
28
f
(MHz)
S11
S21
φ
S12
φ
5
φ
φ
2.0
|S11|
0.932
– 133
|S21|
74.0
112
|S12|
0.011
23
|S22|
0.835
– 151
5.0
0.923
– 160
31.6
98
0.011
12
0.886
– 168
10
0.921
– 170
16.0
93
0.011
10
0.896
– 174
20
0.921
– 175
8.00
88
0.011
12
0.899
– 177
30
0.921
– 177
5.32
86
0.011
16
0.900
– 178
40
0.921
– 177
3.98
83
0.012
21
0.901
– 178
50
0.922
– 178
3.17
81
0.012
26
0.902
– 178
60
0.923
– 178
2.63
79
0.012
30
0.903
– 178
70
0.924
– 178
2.24
77
0.013
34
0.904
– 178
80
0.925
– 178
1.95
75
0.013
39
0.906
– 178
90
0.927
– 178
1.72
73
0.014
43
0.907
– 178
100
0.930
– 178
1.50
71
0.016
45
0.910
– 178
110
0.930
– 178
1.31
70
0.018
46
0.912
– 178
120
0.931
– 178
1.19
68
0.019
47
0.914
– 178
130
0.942
– 178
1.10
67
0.019
49
0.919
– 178
140
0.936
– 178
1.01
66
0.021
50
0.921
– 178
150
0.938
– 178
0.936
65
0.021
53
0.922
– 178
160
0.938
– 178
0.879
64
0.022
53
0.923
– 178
170
0.940
– 178
0.830
63
0.023
54
0.923
– 177
180
0.942
– 178
0.780
61
0.024
56
0.924
– 177
190
0.942
– 178
0.737
60
0.026
59
0.928
– 177
200
0.952
– 178
0.705
59
0.027
58
0.929
– 177
210
0.950
– 178
0.668
57
0.029
61
0.934
– 177
220
0.942
– 178
0.626
56
0.030
61
0.933
– 177
230
0.943
– 178
0.592
56
0.032
62
0.939
– 177
240
0.946
– 177
0.566
55
0.033
64
0.941
– 177
250
0.952
– 177
0.545
54
0.035
64
0.943
– 177
260
0.958
– 177
0.523
53
0.036
65
0.946
– 177
270
0.956
– 177
0.500
52
0.038
67
0.943
– 177
280
0.960
– 177
0.481
52
0.039
68
0.946
– 177
290
0.956
– 178
0.460
51
0.042
68
0.944
– 177
300
0.955
– 178
0.443
50
0.043
68
0.947
– 177
Table 1. Common Source Scattering Parameters
VDS = 28 V, ID = 3.0 A
REV 7
S22
+ j50
+ 90°
+ j25
+ j100
+ 60°
+120°
300
+ j150
+ j10
250
+150°
+ j250
+ j500
10
300
0
25
50
100
150
.05
250 500
180°
f = 30 MHz
.04
.03
.02
+ 30°
200
150
100
50
f = 30 MHz
.01
0°
– j500
– j250
– j10
– 30°
–150°
– j150
– j100
– j25
– 60°
–120°
– j50
– 90°
Figure 13. S11, Input Reflection Coefficient
versus Frequency
VDS = 28 V, ID = 3.0 A
Figure 14. S12, Reverse Transmission Coefficient
versus Frequency
VDS = 28 V, ID = 3.0 A
+ j50
+ 90°
f = 30 MHz
+ j25
+ 60°
+120°
+ j100
+ j150
50
+ 30°
+150°
180°
5
4
3
2
1
100
150
300
+ j10
+ j250
+ j500
0°
0
f = 30 MHz
25
50
100
150
250 500
300
– j500
– j250
– j10
– 30°
–150°
– 60°
–120°
– j150
– j100
– j25
– 90°
– j50
Figure 15. S21, Forward Transmission Coefficient
versus Frequency
VDS = 28 V, ID = 3.0 A
Figure 16. S22, Output Reflection Coefficient
versus Frequency
VDS = 28 V, ID = 3.0 A
REV 7
6
150
f = 200 MHz
f = 200 MHz
100
100
Zin
Pout = 125 W, VDD = 28 V
IDQ = 100 mA
ZOL*
30
30
150
Zo = 10 Ω
ZOL* = Conjugate of the optimum load impedance
ZOL* = into which the device output operates at a
ZOL* = given output power, voltage and frequency.
f
MHz
Zin
Ohms
ZOL*
Ohms
30
100
150
200
2.90 – j3.95
1.25 – j2.90
1.18 – j1.40
1.30 – j0.90
2.95 – j3.90
1.85 – j1.05
1.72 – j0.05
1.70 + j0.25
Figure 17. Series Equivalent Input/Output Impedance, Zin, ZOL*
REV 7
7
DESIGN CONSIDERATIONS
The MRF174 is a RF power N–Channel enhancement
mode field–effect transistor (FET) designed especially for
UHF power amplifier and oscillator applications. M/A-COM RF
MOSFETs feature a vertical structure with a planar design,
thus avoiding the processing difficulties associated with V–
groove vertical power FETs.
M/A-COM Application Note AN211A, FETs in Theory and
Practice, is suggested reading for those not familiar with the
construction and characteristics of FETs.
The major advantages of RF power FETs include high
gain, low noise, simple bias systems, relative immunity from
thermal runaway, and the ability to withstand severely mismatched loads without suffering damage. Power output can
be varied over a wide range with a low power dc control signal, thus facilitating manual gain control, ALC and modulation.
DC BIAS
The MRF174 is an enhancement mode FET and, therefore, does not conduct when drain voltage is applied. Drain
current flows when a positive voltage is applied to the gate.
See Figure 9 for a typical plot of drain current versus gate
voltage. RF power FETs require forward bias for optimum
performance. The value of quiescent drain current (IDQ) is
not critical for many applications. The MRF174 was charac-
REV 7
8
terized at IDQ = 100 mA, which is the suggested minimum
value of IDQ. For special applications such as linear amplification, IDQ may have to be selected to optimize the critical
parameters.
The gate is a dc open circuit and draws no current. Therefore, the gate bias circuit may generally be just a simple resistive divider network. Some special applications may
require a more elaborate bias system.
GAIN CONTROL
Power output of the MRF174 may be controlled from its
rated value down to zero (negative gain) by varying the dc
gate voltage. This feature facilitates the design of manual
gain control, AGC/ALC and modulation systems. (See
Figure 8.)
AMPLIFIER DESIGN
Impedance matching networks similar to those used with
bipolar UHF transistors are suitable for MRF174. See
M/A-COM Application Note AN721, Impedance Matching Networks Applied to RF Power Transistors. The higher input
impedance of RF MOSFETs helps ease the task of broadband network design. Both small signal scattering parameters and large signal impedances are provided. While the
s–parameters will not produce an exact design solution for
high power operation, they do yield a good first approximation. This is an additional advantage of RF MOS power FETs.
PACKAGE DIMENSIONS
A
U
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
M
1
M
Q
DIM
A
B
C
D
E
H
J
K
M
Q
R
U
4
R
2
B
3
D
K
J
H
C
E
SEATING
PLANE
CASE 211–11
ISSUE N
Specifications subject to change without notice.
n North America: Tel. (800) 366-2266, Fax (800) 618-8883
n Asia/Pacific: Tel.+81-44-844-8296, Fax +81-44-844-8298
n Europe: Tel. +44 (1344) 869 595, Fax+44 (1344) 300 020
Visit www.macom.com for additional data sheets and product information.
REV 7
9
INCHES
MIN
MAX
0.960
0.990
0.465
0.510
0.229
0.275
0.216
0.235
0.084
0.110
0.144
0.178
0.003
0.007
0.435
–––
45 _NOM
0.115
0.130
0.246
0.255
0.720
0.730
STYLE 2:
PIN 1.
2.
3.
4.
SOURCE
GATE
SOURCE
DRAIN
MILLIMETERS
MIN
MAX
24.39
25.14
11.82
12.95
5.82
6.98
5.49
5.96
2.14
2.79
3.66
4.52
0.08
0.17
11.05
–––
45 _NOM
2.93
3.30
6.25
6.47
18.29
18.54