2SJ319(L), 2SJ319(S) Silicon P Channel MOS FET REJ03G0858-0200 (Previous: ADE-208-1192) Rev.2.00 Sep 07, 2005 Description High speed power switching Features • • • • • Low on-resistance High speed switching Low drive current No secondary breakdown Suitable for switching regulator, DC-DC converter Outline RENESAS Package code: PRSS0004ZD-A (Package name: DPAK (L)-(1) ) RENESAS Package code: PRSS0004ZD-C (Package name: DPAK (S) ) 4 1 1 2 3 Rev.2.00 Sep 07, 2005 page 1 of 7 D 4 2 1. Gate 2. Drain 3. Source 4. Drain G 3 S 2SJ319(L), 2SJ319(S) Absolute Maximum Ratings (Ta = 25°C) Item Drain to source voltage Gate to source voltage Drain current Drain peak current Body to drain diode reverse drain current Symbol VDSS Value –200 Unit V VGSS ID ±20 –3 V A –12 –3 A A 20 150 W °C –55 to +150 °C ID (pulse) IDR Note 1 Note 2 Channel dissipation Channel temperature Pch Tch Storage temperature Notes: 1. PW ≤ 10 µs, duty cycle ≤ 1% 2. Value at Tc = 25°C Tstg Electrical Characteristics (Ta = 25°C) Item Drain to source breakdown voltage Symbol V (BR) DSS Min –200 Typ — Max — Unit V Test Conditions ID = –10 mA, VGS = 0 Gate to source breakdown voltage Gate to source leak current V (BR) GSS IGSS ±20 — — — — ±10 V µA IG = ±100 µA, VDS = 0 VGS = ±16 V, VDS = 0 IDSS — — –100 –4.0 µA V VDS = –160 V, VGS = 0 ID = –1 mA, VDS = –10 V Zero gate voltage drain current Gate to source cutoff voltage VGS (off) — –2.0 Static drain to source on state resistance Forward transfer admittance RDS (on) |yfs| — 1.0 1.7 1.7 2.3 — Ω S ID = –2 A, VGS = –10 V Note 3 ID = –2 A, VDS = –10 V Input capacitance Output capacitance Ciss Coss — — 330 130 — — pF pF Reverse transfer capacitance Turn-on delay time Crss td (on) — — 25 10 — — pF ns VDS = –10 V VGS = 0 f = 1 MHz tr 30 40 — — ns ns Rise time Turn-off delay time td (off) — — Fall time Body to drain diode forward voltage tf VDF — — 30 –1.15 — — ns V trr — 180 — ns Body to drain diode reverse recovery time Note: 3. Pulse test Rev.2.00 Sep 07, 2005 page 2 of 7 Note 3 ID = –2 A VGS = –10 V RL = 15 Ω IF = –3 A, VGS = 0 IF = –3 A, VGS = 0 diF/dt = 50 A/µs 2SJ319(L), 2SJ319(S) Main Characteristics Maximum Safe Operation Area Power vs. Temperature Derating –50 –30 ID (A) 15 –10 10 –3 Drain Current Channel Dissipation Pch (W) 20 10 05 0 50 100 150 –1 –0.3 Case Temperature –0.05 –1 200 Tc (°C) –3 Drain Current –10 –6 V Tc = –25°C ID (A) Pulse Test –5 V –2 –4 V –1 –4 –8 –12 75°C –3 –2 –1 VDS = –10 V Pulse Test –16 0 –20 Drain to Source Saturation Voltage vs. Gate to Source Voltage –20 Pulse Test –16 –12 ID = –5 A –8 –2 A –4 –1 A 0 –4 –8 –12 Gate to Source Voltage Rev.2.00 Sep 07, 2005 page 3 of 7 –16 –20 VGS (V) 0 –2 –4 –6 –8 Gate to Source Voltage VDS (V) –10 VGS (V) Static Drain to Source on State Resistance vs. Drain Current Drain to Source on State Resistance RDS (on) (Ω) Drain to Source Saturation Voltage VDS (on) (V) Drain to Source Voltage 0 VDS (V) 25°C –4 VGS = –3.5 V 0 –100 –300 –500 –30 Typical Transfer Characteristics Drain Current ID (A) –8 V –3 0 µs µs –5 –10 V –4 PW Drain to Source Voltage Typical Output Characteristics –5 0 1 m = s 10 Op m s( er ati 1s on ho (T t) Operation in c= this area is 25 °C limited by RDS (on) ) Ta = 25°C DC –0.1 0 10 10 5 VGS = –10 V Pulse Test 2 1 0.5 0.2 0.1 –0.2 –0.5 –1 –2 Drain Current –5 ID (A) –10 2SJ319(L), 2SJ319(S) Forward Transfer Admittance vs. Drain Current Forward Transfer Admittance |yfs| (S) Static Drain to Source on State Resistance RDS (on) (Ω) Static Drain to Source on State Resistance vs. Temperature 5 4 –2 A 3 ID = –5 A 2 –1 A 1 VGS = –10 V Pulse Test 0 –40 0 40 80 Case Temperature 120 160 3 2 1 0.2 VDS = –10 V Pulse Test 0.1 –0.05 –0.1 –0.2 Tc (°C) –2 –5 –10 Typical Capacitance vs. Drain to Source Voltage 1000 500 200 Capacitance C (pF) Reverse Recovery Time trr (ns) –0.5 –1 Drain Current ID (A) 500 100 50 20 di / dt = 50 A / µs, VGS = 0 duty ≤ 1 %, Ta = 25°C 10 5 –0.05 –0.1 –0.2 –0.5 –1 Reverse Drain Current –2 100 50 20 –5 IDR (A) –4 VDD = –150 V –100 V –50 V –300 –8 –12 VGS –16 –400 –500 0 4 8 Gate Charge Rev.2.00 Sep 07, 2005 page 4 of 7 12 16 Qg (nc) –30 –40 –50 –20 20 500 VGS = –10 V, VDD = –30 V PW = 2 µs, duty ≤ 1 % Switching Time t (ns) VDS –200 –20 Switching Characteristics VGS (V) –100 Crss Drain to Source Voltage VDS (V) 0 VDD = –50 V –100 V –150 V Coss 10 V = 0 GS f = 1 MHz 5 0 –10 Gate to Source Voltage 0 Ciss 200 Dynamic Input Characteristics VDS (V) 25°C 75°C 0.5 Body-Drain Diode Reverse Recovery Time Drain to Source Voltage Tc = –25°C 200 100 td(off) 50 tf 20 tr 10 5 –0.05 –0.1 –0.2 td(on) –0.5 –1 Drain Current –2 ID (A) –5 –10 2SJ319(L), 2SJ319(S) Reverse Drain Current vs. Source to Drain Voltage –5 Reverse Drain Current IDR (A) Pulse Test –4 –3 –2 –10 V –1 VGS = 0, 5 V 0 –1.2 –1.6 Source to Drain Voltage VSD 0 –0.4 –0.8 –2.0 (V) Normalized Transient Thermal Impedance γ s (t) Normalized Transient Thermal Impedance vs. Pulse Width 3 Tc = 25°C 1 D=1 0.5 0.3 0.2 0.1 0.1 θch – c (t) = γ s (t) • θch – c θch – c = 6.25°C/W, Tc = 25°C 0.05 0.02 0.03 0.0 1s 1 t ho D= PDM pu lse 0.01 10 µ PW T PW T 100 µ 1m 10 m 100 m 1 10 Pulse Width PW (S) Switching Time Test Circuit Waveform Vin Vout Monitor Vin Monitor 10% D.U.T. 90% RL 90% 90% Vin –10 V 50 Ω VDD = –30 V Vout td(on) Rev.2.00 Sep 07, 2005 page 5 of 7 10% tr 10% td(off) tf 2SJ319(L), 2SJ319(S) Package Dimensions RENESAS Code Package Name MASS[Typ.] PRSS0004ZD-A DPAK(L)-(1) / DPAK(L)-(1)V 0.42g 1.7 ± 0.5 JEITA Package Code 2.3 ± 0.2 0.55 ± 0.1 5.5 ± 0.5 6.5 ± 0.5 5.4 ± 0.5 Unit: mm 3.1 ± 0.5 1.15 ± 0.1 0.8 ± 0.1 2.29 ± 0.5 16.2 ± 0.5 1.2 ± 0.3 2.29 ± 0.5 RENESAS Code Package Name MASS[Typ.] SC-63 PRSS0004ZD-C DPAK(S) / DPAK(S)V 0.28g 6.5 ± 0.5 5.4 ± 0.5 (0.1) Unit: mm 2.3 ± 0.2 0.55 ± 0.1 0 – 0.25 2.5 ± 0.5 (1.2) 1.0 Max. 2.29 ± 0.5 Rev.2.00 Sep 07, 2005 page 6 of 7 (5.1) (5.1) (0.1) 1.2 Max 5.5 ± 0.5 1.5 ± 0.5 JEITA Package Code 0.55 ± 0.1 0.8 ± 0.1 2.29 ± 0.5 0.55 ± 0.1 2SJ319(L), 2SJ319(S) Ordering Information Part Name 2SJ319L-E 2SJ319STL-E Quantity 3200 pcs 3000 pcs Shipping Container Box (Sack) Taping Note: For some grades, production may be terminated. Please contact the Renesas sales office to check the state of production before ordering the product. Rev.2.00 Sep 07, 2005 page 7 of 7 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. 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