2SJ244 Silicon P Channel MOS FET REJ03G0853-0200 (Previous: ADE-208-1187) Rev.2.00 Sep 07, 2005 Description High speed power switching Low voltage operation Features • Very Low on-resistance • High speed switching • Suitable for camera or VTR motor drive circuit, power switch, solenoid drive and etc. Outline RENESAS Package code: PLZZ0004CA-A (Package name: UPAK R ) D 3 2 1 1. Gate 2. Drain 3. Source 4. Drain G 4 S Note: Marking is “JY”. *UPAK is a trademark of Renesas Technology Corp. Rev.2.00 Sep 07, 2005 page 1 of 6 2SJ244 Absolute Maximum Ratings (Ta = 25°C) Item Drain to source voltage Gate to source voltage Drain current Symbol VDSS Value –12 Unit V VGSS ID ±7 ±2 V A ±4 1 A W 150 –55 to +150 °C °C Note 1 Drain peak current Channel dissipation ID (pulse) Note 2 Pch Channel temperature Storage temperature Tch Tstg Notes: 1. PW ≤ 100 µs, duty cycle ≤ 10% 2. Value on the alumina ceramic board (12.5 × 20 × 0.7 mm) Electrical Characteristics (Ta = 25°C) Item Symbol Min Typ Max Unit V (BR) DSS V (BR) GSS –12 ±7 — — — — V V ID = –1 mA, VGS = 0 IG = ±10 µA, VDS = 0 IGSS IDSS — — — — ±5 –1 µA µA VGS = ±6 V, VDS = 0 VDS = –8 V, VGS = 0 Gate to source cutoff voltage Static drain to source on state resistance VGS (off) RDS (on) 1 –0.4 — — 0.65 –1.4 0.9 V Ω ID = –100 µA, VDS = –5 V Note 3 ID = –0.5 A, VGS = –2.5 V Forward transfer admittance RDS (on) 2 |yfs| — — 0.5 1.8 — — Ω S ID = –1 A, VGS = –4 V Note 3 ID = –1 A, VDS = –5 V Input capacitance Output capacitance Ciss Coss — — 100 168 — — pF pF Reverse transfer capacitance Turn-on delay time Crss td (on) — — 35 365 — — pF ns VDS = –5 V VGS = 0 f = 1 MHz Turn-off delay time Body to drain diode forward voltage td (off) VDF — — 1450 — — 7 ns V Drain to source breakdown voltage Gate to source breakdown voltage Gate to source leak current Zero gate voltage drain current Note: 3. Pulse test Rev.2.00 Sep 07, 2005 page 2 of 6 Test Conditions Note 3 Note 3 ID = –0.2 A Vin = –4 V, RL = 51 Ω IF = 4 A Note 3 , VGS = 0 2SJ244 Main Characteristics Maximum Safe Operation Area –10 2.0 ID (A) PW = 1 ms (1 shot) 1.0 50 100 150 Ambient Temperature –0.03 Ta (°C) –5 –4 V ID (A) Pulse Test –4 –3 V –2 –2 V –1 Drain Current –2.5 V 0 –2 –4 –6 –8 Drain to Source Voltage 75°C –2 –1 VDS = –5 V Pulse Test 0 –10 10 5 Tc = –25°C 25°C 2 75°C 1 0.5 VDS = –5 V Pulse Test 0.2 –0.1 –0.2 –0.5 –1 –2 Drain Current ID (A) Rev.2.00 Sep 07, 2005 page 3 of 6 –5 –10 –1 –2 –3 –4 –5 VGS (V) Drain to Source on State Resistance vs. Drain Current Drain to Source on State Resistance RDS (on) (Ω) 20 0 Gate to Source Voltage VDS (V) Forward Transfer Admittance vs. Drain Current Forward Transfer Admittance |yfs| (S) –100 25°C –4 VGS = –1.5 V 0 –30 –3 –3 Drain Current –10 Tc = –25°C –3.5 V –4.5 V –3 Typical Forward Transfer Characteristics ID (A) –5 V –1 Drain to Source Voltage VDS (V) (on the alumina ceramic board) Typical Output Characteristics –5 Operation in this area is limited by RDS (on) –0.01 –0.1 –0.3 200 ) °C 25 0 –0.1 = 0 –0.3 a (T 0.5 –1 n tio ra pe O Drain Current 1.5 –3 DC Channel Power Dissipation Pch (W) (on the alumina ceramic board) Maximum Channel Power Dissipation Curve 10 Pulse Test 5 2 –2 V –3 V 1 0.5 VGS = –4 V 0.2 0.1 –0.1 –0.2 –0.5 –1 Drain Current –2 –5 ID (A) 10 Drain to Source Saturation Voltage vs. Gate to Source Voltage Drain to Source on State Resistance vs. Temperature –1.0 Drain to Source on State Resistance RDS (on) (Ω) Drain to Source Saturation Voltage VDS (on) (V) 2SJ244 Pulse Test –0.8 –0.6 ID = –1 A –0.4 –0.5 A –0.2 –0.2 A –0.1 A 0 0 –1 –2 –3 –4 Gate to Source Voltage –5 1.0 ID = –1 A 0.8 –0.5 A 0.6 0.4 Pulse Test 1000 1000 500 200 100 50 –2 Reverse Drain Current –5 500 tr td(on) 100 50 VDS –10 –4 VDD = –10 V –2 –5 V 0 0 4 Gate Charge Rev.2.00 Sep 07, 2005 page 4 of 6 6 8 Qg (nc) –2 –5 –10 ID (A) 10 VGS (V) 1000 500 Capacitance C (pF) –6 Gate to Source Voltage –8 VGS 2 –1 Typical Capacitance vs. Drain to Source Voltage VDD = –10 V 0 –0.5 Drain Current IDR (A) –10 –5 Tc (°C) tf 20 –0.1 –0.2 –5 V –15 100 VGS = –4 V, VDD = –10 V PW = 2 µs, Duty Cycle = 1 % –10 –25 –20 75 200 Dynamic Input Characteristics ID = –4 A Pulse Test 50 td(off) di / dt = 10 A / µs PW = 10 µs –1 25 Switching Time vs. Drain Current Switching Time t (ns) Reverse Recovery Time trr (ns) 0 Case Temperature VGS (V) 2000 –0.5 VGS = –4 V ID = –1 A 0 –25 2000 20 –0.1 –0.2 VDS (V) –0.5 A 0.2 Body-Drain Diode Reverse Recovery Time Drain to Source Voltage VGS = –2.5 V Coss 200 Ciss 100 50 Crss 20 VGS = 0 f = 1 MHz 10 –0.1 –0.2 –0.5 –1 –2 –5 –10 Drain to Source Voltage VDS (V) 2SJ244 Reverse Drain Current vs. Source to Drain Voltage Reverse Drain Current IDR (A) –4 Pulse Test –3 –4 V –2 –2.5 V –1 VGS = 0 0 0 –0.5 –1.0 Source to Drain Voltage Rev.2.00 Sep 07, 2005 page 5 of 6 –1.5 VSD –2.0 (V) 2SJ244 Package Dimensions RENESAS Code Package Name MASS[Typ.] PLZZ0004CA-A UPAK / UPAKV 0.050g 1.5 1.5 3.0 1.5 ± 0.1 0.44 Max 2.5 ± 0.1 4.25 Max (1.5) 0.44 Max (0.2) 0.53 Max 0.48 Max 0.8 Min φ1 0.4 4.5 ± 0.1 1.8 Max Unit: mm (2.5) SC-62 (0.4) JEITA Package Code Ordering Information Part Name 2SJ244JYTL-E 2SJ244JYTR-E Quantity 1000 pcs 1000 pcs Shipping Container Taping Taping Note: For some grades, production may be terminated. Please contact the Renesas sales office to check the state of production before ordering the product. Rev.2.00 Sep 07, 2005 page 6 of 6 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. 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