TI INA148-Q1

INA148-Q1
SBOS472A – MARCH 2009 – REVISED OCTOBER 2011
www.ti.com
±200-V COMMON-MODE VOLTAGE DIFFERENCE AMPLIFIER
Check for Samples: INA148-Q1
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
•
1
•
•
•
•
•
•
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Qualified for Automotive Applications
High Common-Mode Voltage
– 75 V at VS = 5 V
– ±200 V at VS = ±15 V
Fixed Differential Gain = 1 V/V
Low Quiescent Current: 260 µA
Wide Supply Range
– Single Supply: 2.7 V to 36 V
– Dual Supplies: ±1.35 V to ±18 V
Low Gain Error: 0.075% Max
Low Nonlinearity: 0.002% Max
High CMR: 86 dB
Surface-Mount SO-8 (D) Package
Current-Shunt Measurements
Differential Sensor Amplifiers
Line Receivers
Battery-Powered Systems
Automotive Instrumentation
Stacked-Cell Monitors
D PACKAGE
(TOP VIEW)
REF
1
8
NC
–IN
2
7
V+
+IN
3
6
OUT
V–
4
5
NC
NC – No internal connection
DESCRIPTION
The INA148 is a precision low-power unity-gain difference amplifier with a high common-mode input voltage
range. It consists of a monolithic precision bipolar operational amplifier with a thin-film resistor network.
The on-chip resistors are laser trimmed for an accurate 1-V/V differential gain and high common-mode rejection.
Excellent temperature tracking of the resistor network maintains high gain accuracy and common- mode rejection
over temperature. The INA148 operates on single or dual supplies.
The INA148 is available in a small SO-8 surface-mount package, and it is specified for operation over the
temperature range of –40°C to 125°C.
ORDERING INFORMATION (1)
PACKAGE (2)
TA
–40°C to 125°C
(1)
(2)
SOIC – D
Reel of 2500
ORDERABLE PART NUMBER
INA148QDRQ1
TOP-SIDE MARKING
148Q1
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2011, Texas Instruments Incorporated
INA148-Q1
SBOS472A – MARCH 2009 – REVISED OCTOBER 2011
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VS
Supply voltage, V+ to V–
36 V
VIN
Input voltage
tSS
Short circuit to ground duration
θJA
Package thermal impedance, junction to free air
TA
Operating free-air temperature range
TJ
Maximum operating virtual-junction temperature
Tstg
Storage temperature range
Tlead
Lead temperature range (soldering, 10 seconds)
Continuous
±200 V
Peak (0.1 second)
±500 V
Continuous
97.1°C/W
–40°C to 125°C
150°C
–65°C to 150°C
300°C
Human-Body Model (HBM)
ESD
(1)
Electrostatic discharge rating
1500 V
Machine Model (MM)
150 V
Charged-Device Model (CDM)
2000 V
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN
VS
Supply voltage
TA
Operating free-air temperature
2
Single supply
Dual supply
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MAX
2.7
36
±1.35
±18
–40
125
UNIT
V
°C
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ELECTRICAL CHARACTERISTICS
VS = ±5 V to ±15 V (dual supply), RL = 10 kΩ to ground, VREF = 0 V, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TYP
MAX
VS = ±15 V
±1
±5
VS = ±5 V
±1
±5
VOS
Input offset voltage (1)
ΔVOS/ΔT
Input offset voltage drift (1)
TA = –40°C to 125°C
±10
PSRR
Power supply ripple rejection (1)
VS = ±1.35 V to ±18 V, VCM = 0 V
±50
VCM
Common-mode voltage range
V+IN – V–IN = 0
CMRR
Common-mode rejection ratio
Vn
(2)
MIN
VCM = 0 V
–200
200
–100
80
86
VS = ±5 V, VCM = –100 V to 80 V, RS = 0 Ω
70
86
dB
2
MΩ
1
MΩ
Voltage noise
(1) (3)
f = 0.1 Hz to 10 Hz
(3)
Gain error
f = 1 kHz
Gain nonlinearity
μVp-p
nV/√Hz
±0.075
±3
±10
ppm/°C
VS = ±15 V
±0.00
1
±0.002
%FSR
VS = ±5 V
±0.00
1
VO = (V– + 0.5) to (V+ – 1.5)
Slew rate
VS = ±15 V, 10-V step
Settling time
VS = ±5 V, 6-V step
V/V
±0.01
Small signal bandwidth frequency
response
Overload recovery
17
880
1
VO = (V– + 0.5) to (V+ – 1.5)
Gain error over temperature
%FSR
kHz
1
V/μs
21
0.01%
25
0.1%
21
0.01%
25
50% input overload
μs
μs
24
RL = 100 kΩ
V– + 0.25
V+ – 1
RL = 10 kΩ
V– + 0.5
V+ – 1.5
Output voltage
IO
Output current
Short-circuit current, continuous to common
CL
Load capacitance
Stable operation
IS
Supply current
VIN = 0, IO = 0
%
100
0.1%
VO
(1)
(2)
(3)
V
Common-mode input impedance
Initial gain (1)
ts
μV/V
Differential input impedance
Voltage noise density (1)
SR
μV/°C
VS = ±5 V
70
mV
±400
VS = ±15 V
VS = ±15 V, VCM = –200 V to 200 V, RS = 0 Ω
UNIT
V
±13
mA
10
nF
±260
±300
μA
Overall difference amplifier configuration. Referred to input pins (V+IN and V–IN ), gain = 1 V/V.
Includes effects of amplifier's input bias and offset currents.
Includes effects of input current noise and thermal noise contribution of resistor network.
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ELECTRICAL CHARACTERISTICS
VS = 5 V (single supply), RL = 10 kΩ to VS/2, VREF = VS/2, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
(1) (2)
VOS
Input offset voltage
ΔVOS/ΔT
Input offset voltage drift (1)
TA = –40°C to 125°C
PSRR
Power supply ripple rejection (1)
VS = 2.7 V to 36 V, VCM = VS/2
MIN
VCM = VS/2
V+IN – V–IN = 0
CMRR
Common-mode rejection ratio
VCM = –47.5 V to 32.5 V, RS = 0 Ω
VREF = VS/2
32.5
Initial gain
f = 0.1 Hz to 10 Hz
(3)
f = 1 kHz
(1)
Gain error
Small signal bandwidth
SR
Slew rate
ts
Settling time
VS = 5 V, 3-V step
Overload recovery
50% input overload
μV/V
V
dB
2
MΩ
1
MΩ
17
μVp-p
880
nV/√Hz
V/V
±0.01
±0.075
±3
±10
±0.00
1
VO = 0.5 V to 3.5 V
mV
86
1
VO = 0.5 V to 3.5 V
Gain error over temperature
Gain nonlinearity
±400
–47.5
70
UNIT
μV/°C
75
Common-mode input impedance
Voltage noise density (1)
±5
–4
Differential input impedance
(3)
±1
±50
VREF = 0.25 V
Common-mode voltage range
Voltage noise (1)
MAX
±10
VCM
Vn
TYP
%
ppm/°C
%FSR
100
kHz
1
V/μs
0.1%
21
0.01%
25
μs
μs
13
RL = 100 kΩ
V– + 0.25
V+ – 1
RL = 10 kΩ
V– + 0.5
V+ – 1.5
VO
Output voltage
IO
Output current
Short-circuit current, continuous to common
±8
mA
CL
Load capacitance
Stable operation
10
nF
IQ
Quiescent current
VIN = 0, IO = 0
(1)
(2)
(3)
4
260
300
V
μA
Overall difference amplifier configuration. Referred to input pins (V+IN and V–IN ), gain = 1 V/V.
Includes effects of amplifier's input bias and offset currents.
Includes effects of input current noise and thermal noise contribution of resistor network.
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TYPICAL CHARACTERISTICS
VS = ±15 V, RL = 10 kΩ to common, VREF = 0 V, TA = 25°C (unless otherwise noted)
COMMON-MODE REJECTION vs FREQUENCY
GAIN vs FREQUENCY
5
100
= V S = ±15 V
VS= ±1.35 V
0
= V S = ±1.35 V
VS = ±15 V
Voltage Gain (dB)
Voltage Gain (dB)
80
–5
–10
–20
–25
60
40
20
–30
0
–35
10
100
10k
1k
100k
10
1M
100
100k
1M
Frequency (Hz)
INPUT VOLTAGE NOISE SPECTRAL DENSITY
POWER SUPPLY REJECTION vs FREQUENCY
1000
Input Noise Spectral Density (nV/ÖHz)
110
PSR+
(VS = ±18 V)
100
Power Supply Rejection (dB)
10k
1k
Frequency (Hz)
90
PSR+
(VS = ±1.35 V)
80
PSR–
(VS = ±18 V)
70
60
PSR–
(VS = ±1.35 V)
50
40
30
20
800
600
400
200
100
10
1
10
1k
100
Frequency (Hz)
10k
10
100k
100
1k
Frequency (Hz)
10k
100k
QUIESCENT CURRENT vs TEMPERATURE
VOLTAGE NOISE (RTI)
0.1 Hz to 10 Hz
290
280
VS = ±15 V
270
5 µV/div
IQ (µA)
260
250
VS = ±2.5 V
240
230
220
210
–60 –40 –20
1 s/div
0
20
40
60
80
100 120 140
Temperature (°C)
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TYPICAL CHARACTERISTICS (continued)
VS = ±15 V, RL = 10 kΩ to common, VREF = 0 V, TA = 25°C (unless otherwise noted)
SHORT-CIRCUIT CURRENT vs TEMPERATURE
LARGE-SIGNAL STEP RESPONSE
vs TEMPERATURE
20
+SC
10
125°C
5
0
125°C
–55°C
–55°C
5 V/div
Short-Circuit Current (mA)
15
–5
–10
–SC
–15
–20
–60
–40
–20
0
20
40
60
80
100
120
140
Temperature (°C)
25 µs/div
LARGE-SIGNAL STEP RESPONSE
(RL = 10 kW, CL = 10 pF)
OUTPUT VOLTAGE SWING vs RL
R L = 1 kW
R L = 1 kW
RL = 10 kW
5 V/div
5 V/div
RL = 100 kW
RL = 10 kW
RL = 100 kW
1 ms/div
25 ms/div
SMALL-SIGNAL STEP RESPONSE
(RL = 10 kW, CL = 10 pF)
LARGE-SIGNAL CAPACITIVE LOAD RESPONSE
(CL = 1 nF and 10 nF)
CL = 1 nF
CL = 10 nF
G = +1 V/V
5 V/div
50 mV/div
VIN
10 ms/div
6
100 µs/div
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TYPICAL CHARACTERISTICS (continued)
VS = ±15 V, RL = 10 kΩ to common, VREF = 0 V, TA = 25°C (unless otherwise noted)
OFFSET VOLTAGE PRODUCTION DISTRIBUTION
OFFSET VOLTAGE PRODUCTION DISTRIBUTION
24
24
VS = ±2.5 V
Percent of Amplifiers (%)
Percent of Amplifiers (%)
VS = ±15 V
18
12
6
20
16
12
8
4
OFFSET VOLTAGE DRIFT
PRODUCTION DISTRIBUTION
OFFSET VOLTAGE DRIFT
PRODUCTION DISTRIBUTION
20
20
VS = ±15 V
VS = ±2.5 V
Percent of Amplifiers (%)
15
10
5
15
10
5
30.0
18.0
24.0
12.0
6.0
0.0
–6.0
–12.0
–30.0
30.0
24.0
18.0
12.0
6.0
0.0
–6.0
–12.0
–18.0
–24.0
–30.0
Offset Voltage Drift, RTI (µV/°C)
–18.0
0
0
–24.0
Offset Voltage Drift, RTI (µV/°C)
GAIN DRIFT PRODUCTION DISTRIBUTION
GAIN DRIFT PRODUCTION DISTRIBUTION
40
40
VS = ±2.5 V
Percent of Amplifiers (%)
VS = ±15 V
30
20
10
30
20
10
10.0
8.0
4.0
2.0
0.0
–2.0
–4.0
–6.0
–8.0
10.0
8.0
6.0
4.0
2.0
0.0
–2.0
–4.0
–6.0
–8.0
–10.0
–10.0
0
0
6.0
Percent of Amplifiers (%)
5.0
3.0
Offset Voltage, RTI (mV)
Offset Voltage, RTI (mV)
Percent of Amplifiers (%)
4.0
2.0
1.0
0.0
–1.0
–2.0
–3.0
–5.0
5.0
4.0
3.0
2.0
1.0
0.0
–1.0
–2.0
–3.0
–4.0
–5.0
–4.0
0
0
Gain Drift (ppm/°C)
Gain Drift (ppm/°C)
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TYPICAL CHARACTERISTICS (continued)
VS = ±15 V, RL = 10 kΩ to common, VREF = 0 V, TA = 25°C (unless otherwise noted)
INVERTING INPUT
50% OVERLOAD RECOVERY TIME
NON-INVERTING INPUT
50% OVERLOAD RECOVERY TIME
VS = ±15V
VS = ±15 V
V+IN
0V
V–IN
VOUT
5 V/div
5 V/div
VOUT
0V
0V
5 ms/div
5 ms/div
8
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APPLICATION INFORMATION
The INA148 is a unity-gain difference amplifier with a high common-mode input voltage range. A basic diagram
of the circuit and pin connections is shown in Figure 1.
+VS
0.1 µF
7
V–IN
2
1 MW
50 kW
50 kW
VO = (V+IN – V–IN)
2.7778 kW
6
A1
V+IN
3
1 MW
VO
52.6316 kW
INA148
4
0.1 µF
1
–VS
Figure 1. Basic Circuit Connections
To achieve its high common-mode voltage range, the INA148 features a precision laser-trimmed thin-film resistor
network with a 20:1 input voltage divider ratio. High input voltages are thereby reduced in amplitude, allowing the
internal operational amplifier (op amp) to "see" input voltages that are within its linear operating range. A "Tee"
network in the op amp feedback network places the amplifier in a gain of 20 V/V, thus restoring the circuit's
overall gain to unity (1 V/V).
External voltages can be summed into the amplifier's output by using the REF pin, making the differential
amplifier a highly versatile design tool. Voltages on the REF pin also influence the INA148's common-mode
voltage range.
In accordance with good engineering practice for linear integrated circuits, the INA148's power-supply bypass
capacitors should be connected as close to pins 4 and 7 as practicable. Ceramic or tantalum types are
recommended for use as bypass capacitors.
The input impedances are unusually high for a difference amplifier and this should be considered when routing
input signal traces on a PC board. Avoid placing digital signal traces near the difference amplifier's input traces to
minimize noise pickup.
Operating Voltage
The INA148 is specified for ±15-V and ±5-V dual supplies and 5-V single supplies. The INA148 can be operated
with single or dual supplies with excellent performance.
The INA148 is fully characterized for supply voltages from ±1.35 V to ±18 V and over temperatures of –40°C to
125°C. Parameters that vary significantly with operating voltage, load conditions, or temperature are shown in the
Typical Characteristics section.
Gain Equation
An internal on-chip resistor network sets the overall differential gain of the INA148 to precisely 1 V/V. Output is
accordance with Equation 1.
VOUT = (V+IN – V–IN) + VREF
(1)
(1)
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Common-Mode Range
The 20:1 input resistor ratio of the INA148 provides an input common-mode range that extends well beyond its
power supply rails.
The exact input voltage range depends on the amplifier's power-supply voltage and the voltage applied to the
REF terminal (pin 1). Typical input voltage ranges at different power supply voltages can be found in the
applications circuits section.
Offset Trim
The INA148 is laser-trimmed for low offset voltage and drift. Most applications require no external offset
adjustment.
Because a voltage applied to the reference (REF) pin (pin 1) is summed directly into the amplifier's output signal,
this technique can be used to null the amplifier's input offset voltage. Figure 2 shows an optional circuit for
trimming the offset voltage.
+VS
7
2
V–IN
1 MW
50 kW
50 kW
VO = (V+IN – V–IN)
2.7778 kW
6
A1
190 W
V+IN
3
VO
52.6316 kW
1 MW
INA148
4
–VS
VREF 1
+15 V
10 kW
10 kW
10 W
±15-mV Offset Trim Range, RTI
–15 V
Figure 2. Optional Offset Trim Circuit
To maintain high common-mode rejection (CMR), the source impedance of any signal applied to the REF
terminal should be very low (≤5 Ω).
A source impedance of only 10 Ω at the REF pin reduces the INA148's CMR to approximately 74 dB. High CMR
can be restored if a resistor is added in series with the amplifier's positive input terminal (pin 3). This resistor
should be 19 times the source impedance that drives the REF pin. For example, if the REF pin sees a source
impedance of 10 Ω, a resistor of 190 Ω should be added in series with pin 3.
Preferably, the offset trim voltage applied to the REF pin should be buffered with an amplifier such as an
OPA237 (see Figure 3). In this case, the op amp output impedance is low enough that no external resistor is
needed to maintain the INA148's excellent CMR.
10
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+15 V
7
2
V–IN
1 MW
50 kW
50 kW
VO = (V+IN – V–IN)
2.7778 kW
6
A1
3
V+IN
VO
52.6316 kW
1 MW
INA148
4
VREF 1
+15 V
–15 V
OPA237
100 kW
100 kW
±15-mV Offset Trim Range, RTI
100 W
–15 V
Figure 3. Preferred Offset Trim Circuit
Input Impedance
The input resistor network determines the impedance of each of the INA148 inputs. It is approximately 1 MΩ.
Unlike an instrumentation amplifier, signal source impedances at the two input terminals must be nearly equal to
maintain good common-mode rejection.
A mismatch between the two inputs' source impedances causes a differential amplifier's common-mode rejection
to be degraded. With a source impedance imbalance of only 500 Ω, CMR can fall to approximately 66 dB.
Figure 4 shows a common application—measuring power supply current through a shunt resistor (RS). A shunt
resistor creates an unbalanced source resistance condition that can degrade a differential amplifier's common
mode rejection.
+15 V
7
Load
2
1 MW
50 kW
50 kW
IL
VO = I L × R S
2.7778 kW
6
RC
VO
A1
RS
3
52.6316 kW
1 MW
INA148
VCM
200 V
4
1
–15 V
Make RC = RS if RS ³ 100 W
Figure 4. Shunt-Resistor Current Measurement Circuit
Unless the shunt resistor is less than approximately 100 Ω, an additional equal compensating resistor (RC) is
recommended to maintain input balance and high CMR.
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Source impedances (or shunts) greater than 5 kΩ are not recommended, even if they are "perfectly"
compensated. This is because the internal resistor network is laser-trimmed for accurate voltage divider ratios,
but not necessarily to absolute values. Input resistors are shown as 1 MΩ, however, this is only their nominal
value.
In practice, the input resistors' absolute values may vary by as much as 30%. The two input resistors match to
about 5%, so adding compensating resistors greater than 5 kΩ can cause a serious mismatch in the resulting
resistor network voltage divider ratios, thus degrading CMR.
Attempts to extend the INA148 input voltage range by adding external resistors is not recommended for the
reasons described in the previous paragraph. CMR suffers serious degradation unless the resistors are carefully
trimmed for CMR and gain. This is an iterative adjustment and can be tedious and time consuming.
Typical Application Circuits
Figure 5 through Figure 9 show typical application circuits for the INA148.
+15 V
C1
7
(1)
4.7 µF
250 V
V–IN
2
1 MW
50 kW
50 kW
2.7778 kW
VO = (V+IN – V–IN)
6
VCM = 200 Vpk
A1
VO
C2
(1)
4.7 µF
250 V
V+IN
3
52.6316 kW
1 MW
INA148
4
1
Typical CMR: 50 Hz = 59 dB
60 Hz = 61 dB
400 Hz = 78 dB
–15 V
NOTE: (1) Metallized polypropylene, ±5% tolerance.
Figure 5. AC-Coupled Difference Amplifier
+VS
fC » 0.75 Hz HPF
7
V–IN
2
U1
1 MW
50 kW
50 kW
VO = (V+IN – V–IN) + VREF
2.7778 kW
6
VO
A1
V+IN
3
1 MW
52.6316 kW
1 MW
INA148
1
4
0.22 µF
–VS
+VS
U2:
OPA132 for VS = ±5 V to ±15 V
OPA340 for VS = ±2.5 V
7
6
U2
4
2
3
VREF
–VS
Figure 6. Quasi-AC-Coupled Differential Amplifier
12
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+5 V
0.1 µF
7
2
V–IN
1 MW
50 kW
50 kW
VO = (V+IN – V –IN) + 1.235V
2.7778 kW
6
VCM = –23 V to +56 V
3
V+IN
VO
A1
52.6316 kW
1 MW
INA148
4
1
34 kW
5W
+5 V
10 µF
+
REF1004-1.2
Figure 7. Single-Supply Differential Amplifier
IC
RS
0.01 W
+
0.1 µF
–
28-V
Supply
7
2
1 MW
50 kW
50 kW
2.7778 kW
VO = 1.235 V + (IC × RS)
6
A1
3
VO
52.6316 kW
1 MW
271 kW
INA148
4
1
10 µF
5W
+
REF1004-1.2
Figure 8. Battery Monitor Circuit
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Product Folder Link(s): INA148-Q1
13
INA148-Q1
SBOS472A – MARCH 2009 – REVISED OCTOBER 2011
www.ti.com
0.47 µF ceramic (all)
RS
50 mV
shunt
I
6 +15
+VISO
+VS
IN5245
VCM = –200V max
5
1 kW
200 kW
0.1 µF
+VISO
2
3
O
7
–VISO
2
–15
DCP011515D
7
OPA277
C
IN5245
+15 V
+15 V
1
6
4
7
2
1 MW
50 kW
50k W
–VISO
2.7778 kW
6 VO
A1
–50-mV Input = –10-V Output
3
52.6316 kW
1 MW
INA148
4
0.1 µF
1
–15 V
Figure 9. 50-mV Current-Shunt Amplifier with ±200-V Common-Mode Voltage Range
SPACER
REVISION HISTORY
Changes from Original (March 2009) to Revision A
•
14
Page
Features Bullet From: Low Quiescent Current: 260 mA To: Low Quiescent Current: 260 µA ............................................. 1
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Product Folder Link(s): INA148-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
25-Oct-2011
PACKAGING INFORMATION
Orderable Device
INA148QDRQ1
Status
(1)
Package Type Package
Drawing
ACTIVE
SOIC
D
Pins
Package Qty
8
2500
Eco Plan
(2)
Green (RoHS
& no Sb/Br)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
CU NIPDAU Level-3-260C-168 HR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF INA148-Q1 :
• Catalog: INA148
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
INA148QDRQ1
Package Package Pins
Type Drawing
SOIC
D
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
12.4
Pack Materials-Page 1
6.4
B0
(mm)
K0
(mm)
P1
(mm)
5.2
2.1
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
INA148QDRQ1
SOIC
D
8
2500
367.0
367.0
35.0
Pack Materials-Page 2
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