PD - 97395B IRF6718L2TRPbF IRF6718L2TR1PbF l l l l l l RoHS Compliant Containing No Lead and Bromide Dual Sided Cooling Compatible Ultra Low Package Inductance Very Low RDS(ON) for Reduced Conduction Losses Optimized for Active O-Ring / Efuse Applications Compatible with existing Surface Mount Techniques DirectFET Power MOSFET Typical values (unless otherwise specified) VDSS VGS S2 SB Qg tot 64nC Qgd Qgs2 Qrr Qoss Vgs(th) 20nC 9.4nC 67nC 50nC 1.9V DirectFET ISOMETRIC L6 M2 RDS(on) 25V max ±20V max 0.50mΩ@10V 1.0mΩ@4.5V Applicable DirectFET Outline and Substrate Outline S1 RDS(on) M4 L4 L8 L6 Description The IRF6718L2TRPbF combines the latest HEXFET® Power MOSFET Silicon technology with the advanced DirectFETTM packaging to achieve the lowest on-state resistance in a package that has the footprint of a D-pak. The DirectFET package is compatible with existing layout geometries used in power applications, PCB assembly equipment and vapor phase, infra-red or convection soldering techniques, when application note AN-1035 is followed regarding the manufacturing methods and processes. The DirectFET package allows dual sided cooling to maximize thermal transfer in power systems. The IRF6718L2TRPbF has extremely low Si Rdson coupled with ultra low package resistance to minimize conduction losses. The IRF6718L2TRPbF has been optimized for parameters that are critical in reliable operation on Active O-Ring / Efuse / hot swap applications. Absolute Maximum Ratings Parameter Drain-to-Source Voltage Gate-to-Source Voltage Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V VGS ID @ TA = 25°C ID @ TA = 70°C ID @ TC = 25°C IDM EAS IAR g Pulsed Drain Current Single Pulse Avalanche Energy Avalanche Current g h Typical RDS(on) (mΩ) 4 ID = 61A 3 2 T J = 125°C 1 T J = 25°C 0 2 4 6 8 e e f 10 VGS, Gate -to -Source Voltage (V) Fig 1. Typical On-Resistance vs. Gate Voltage VGS, Gate-to-Source Voltage (V) VDS Max. Units 25 ±20 61 52 270 490 530 49 V A mJ A 14.0 ID= 49A 12.0 VDS= 20V VDS= 13V 10.0 8.0 6.0 4.0 2.0 0.0 0 20 40 60 80 100 120 140 160 180 QG Total Gate Charge (nC) Fig 2. Typical Total Gate Charge vs Gate-to-Source Voltage Notes: Click on this section to link to the appropriate technical paper. Click on this section to link to the DirectFET Website. Surface mounted on 1 in. square Cu board, steady state. www.irf.com TC measured with thermocouple mounted to top (Drain) of part. Repetitive rating; pulse width limited by max. junction temperature. Starting TJ = 25°C, L = 0.44mH, RG = 25Ω, IAS = 49A. 1 01/26/2010 IRF6718L2TR/TR1PbF Static @ TJ = 25°C (unless otherwise specified) Parameter Min. Conditions Typ. Max. Units VGS = 0V, ID = 250µA BVDSS Drain-to-Source Breakdown Voltage 25 ––– ∆ΒVDSS/∆TJ RDS(on) Breakdown Voltage Temp. Coefficient ––– 11 Static Drain-to-Source On-Resistance ––– 0.50 ––– 1.0 VGS(th) Gate Threshold Voltage 1.35 1.90 V mV/°C Reference to 25°C, ID = 1mA 0.70 mΩ VGS = 10V, ID = 61A i VGS = 4.5V, ID = 49A i 1.4 VDS = VGS, ID = 150µA 2.35 V ∆VGS(th)/∆TJ IDSS Gate Threshold Voltage Coefficient ––– -7.6 ––– mV/°C Drain-to-Source Leakage Current ––– ––– 1.0 µA ––– ––– 150 IGSS gfs Qg ––– ––– Gate-to-Source Forward Leakage ––– ––– 100 Gate-to-Source Reverse Leakage ––– ––– -100 Forward Transconductance 820 ––– ––– VDS = 20V, VGS = 0V VDS = 20V, VGS = 0V, TJ = 125°C nA VGS = 20V VGS = -20V S VDS = 13V, ID = 49A Total Gate Charge ––– 64 96 Qgs1 Pre-Vth Gate-to-Source Charge ––– 18 ––– Qgs2 Post-Vth Gate-to-Source Charge ––– 9.4 ––– Qgd Gate-to-Drain Charge ––– 20 ––– ID = 49A Qgodr Gate Charge Overdrive Switch Charge (Qgs2 + Qgd) ––– 16.6 ––– See Fig. 18 Qsw ––– 29.4 ––– Qoss Output Charge ––– 50 ––– nC RG Gate Resistance ––– 0.90 ––– Ω td(on) Turn-On Delay Time ––– 67 ––– VDD = 13V, VGS = 4.5Vi ID = 49A tr Rise Time ––– 140 ––– td(off) Turn-Off Delay Time ––– 47 ––– tf Fall Time ––– 53 ––– Ciss Input Capacitance ––– 8910 ––– Coss Output Capacitance ––– 2310 ––– Crss Reverse Transfer Capacitance VDS = 13V nC ns VGS = 4.5V VDS = 16V, VGS = 0V RG= 6.8Ω VGS = 0V pF VDS = 13V ƒ = 1.0MHz ––– 1115 ––– Min. Typ. Max. Units ––– ––– 61 ––– ––– 490 integral reverse Diode Characteristics Parameter IS Continuous Source Current (Body Diode) ISM Pulsed Source Current Conditions MOSFET symbol A showing the VSD Diode Forward Voltage ––– ––– 1.0 V p-n junction diode. TJ = 25°C, IS = 49A, VGS = 0V i trr Reverse Recovery Time ––– 39 59 ns TJ = 25°C, IF = 49A Qrr Reverse Recovery Charge ––– 67 100 nC di/dt = 200A/µs i (Body Diode)g Notes: Repetitive rating; pulse width limited by max. junction temperature. Pulse width ≤ 400µs; duty cycle ≤ 2%. 2 www.irf.com IRF6718L2TR/TR1PbF Absolute Maximum Ratings Max. Units 4.3 3.0 83 270 -55 to + 175 W Parameter e e f Power Dissipation Power Dissipation Power Dissipation Peak Soldering Temperature Operating Junction and Storage Temperature Range PD @TA = 25°C PD @TA = 70°C PD @TC = 25°C TP TJ TSTG °C Thermal Resistance e j k fl RθJA RθJA RθJA RθJC RθJ-PCB Parameter Junction-to-Ambient Junction-to-Ambient Junction-to-Ambient Junction-to-Case Junction-to-PCB Mounted Linear Derating Factor e Typ. Max. Units ––– 12.5 20 ––– 1.0 35 ––– ––– 1.8 ––– °C/W 0.029 W/°C 100 Thermal Response ( Z thJA ) 10 1 D = 0.50 0.20 0.10 0.05 0.02 0.01 0.1 τJ 0.01 0.001 0.0001 1E-006 R1 R1 τJ τ1 R2 R2 R3 R3 R4 R4 τ1 τ2 τ2 τ3 τ4 τ3 Ci= τi/Ri Ci= τi/Ri 0.0001 τ4 τA τi (sec) 12.2942 18.10679 14.4246 2.626824 2.07265 0.007811 6.20859 0.239314 Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthja + Tc SINGLE PULSE ( THERMAL RESPONSE ) 1E-005 Ri (°C/W) τA 0.001 0.01 0.1 1 10 100 1000 t1 , Rectangular Pulse Duration (sec) Fig 3. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient (At lower pulse widths ZthJA & ZthJC are combined) Notes: Mounted on minimum footprint full size board with metalized Surface mounted on 1 in. square Cu board, steady state. TC measured with thermocouple incontact with top (Drain) of part. back and with small clip heatsink. Rθ is measured at TJ of approximately 90°C. Used double sided cooling, mounting pad with large heatsink. Surface mounted on 1 in. square Cu board (still air). www.irf.com Mounted on minimum footprint full size board with metalized back and with small clip heatsink. (still air) 3 IRF6718L2TR/TR1PbF 1000 1000 100 BOTTOM TOP ID, Drain-to-Source Current (A) ID, Drain-to-Source Current (A) TOP VGS 10V 5.0V 4.5V 4.0V 3.5V 3.0V 2.8V 2.5V BOTTOM 100 10 1 2.5V ≤60µs PULSE WIDTH 0.1 1 10 100 0.1 1000 1 10 100 1000 V DS, Drain-to-Source Voltage (V) VDS, Drain-to-Source Voltage (V) Fig 4. Typical Output Characteristics Fig 5. Typical Output Characteristics 1000 2.0 VDS = 15V ≤60µs PULSE WIDTH ID = 61A Typical RDS(on) (Normalized) ID, Drain-to-Source Current (A) Tj = 175°C 10 0.1 100 10 T J = 175°C T J = 25°C T J = -40°C 1 0.1 V GS = 10V V GS = 4.5V 1.5 1.0 0.5 1 2 3 4 5 -60 -40 -20 0 20 40 60 80 100120140160180 T J , Junction Temperature (°C) VGS, Gate-to-Source Voltage (V) Fig 7. Normalized On-Resistance vs. Temperature Fig 6. Typical Transfer Characteristics 100000 0.90 VGS = 0V, f = 1 MHZ C iss = C gs + C gd, C ds SHORTED C rss = C gd Top Typical RDS(on) ( mΩ) C oss = C ds + C gd C, Capacitance(pF) ≤60µs PULSE WIDTH 2.5V Tj = 25°C Ciss 10000 Coss Crss 1000 0.80 Bottom T J = 25°C Vgs = 6.0V Vgs = 8.0V Vgs = 10V Vgs = 12V Vgs = 14V Vgs = 16V Vgs = 18V 0.70 0.60 0.50 100 1 10 100 VDS, Drain-to-Source Voltage (V) Fig 8. Typical Capacitance vs.Drain-to-Source Voltage 4 VGS 10V 5.0V 4.5V 4.0V 3.5V 3.0V 2.8V 2.5V 0 50 100 150 200 ID, Drain Current (A) Fig 9. Typical On-Resistance vs. Drain Current and Gate Voltage www.irf.com IRF6718L2TR/TR1PbF 10000 T J = 175°C 100 ID, Drain-to-Source Current (A) ISD, Reverse Drain Current (A) 1000 T J = 25°C T J = -40°C 10 1 OPERATION IN THIS AREA LIMITED BY R DS(on) 1000 100µsec 100 1msec 10msec 10 DC 1 T A = 25°C T J = 175°C Single Pulse VGS = 0V 0.1 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0.01 VSD, Source-to-Drain Voltage (V) Fig 10. Typical Source-Drain Diode Forward Voltage 10.00 100.00 Fig 11. Maximum Safe Operating Area Typical VGS(th) Gate threshold Voltage (V) 60 50 40 30 20 10 0 25 50 75 100 125 150 2.5 2.0 1.5 ID = 150µA ID = 250µA 1.0 ID = 1.0mA ID = 1.0A 0.5 0.0 -75 -50 -25 0 175 25 50 75 100 125 150 175 200 T J , Temperature ( °C ) T C , Case Temperature (°C) Fig 12. Maximum Drain Current vs. Case Temperature 400 Fig 13. Typical Threshold Voltage vs. Junction Temperature 2400 EAS , Single Pulse Avalanche Energy (mJ) Gfs, Forward Transconductance (S) 1.00 3.0 70 ID, Drain Current (A) 0.10 VDS, Drain-to-Source Voltage (V) ID 2.9A 4.6A BOTTOM 49A TOP 2000 300 T J = 175°C 1600 T J = 25°C 200 1200 100 V DS = 10V 380µs PULSE WIDTH 2 0 800 400 0 0 20 40 60 80 ID,Drain-to-Source Current (A) 100 25 50 75 100 125 150 175 Starting T J , Junction Temperature (°C) Fig 14. Typ. Forward Transconductance vs. Drain Current Fig 15. Maximum Avalanche Energy vs. Drain Current www.irf.com 5 IRF6718L2TR/TR1PbF 1000 Allowed avalanche Current vs avalanche pulsewidth, tav, assuming DTj = 150°C and Tstart =25°C (Single Pulse) Duty Cycle = Single Pulse Avalanche Current (A) 100 10 0.01 1 0.1 0.05 0.10 Allowed avalanche Current vs avalanche pulsewidth, tav, assuming ∆ Tj = 25°C and Tstart = 150°C. 0.01 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 1.0E+00 1.0E+01 tav (sec) Fig 16. Typical Avalanche Current vs.Pulsewidth EAR , Avalanche Energy (mJ) 600 Single Pulse ID = 49A 500 400 300 200 100 0 25 50 75 100 125 150 Starting T J , Junction Temperature (°C) Fig 17. Maximum Avalanche Energy vs. Temperature 6 175 Notes on Repetitive Avalanche Curves , Figures 16, 17: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 19a, 19b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25°C in Figure 16, 17). tav = Average time in avalanche. D = Duty cycle in avalanche = tav ·f ZthJC(D, tav) = Transient thermal resistance, see figure 11) PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC Iav = 2DT/ [1.3·BV·Zth] EAS (AR) = PD (ave)·tav www.irf.com IRF6718L2TR/TR1PbF Id Vds Vgs L VCC DUT 0 20K 1K Vgs(th) S Qgodr Fig 18a. Gate Charge Test Circuit Qgs2 Qgs1 Qgd Fig 18b. Gate Charge Waveform V(BR)DSS tp 15V DRIVER L VDS D.U.T RG + V - DD IAS 20V I AS 0.01Ω tp Fig 19a. Unclamped Inductive Test Circuit VDS VGS RG A RD Fig 19b. Unclamped Inductive Waveforms VGS 90% D.U.T. + - VDD V10V GS Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 % Fig 20a. Switching Time Test Circuit www.irf.com 10% VDS td(off) tf td(on) tr Fig 20b. Switching Time Waveforms 7 IRF6718L2TR/TR1PbF D.U.T Driver Gate Drive + - • • • • D.U.T. ISD Waveform Reverse Recovery Current + di/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test VDD P.W. Period * RG D= VGS=10V Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer - Period P.W. + + Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt Re-Applied Voltage Body Diode VDD Forward Drop Inductor Current Inductor Curent - ISD Ripple ≤ 5% * VGS = 5V for Logic Level Devices Fig 19. Diode Reverse Recovery Test Circuit for N-Channel HEXFET® Power MOSFETs DirectFET Board Footprint, L6 (Large Size Can). Please see AN-1035 for DirectFET assembly details and stencil and substrate design recommendations G = GATE D = DRAIN S = SOURCE D D D 8 D S S S S S S G D D www.irf.com IRF6718L2TR/TR1PbF DirectFET Outline Dimension, L6 Outline (LargeSize Can). Please see AN-1035 for DirectFET assembly details and stencil and substrate design recommendations DIMENSIONS METRIC MAX CODE MIN 9.15 A 9.05 7.10 B 6.85 6.00 C 5.90 0.65 D 0.55 0.62 E 0.58 1.22 F 1.18 G 0.98 1.02 0.77 H 0.73 0.42 J 0.38 1.47 K 1.34 2.69 L 2.52 M 0.616 0.676 N 0.020 0.080 0.18 P 0.09 IMPERIAL MIN MAX 0.356 0.360 0.270 0.280 0.232 0.236 0.022 0.026 0.023 0.024 0.046 0.048 0.015 0.017 0.029 0.030 0.015 0.017 0.053 0.058 0.099 0.106 0.0235 0.0274 0.0008 0.0031 0.003 0.007 DirectFET Part Marking GATE MARKING LOGO PART NUMBER BATCH NUMBER DATE CODE Line above the last character of the date code indicates "Lead-Free" www.irf.com 9 IRF6718L2TR/TR1PbF DirectFET Tape & Reel Dimension (Showing component orientation). NOTE: Controlling dimensions in mm Std reel quantity is 4000 parts. (ordered as IRF6718L2PBF). REEL DIMENSIONS STANDARD OPTION (QTY 4000) IMPERIAL METRIC MIN CODE MAX MIN MAX 12.992 N.C A 330.0 N.C 0.795 B 20.2 N.C N.C 0.504 C 12.8 0.520 13.2 0.059 D 1.5 N.C N.C E 3.937 100.0 N.C N.C F N.C N.C 0.889 22.4 G 0.646 16.4 0.724 18.4 H 0.626 15.9 0.724 18.4 016'%10641..+0) &+/'05+105+0// &+/'05+105 +/2'4+#. /'64+% /+0 /#: %1&' /+0 /#: # 0% 0% $ % & ' ( 0% ) 0% * Note: For the most current drawing please refer to IR website at http://www.irf.com/package Data and specifications subject to change without notice. This product has been designed and qualified to MSL1 rating for the Consumer market. Additional storage requirement details for DirectFET products can be found in application note AN1035 on IRs Web site. Qualification Standards can be found on IR’s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.01/2010 10 www.irf.com