INTEGRATED CIRCUITS DATA SHEET TEA1210TS High efficiency, high current DC/DC converter Preliminary specification File under Integrated Circuits, IC03 1999 Mar 08 Philips Semiconductors Preliminary specification High efficiency, high current DC/DC converter TEA1210TS FEATURES GENERAL DESCRIPTION • Fully integrated DC/DC converter circuit, featuring internal very low RDSon power MOSFETs The TEA1210TS is a fully integrated DC/DC converter. Efficient, compact and dynamic power conversion is achieved using a novel digitally controlled concept like Pulse Width Modulation (PWM) or Pulse Frequency Modulation (PFM), integrated low R CMOS power switches with low parasitic capacitances, and fully synchronous rectification. • Up-or-down conversion • Start-up from 1.85 V input voltage • Adjustable output voltage • High efficiency over large load range • 600 kHz switching frequency The device operates at 600 kHz switching frequency which enables the use of external components with minimum size. The switching frequency can be locked to an external high-frequency clock. • Low quiescent power consumption • Synchronizing with external clock • Two selectable current limits for efficient battery use in case of dynamic loads Optionally, the device can be kept in the Pulse Width Modulation (PWM) mode regardless of the load applied. • Up to 100% duty cycle in down mode Deadlock is prevented by an on-chip undervoltage lockout circuit. • Undervoltage lockout • Shut-down function Two selectable current limits in upconversion mode enable efficient battery use even at highly dynamic loads such as cellular phone electronics. • 16-pin small body SSOP16 package. APPLICATIONS • Cellular phones, Personal Digital Assistants (PDAs) and others • Supply voltage source for low-voltage chip sets • Portable computers • Battery backup supplies. ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TEA1210TS 1999 Mar 08 SSOP16 DESCRIPTION plastic shrink small outline package; 16 leads; body width 4.4 mm 2 VERSION SOT369-1 Philips Semiconductors Preliminary specification High efficiency, high current DC/DC converter TEA1210TS QUICK REFERENCE DATA Tamb = −40 to +80 °C; all voltages measured with respect to ground; positive currents flow into the IC; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Voltage levels UPCONVERSION; pin U/D = LOW VI input voltage VI(start) − 5.50 V VO output voltage 2.90 − 5.50 V VI(start) start-up input voltage 1.20 1.60 1.85 V VI(uvlo) undervoltage lockout input voltage 1.50 2.10 2.70 V IL < 200 mA DOWNCONVERSION; pin U/D = HIGH VI input voltage 2.90 − 5.50 V VO output voltage 1.30 − 5.50 V Vfb feedback input voltage 1.20 1.25 1.30 V ∆Vwindow output voltage window PWM mode 1.5 2.0 3.0 % VI =2.40 V; VO = 3.60 V 100 125 150 µA − 2 10 µA −12 − +12 % GENERAL Current levels Iq quiescent current on pins LX Ishdwn current in shut-down mode ∆Ilim(up) current limit deviation in up mode Ilim(down) current limit in down mode ILX maximum continuous current on pins LX Ilim(up) set to 2.0 A 4.8 A Tamb = 60 °C − − 1.8 A Power MOSFETs RDSon(N) drain-to-source on-state resistance NFET Tj = 27 °C − 56 63 mΩ RDSon(P) drain-to-source on-state resistance PFET Tj = 27 °C − 68 77 mΩ efficiency upconversion VI = 2.4 V; VO = 3.6 V; Tamb = 20 °C IL = 1 mA 83 86 − % IL = 100 mA 90 93 − % IL = 500 mA 92 94 − % IL = 1.5 A; not continual 84 86 − % 480 600 720 kHz 9 13 20 MHz − 25 − µs Efficiency η Timing fsw switching frequency fsync synchronization clock input frequency tres response time 1999 Mar 08 PWM mode from standby to Po(max) 3 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 7 I/V CONVERTER START-UP CIRCUIT TEA1210TS 10 LPF ILIMSEL UPOUT INTERNAL SUPPLY sense FET SWITCH ILIML 1, 16 I/V CONVERTER 11 4 N-type POWER FET TEMPERATURE PROTECTION TIME COUNTER sense FET 13 MHz OSCILLATOR 8, 9 15 CONTROL LOGIC AND MODE GEARBOX CURRENT LIMIT COMPARATORS SYNC GATE BAND GAP REFERENCE FB Philips Semiconductors P-type POWER FET 4, 5, 12, 13 High efficiency, high current DC/DC converter ILIMH BLOCK DIAGRAM ndbook, full pagewidth 1999 Mar 08 LX DIGITAL CONTROLLER 2 3 SYNC SHDWN 6 14 MGR725 GND PWM U/D Preliminary specification TEA1210TS Fig.1 Block diagram. Philips Semiconductors Preliminary specification High efficiency, high current DC/DC converter PINNING FUNCTIONAL DESCRIPTION SYMBOL PIN UPOUT 1, 16 output voltage in up mode; input voltage in down mode SYNC 2 synchronization clock input SHDWN 3 shut-down input LX TEA1210TS Control mechanism DESCRIPTION The TEA1210TS DC/DC converter is able to operate in PFM (discontinuous conduction) or PWM (continuous conduction) operating mode. All switching actions are completely determined by a digital control circuit which uses the output voltage level as its control input. This novel digital approach enables the use of a new pulse width and frequency modulation scheme, which ensures optimum power efficiency over the complete operating range of the converter. 4, 5, 12, 13 inductor connection U/D 6 up-or-down mode selection input; active LOW for up mode ILIMH 7 current limiting resistor 1 connection GND 8, 9 ground ILIML 10 current limiting resistor 2 connection ILIMSEL 11 current limiting selection input PWM 14 PWM-only mode selection input FB 15 feedback input When high output power is requested, the device will operate in PWM (continuous conduction) operating mode. This results in minimum AC currents in the circuit components and hence optimum efficiency, cost and EMC. In this operating mode, the output voltage is allowed to vary between two predefined voltage levels. As long as the output voltage stays within this so-called window, switching continues in a fixed pattern. When the output voltage reaches one of the window borders, the digital controller immediately reacts by adjusting the pulse width and inserting a current step in such a way that the output voltage stays within the window with higher or lower current capability. This approach enables very fast reaction to load variations. Figure 3 shows the converter’s response to a sudden load increase. The upper trace shows the output voltage. The ripple on top of the DC level is a result of the current in the output capacitor, which changes in sign twice per cycle, times the capacitor’s internal Equivalent Series Resistance (ESR). After each ramp-down of the inductor current, i.e. when the ESR effect increases the output voltage, the converter determines what to do in the next cycle. As soon as more load current is taken from the output the output voltage starts to decay. handbook, halfpage UPOUT 1 16 UPOUT SYNC 2 15 FB SHDWN 3 14 PWM LX 4 13 LX TEA1210TS LX 5 12 LX U/D 6 11 ILIMSEL ILIMH 7 10 ILIML Fig.2 Pin configuration. When the output voltage becomes lower than the low limit of the window, a corrective action is taken by a ramp-up of the inductor current during a much longer time. As a result, the DC current level is increased and normal PWM control can continue. The output voltage (including ESR effect) is again within the predefined window. For all possible applications, the following groups of pins must be connected together: Figure 4 depicts the spread of the output voltage window. The absolute value is most dependent on spread, while the actual window size is not affected. For one specific device, the output voltage will not vary more than 2% typically. GND 8 9 GND MGR726 • Pins 4, 5, 12 and 13 (pins LX) In low output power situations, the TEA1210TS will switch over to PFM (discontinuous conduction) operating mode in case the PWM-only mode is not active. • Pins 1 and 16 (pins UPOUT) • Pins 8 and 9 (pins GND). 1999 Mar 08 5 Philips Semiconductors Preliminary specification High efficiency, high current DC/DC converter In the PFM mode, regulation information from earlier PWM operating modes is used. This results in optimum inductor peak current levels in the PFM mode, which are slightly larger than the inductor ripple current in the PWM mode. As a result, the transition between PFM and PWM mode is optimum under all circumstances. In the PFM mode, TEA1210TS regulates the output voltage to the high window limit shown in Fig.3. that the inductor current does not fall below zero. In this way, the achieved efficiency is higher than in standard PWM-controlled converters. Start-up Start-up from low input voltage in boost mode is realized by an independent start-up oscillator, which starts switching the N-type power MOSFET as soon as the voltage on pins UPOUT is measured to be sufficiently high. The switch actions of the start-up oscillator will increase the output voltage. As soon as the output voltage is high enough for normal regulation, the digital control system takes over the control of the power MOSFETs. Synchronous rectification For optimum efficiency over the whole load range, synchronous rectifiers inside the TEA1210TS ensure that during the whole second switching phase, all inductor current will flow through the low-ohmic power MOSFETs. Special circuitry is included which detects that the inductor current reaches zero. Following this detection, the digital controller switches off the power MOSFET and proceeds regulation. Undervoltage lockout As a result of too high load or disconnection of the input power source, the output voltage can drop so low that normal regulation cannot be guaranteed. In that case, the device switches back to start-up mode. If the output voltage drops down even further, switching is stopped completely. PWM-only mode When pin PWM is pulled to HIGH-level in the upconversion mode, the TEA1210TS will use PWM regulation independent of the load applied. As a result, the switching frequency does not vary over the whole load range. Furthermore, the P-type power MOSFET is always on when the input voltage exceeds the target output voltage. The internal synchronous rectifier still takes care load increase handbook, full pagewidth TEA1210TS Shut-down When the shut-down input is made HIGH, the converter disables both switches and power consumption is reduced to a few microamperes. start corrective action Vo high window limit low window limit time IL time Fig.3 Response to load increase. 1999 Mar 08 6 MGK925 Philips Semiconductors Preliminary specification High efficiency, high current DC/DC converter In the upconversion mode, the first current limit is set by an external resistor connected between the pins ILIMH and UPOUT and the second current limit is set by an external resistor connected between the pins ILIML and UPOUT. The digital signal on the current limiting selection input determines which resistor sets the limit level (pin ILIMSEL = HIGH results in the use of pin ILIMH). The current limiting selection input can accept a digital signal having a HIGH-level of just 55% of the voltage on pins UPOUT. The noise margin on this input is increased by a low-pass filter, having a cutoff frequency of about 50 MHz. However, for stability reasons the level on the current limiting selection input shall not change within a period shorter than 20 ms. Power switches The power switches in the IC are one N-type and one P-type power MOSFET, having a typical drain-to-source resistance of 56 and 68 mΩ respectively. The maximum average current in the power switches is 1.8 A at Tamb = 60 °C. Temperature protection When the device operates in the PWM mode, and the die temperature gets too high (typically 175 °C), the converter stops operating. It resumes operation when the die temperature falls below 175 °C again. As a result, low-frequent cycling between on and off state will occur. It should be noted that in the event of device temperatures around the cut-off limit, the application differs strongly from maximum specifications. In case just one current limit is sufficient, the unused pin (pin ILIML or ILIMH) must be connected either to the other pin (pin ILIMH or ILIML), or to pin UPOUT. In the downconversion mode, the current limiting level is set internally at a fixed value which is higher than the current level that most applications require. It should be regarded as a protection function only. In the downconversion mode, pins ILIMH and ILIML must be connected to pin UPOUT. Current limiters If the current in one of the power switches exceeds its limit in the PWM mode, the current ramp is stopped immediately, and the next switching phase is entered. Current limiting is required to keep power conversion efficient during temporary high loads. Furthermore, current limiting protects the IC against overload conditions, inductor saturation, etc. maximum positive spread of Vfb Vh handbook, full pagewidth TEA1210TS upper specification limit 2% +4% Vl Vh Vout, typ 2% Vl −4% Vh 2% Vl typical situation lower specification limit maximum negative spread of Vfb Fig.4 Spread of location of output voltage window. 1999 Mar 08 7 MGR667 Philips Semiconductors Preliminary specification High efficiency, high current DC/DC converter TEA1210TS voltage drop. In case the converter is in the PFM mode at high input voltage, the output voltage will equal VI minus the voltage drop over the external diode. The current limiting function is not active. External synchronization If an external high-frequency clock is applied to the synchronization clock input, the switching frequency in PWM mode will be exactly that frequency divided by 22. In PFM mode, the switching frequency is always lower. The quiescent current of the device increases when an external clock is applied. In case no external synchronization is necessary, the synchronization clock input must be connected to ground level. • Downconversion: when the input voltage is lower than the target output voltage, but higher than 2.9 V, the P-type power MOSFET will stay conducting resulting in an output voltage being equal to the input voltage minus some resistive voltage drop. The current limiting function remains active. Behaviour at input voltage exceeding the specified range In general, an input voltage exceeding the specified range is not recommended since instability may occur. There are two exceptions: • Upconversion: at an input voltage higher than the target output voltage, but up to 6 V, the converter will stop switching. As long as the device is in the PWM mode, the internal P-type power MOSFET will be conducting and the output voltage will equal VI minus some resistive LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER Vn voltage on any pin Tj junction temperature Tamb operating ambient temperature Tstg storage temperature Ves electrostatic handling CONDITIONS MIN. MAX. UNIT shut-down mode −0.2 +6.5 operating mode −0.2 +5.9 V −40 +150 °C −40 +80 °C −40 +125 °C +1500 V +300 V human body model; note 1 −1500 machine model; note 2 −300 V Notes 1. Equivalent to discharging a 100 pF capacitor through a 1.5 kΩ resistor. 2. Equivalent to discharging a 200 pF capacitor via a 0.75 µH inductor. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER CONDITIONS thermal resistance from junction to ambient in free air VALUE UNIT 140 K/W QUALITY SPECIFICATION Product lifetime is fully guaranteed over 2000 hours of operation at an ambient temperature of 60 °C with a continuously repeating current profile on pins LX of 4 A during 577 µs followed by 1 A during 4.0 ms. All remaining quality specifications are in accordance with “SNW-FQ-611 part E”. 1999 Mar 08 8 Philips Semiconductors Preliminary specification High efficiency, high current DC/DC converter TEA1210TS CHARACTERISTICS Tamb = −40 to +80 °C; all voltages are measured with respect to ground; positive currents flow into the IC; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Voltage levels UPCONVERSION; pin U/D = LOW VI input voltage VI(start) − 5.50 V VO output voltage 2.90 − 5.50 V VI(start) start-up input voltage IL < 200 mA 1.20 1.60 1.85 V VI(uvlo) undervoltage lockout input voltage note 1 1.50 2.10 2.70 V note 2 2.90 − 5.50 V DOWNCONVERSION; PIN U/D = HIGH VI input voltage VO output voltage 1.30 − 5.50 V Vfb feedback input voltage 1.20 1.25 1.30 V ∆Vwindow output voltage window PWM mode 1.5 2.0 3.0 % up mode; note 3 100 125 150 µA − 2 10 µA Ilim(up) set to 0.4 A −20 − +20 % Ilim(up) set to 2.0 A −12 − +12 % GENERAL Current levels Iq quiescent current on pins LX Ishdwn current in shut-down mode ∆Ilim(up) current limit deviation in up mode Ilim(down) current limit in down mode ILX maximum continuous current on pins LX IUPOUT maximum continuous current on pins UPOUT note 4 − 4.8 − A Tamb = 80 °C − − 1.5 A Tamb = 60 °C − − 1.8 A up mode; VI = 1.8 V; VO = 3.6 V; Tamb = 80 °C − − 0.65 A Power MOSFETs RDSon(N) drain-to-source on-state resistance NFET Tj = 27 °C − 56 63 mΩ Tj = 100 °C − 75 84 mΩ RDSon(P) drain-to-source on-state resistance PFET Tj = 27 °C − 68 77 mΩ Tj = 100 °C − 92 104 mΩ 1999 Mar 08 9 Philips Semiconductors Preliminary specification High efficiency, high current DC/DC converter SYMBOL PARAMETER TEA1210TS CONDITIONS MIN. TYP. MAX. UNIT Efficiency η1 η2 η3 η4 efficiency upconversion efficiency upconversion efficiency upconversion efficiency upconversion Tamb = 20 °C; VI = 1.8 V; VO = 3.6 V; note 5 IL = 1 mA 80 82 − % IL = 4 mA 84 86 − % IL = 100 mA 89 91 − % IL = 500 mA 89 91 − % IL = 1.5 A; note 6 73 75 − % IL = 1 mA 78 80 − % IL = 4 mA 82 84 − % IL = 100 mA 87 89 − % IL = 500 mA 88 90 − % IL = 1.5 A; note 6 67 72 − % IL = 1 mA 83 86 − % IL = 4 mA 87 90 − % IL = 100 mA 90 93 − % IL = 500 mA 92 94 − % IL = 1.5 A; note 6 84 86 − % IL = 1 mA 81 83 − % IL = 4 mA 85 87 − % IL = 100 mA 88 90 − % IL = 500 mA 91 93 − % IL = 1.5 A; note 6 82 85 − % 480 600 720 kHz 9 13 20 MHz Tamb = 80 °C; VI = 1.8 V; VO = 3.6 V; note 5 Tamb = 20 °C; VI = 2.4 V; VO = 3.6 V; note 5 Tamb = 80 °C; VI = 2.4 V; VO = 3.6 V; note 5 Timing fsw switching frequency fsync synchronization clock input frequency tstart start-up time note 7 − 6 − ms tres response time from standby to Po(max) − 25 − µs PWM mode Temperature Tamb operating ambient temperature −40 +25 +80 °C Tmax internal cut-off temperature 150 175 200 °C 1999 Mar 08 10 Philips Semiconductors Preliminary specification High efficiency, high current DC/DC converter SYMBOL PARAMETER TEA1210TS CONDITIONS MIN. TYP. MAX. UNIT Digital levels VlL LOW-level input voltage on pins SHDWN, ILIMSEL, U/D and SYNC VIH HIGH-level input voltage on pins U/D and PWM note 8 0 − 0.4 V V1 − 0.4 − V1 + 0.3 V on pins SYNC and SHDWN note 8 0.55V1 − V1 + 0.3 V on pin ILIMSEL notes 8 and 9 0.55V1 − V1 + 0.3 V Notes 1. The undervoltage lockout voltage shows wide specification limits since it decreases at increasing temperature. When the temperature increases, the minimum supply voltage of the digital control part of the IC decreases and therefore the correct operation of this function is guaranteed over the whole temperature range. 2. When VI is lower than the target output voltage but higher than 2.9 V, the P-type power MOSFET will remain conducting (100% duty cycle), resulting in VO following VI. 3. The quiescent current is specified as the input current in the upconversion configuration at VI = 2.40 V and VO = 3.60 V, using L1 = 6.8 µH, R1 = 178 kΩ and R2 = 93.1 kΩ (see Fig.5). 4. The current limit is defined by the external current limiting resistors, see Section “Current limiting resistors”. Rlimx = 996 Ω results in a typical current limit of 400 mA and Rlimx = 178 Ω results in a typical current limit of 2.0 A. The spread of the current limit decreases with increasing the Ilim setpoint. 5. The specified efficiency is valid when using an output capacitor having an ESR of 0.04 Ω and an inductor having an inductance of 6.8 µH, an ESR of 0.04 Ω, and a sufficient saturation current level. The current limit is assumed to be set at 4.0 A. In the PWM-only mode, the efficiency at IL = 1 mA and IL = 4 mA is lower than the values specified. 6. The specified efficiency at IL = 1.5 A is only valid if the average input current does not exceed the maximum value of ILX. In most practical applications, this means that the load current is not continuous. 7. The specified start-up time is the time between the connection of a 2.40 V input voltage source and the moment the output reaches 3.60 V. The output capacitance equals 2000 µF, the inductance equals 6.8 µH, no load is present. 8. V1 is the voltage on the pins UPOUT. If the applied HIGH-level voltage is less than V1 − 1 V, the quiescent current of the device will increase. 9. Maximum additional supply current on the pins UPOUT is 50 µA in case the voltage V1 = 5.0 V and the input voltage on pin ILIMSEL is 2.2 V. 1999 Mar 08 11 Philips Semiconductors Preliminary specification High efficiency, high current DC/DC converter TEA1210TS APPLICATION INFORMATION handbook, full pagewidth D1 1, 16 L1 VI LX 4, 5, 12, 13 TEA1210TS 8, 9 2 GND U/D 3 14 SYNC SHDWN VO R1 15 6 C1 UPOUT 7 11 PWM ILIMSEL FB C2 10 ILIMH ILIML Rlimh Rliml C3 R2 MGR727 Fig.5 Complete application for upconversion. handbook, full pagewidth UPOUT VI L1 4, 5, LX 12, 13 1, 16 VO TEA1210TS R1 15 C1 6 10 7 11 2 14 U/D ILIML ILIMH ILIMSEL PWM 8, 9 SYNC GND FB C2 3 SHDWN D1 R2 C3 MGR728 Fig.6 Complete application for downconversion. 1999 Mar 08 12 Philips Semiconductors Preliminary specification High efficiency, high current DC/DC converter TEA1210TS External component selection CURRENT LIMITING RESISTORS INDUCTOR L1 The maximum instantaneous current in upconversion mode is set by one of the external resistors Rlimh and Rliml. The preferred type is SMD, 1% accurate. The performance of the TEA1210TS is not very sensitive to inductance value. Best efficiency performance over a wide load current range is achieved by using an inductance of 6.8 µH and a saturation current level of 3.0 A at least. In case the maximum output current is lower, other inductors are also suitable such as the TDK SLF7032 range. The digital level on pin ILIMSEL defines which one of the resistors is used to determine the current limiting level. The functionality of both settings is identical. In case one current limit is enough, the unused pin (pin ILIML or ILIMH) must be connected either to the other pin (pin ILIMH or ILIML), or to pin UPOUT. DIODE D1 The values of the current limiting resistors can be derived from the simplified formula: The Schottky diode is only used a short time during takeover from N-type power MOSFET and P-type power MOSFET and vice versa. Therefore, a medium-power diode such as Philips PRLL5819 is sufficient in most applications. 346 R limh = ------------------------------------ , active when ILIMSEL = HIGH I lim ( up ) – 0.05 346 R liml = ------------------------------------ , active when ILIMSEL = LOW I lim ( up ) – 0.05 INPUT CAPACITOR C1 The value of capacitor C1 strongly depends on the type of input source. In general, a 100 µF tantalum capacitor will do, or a 10 µF ceramic capacitor featuring very low series resistance (ESR value). The average inductor current during limited current operation also depends on the inductance value and the resistive losses in all components in the power path. Ensure that both current limiting levels do not exceed the saturation current of the inductor. OUTPUT CAPACITOR C2 The value and type of capacitor C2 depend on the maximum output current and the ripple voltage which is allowed in the application. Low-ESR tantalum capacitors show best results. The most important specification of capacitor C2 is its ESR value, which mainly determines the output voltage ripple. FEEDBACK CAPACITOR C3 Capacitor C3 prevents the feedback voltage from polluting by switching noise. A ceramic type of capacitor having a maximum value of 33 pF is recommended. FEEDBACK RESISTORS R1 AND R2 The output voltage is determined by the resistors R1 and R2. The following conditions apply: • Use 1% accurate SMD type resistors • Resistors R1 and R2 should have a maximum value of 50 kΩ when connected in parallel. A higher value will result in inaccurate operation. Under these conditions, the output voltage can be R1 calculated by the formula: V O = 1.25 × 1 + -------- R2 1999 Mar 08 13 Philips Semiconductors Preliminary specification High efficiency, high current DC/DC converter TEA1210TS PACKAGE OUTLINE SSOP16: plastic shrink small outline package; 16 leads; body width 4.4 mm D SOT369-1 E A X c y HE v M A Z 9 16 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 8 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 1.5 0.15 0.00 1.4 1.2 0.25 0.32 0.20 0.25 0.13 5.30 5.10 4.5 4.3 0.65 6.6 6.2 1.0 0.75 0.45 0.65 0.45 0.2 0.13 0.1 0.48 0.18 10 0o Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 94-04-20 95-02-04 SOT369-1 1999 Mar 08 EUROPEAN PROJECTION 14 o Philips Semiconductors Preliminary specification High efficiency, high current DC/DC converter If wave soldering is used the following conditions must be observed for optimal results: SOLDERING Introduction to soldering surface mount packages • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Wave soldering Manual soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. To overcome these problems the double-wave soldering method was specifically developed. 1999 Mar 08 TEA1210TS When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. 15 Philips Semiconductors Preliminary specification High efficiency, high current DC/DC converter TEA1210TS Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE REFLOW(1) WAVE BGA, SQFP not suitable HLQFP, HSQFP, HSOP, HTSSOP, SMS not PLCC(3), SO, SOJ suitable suitable(2) suitable suitable suitable LQFP, QFP, TQFP not recommended(3)(4) suitable SSOP, TSSOP, VSO not recommended(5) suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1999 Mar 08 16 Philips Semiconductors Preliminary specification High efficiency, high current DC/DC converter NOTES 1999 Mar 08 17 TEA1210TS Philips Semiconductors Preliminary specification High efficiency, high current DC/DC converter NOTES 1999 Mar 08 18 TEA1210TS Philips Semiconductors Preliminary specification High efficiency, high current DC/DC converter NOTES 1999 Mar 08 19 TEA1210TS Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 465002/800/01/pp20 Date of release: 1999 Mar 08 Document order number: 9397 750 04337