INTEGRATED CIRCUITS OBJECTIVE DEVICE SPECIFICATION T h is D evice S p ecification con tain s d ata for p rod uct d evelop m en t. Ph ilip s S em icond uctors reserves th e righ t to ch an ge th e sp ecification in an y m ann er w ith ou t n otice. TDA8932 2x15W class D Power Amplifier Confidential Objective Device Specification Philips Semiconductors Date: Sept 13, 2005 Version: 1.7 Previous date: July 7, 2005 Philips Semiconductors Objective Device Specification Confidential 2 × 10..25 W class-D amplifier Change history 1.0 22-sep-04 1.1 21-oct-04 1.2 17-nov-04 1.3 24-nov-04 1.4 13-Dec-04 1.5 8-April-05 1.6 7-July-05 1.7 13-Sept-05 TDA8932 Initial version Updated after feedback design team Redefinition of TDA8932: 1xBTL or 2xSE Updated after feedback design team Updated after feedback customer Updated with new pinning Updated with test results and pin configuration General update September 2005, version 1.7 3 Philips Semiconductors Objective Device Specification Confidential 2 × 10..25 W class-D amplifier TDA8932 CONTENTS CONTENTS 4 1 FEATURES 7 2 APPLICATIONS 7 3 GENERAL DESCRIPTION 7 4 QUICK REFERENCE DATA 8 5 ORDERING INFORMATION 8 6 BLOCKDIAGRAM 9 7 PINNING INFORMATION 10 7.1 Pinning 10 7.2 Pin description 11 8 FUNCTIONAL DESCRIPTION 12 8.1 General 12 8.2 Mode selection / interfacing 12 8.3 Pulse width modulation frequency 13 8.4 Protections 8.4.1 Thermal foldback 8.4.2 Over temperature protection (OTP) 8.4.3 Over current protection (OCP) 8.4.4 Window protection (WP) 8.4.5 Supply voltage protections 13 13 13 14 14 15 8.5 Diagnostic Output 16 8.6 Differential inputs 16 8.7 Half supply voltage output 17 9 INTERNAL CIRCUITRY September 2005, version 1.7 18 4 Philips Semiconductors Objective Device Specification Confidential 2 × 10..25 W class-D amplifier TDA8932 10 LIMITING VALUES 25 11 THERMAL CHARACTERISTICS 25 12 QUALITY SPECIFICATION 25 13 STATIC CHARACTERISTICS 26 14 SWITCHING CHARACTERISTICS 28 15 DYNAMIC SE AC CHARACTERISTICS 29 16 DYNAMIC BTL AC CHARACTERISTICS 30 17 APPLICATION INFORMATION 32 17.1 Thermal behaviour (PCB considerations) 32 17.2 Thermal foldback 32 17.3 Output Power estimation 33 17.4 External clock 33 17.5 Pumping effects 35 17.6 Gain setting 36 17.7 Low pass filter considerations 36 17.8 Curves measured in reference design 36 17.9 Typical application schematics 37 18 PACKAGE OUTLINE 39 19 SOLDERING 40 September 2005, version 1.7 5 Philips Semiconductors Objective Device Specification Confidential 2 × 10..25 W class-D amplifier TDA8932 LIST OF FIGURES Figure 1: Block diagram 9 Figure 2: Pin configuration 10 Figure 3: Diagnostic Output for different kind of short circuit conditions. 16 Figure 4: Input configuration for mono BTL application. 17 Figure 5: Output power stereo SE (@ THD=10%) and required Rth(j-a) versus supply voltage (Tj=125°C, dT=70°C) 31 Figure 6: Output power mono BTL application (@ THD=10%) and required Rth(j-a) versus supply voltage (Tj=125°C, dT=70°C) 31 Figure 7: Master slave concept in two chip application 34 Figure 8: Input/speaker configuration for stereo SE application for reducing pumping effects. 35 Figure 9: Input configuration for reducing gain. 36 Figure 10: Typical application diagram for 2 x SE (asymmetrical supply) 37 Figure 11: Typical application diagram for 1 x BTL (asymmetrical supply) 37 Figure 12: Typical application diagram for 2 x SE + 1 x BTL (asymmetrical supply) 38 LIST OF TABLES Table 1: Quick reference data Table 2: Ordering information Table 3: Pinning description Table 4: Mode selection TDA8932 Table 5: Overview protections TDA8932 Table 6: Limiting values Table 7: Thermal characteristics Table 8: Static characteristics Table 9: Switching characteristics Table 10: Dynamic AC SE characteristics Table 11: Dynamic AC BTL characteristics Table 12: Master/Slave configuration Table 13: Filter components value September 2005, version 1.7 8 8 11 12 15 25 25 26 28 29 30 34 36 6 Philips Semiconductors Objective Device Specification Confidential 2 × 10..25 W class-D amplifier TDA8932 1 FEATURES • • • • • • • • • • • • High efficiency Application without heatsink using thermally enhanced small outline package Operating voltage from 10V to 36V asymmetrical or +/-5V to +/-18V symmetrical Thermally protected Thermal foldback Full short circuit proof across load and to supply lines (using advanced current protection) Switchable internal / external oscillator (master-slave setting) No pop noise Low quiescent current Low sleep current Mono bridged tied load (full bridge) or stereo single ended (half bridge) application Full differential inputs 2 APPLICATIONS • • Television sets CRT/LCD/plasma TV/projection TV Monitors 3 GENERAL DESCRIPTION The TDA8932 is a high efficiency class-D amplifier with low dissipation. The maximum output power is 2x25W in stereo half-bridge application (Rl=4 ohm) or 1x50W in mono full bridge application (Rl=8 ohm). Due to the high efficiency the device can be used without any external heat sink when playing music. If proper cooling via the PCB is implemented, a continuous output power of 2 x 15W is feasible. Due to the implementation of thermal foldback even for high supply voltages and/or lower load impedances the device can be operated with considerable music output power without the need for an external heat sink. The device has two full differential inputs driving four integrated power switches, combined in two independent outputs. It can be used as mono full bridge (BTL) or as stereo half bridge (SE). September 2005, version 1.7 7 Philips Semiconductors Objective Device Specification Confidential 2 × 10..25 W class-D amplifier TDA8932 4 QUICK REFERENCE DATA Table 1: Quick reference data SYMBOL PARAMETER General; Vp=29V Vp Operating supply voltage Isleep Sleep current Ip Quiescent current Stereo SE channel PoutSE Continuous-time RMS Output power per channel Peak output power (short-time) Mono BTL channel PoutBTL Continuous RMS Output power Peak output power (short-time) CONDITION MIN. TYP. MAX. UNIT 10 29 80 36 V µA Vpower up < 0.8 V Vengage < 0.8 V Without load, snubbers, output filter RL= 4Ω; THD = 10% Vp=22V RL= 8Ω; THD = 10% Vp=29V RL= 4Ω; THD = 10% Vp=29V RL= 8Ω; THD = 10% Vp=22V RL= 4Ω; THD = 10% Vp=12V RL= 8Ω; THD = 10% Vp=29V 20 mA 14 15 W 14 15 W 23 25 W 28 30 W 14 15 W 48 50 W 5 ORDERING INFORMATION Table 2: Ordering information TYPE NUMBER NAME TDA8932T SO32 September 2005, version 1.7 PACKAGE DESCRIPTION Plastic small outline package; 32 leads; body width 7.5 mm 8 VERSION SOT287-1 Philips Semiconductors Objective Device Specification Confidential 2 × 10..25 W class-D amplifier TDA8932 6 BLOCKDIAGRAM OSCREF VDDA OSCIO 10 8 VDDP1 31 29 Oscillator IN1P IN1N 2 VSSD PWM Modulator Driver High 3 28 BOOT1 27 OUT1 CTRL Driver Low 26 Stabi12V INREF 25 STAB1 VSSP 12 Manager + Stabi12V VSSP IN2P 15 IN2N VSSP1 PWM Modulator Driver High 14 24 STAB2 21 BOOT2 20 VDDP2 22 OUT2 23 VSSP2 18 DREF 11 HVPREF 30 HVP1 CTRL Driver Low DIAG 4 PROTECTIONS OVP, OCP, OTP, UVP, TF, WP REG5V VSSD CGND 7 VDDA POWER UP 6 Mode ENGAGE 5 VSSA TDA8932 9 VSSA 1, 16, 17, 32 13 TEST VSSD/HW Figure 1: Block diagram September 2005, version 1.7 19 HVP2 9 Philips Semiconductors Objective Device Specification Confidential 2 × 10..25 W class-D amplifier TDA8932 7 PINNING INFORMATION 7.1 Pinning VSSD / HW 1 32 VSSD / HW IN1P 2 31 OSCIO IN1N 3 30 HVP1 DIAG 4 29 VDDP1 ENGAGE 5 28 BOOT1 POWER UP 6 27 OUT1 CGND 7 26 VSSP1 VDDA 8 25 STAB1 VSSA 9 24 STAB2 TDA8932 SO32 OSCREF 10 23 VSSP2 HVPREF 11 22 OUT2 INREF 12 21 BOOT2 TEST 13 20 VDDP2 IN2N 14 19 HVP2 IN2P 15 18 DREF VSSD / HW 16 17 VSSD / HW Figure 2: Pin configuration September 2005, version 1.7 10 Philips Semiconductors Objective Device Specification Confidential 2 × 10..25 W class-D amplifier 7.2 TDA8932 Pin description Table 3: Pinning description Pin name Pin no. Description VSSD / HW 1 Negative digital supply voltage and handle wafer connection IN1P 2 Positive audio input for channel 1 IN1N 3 Negative audio input for channel 1 DIAG 4 (Open-drain) diagnostic output ENGAGE 5 Engage input; switch between mute and operating mode POWER UP 6 Power up input; switch between sleep and mute mode CGND 7 Control ground; reference for POWER UP, ENGAGE, DIAG VDDA 8 Positive analog supply voltage VSSA 9 Negative analog supply voltage OSCREF 10 Master/slave setting oscillator. Set internal oscillator frequency (only master-setting) HVPREF 11 Decoupling for internal half supply voltage reference INREF 12 Decoupling for input reference voltage TEST 13 Test signal input; for testing purpose only IN2N 14 Negative audio input for channel 2 IN2P 15 Positive audio input for channel 2 VSSD / HW 16 Negative digital supply voltage and handle wafer connection VSSD / HW 17 Negative digital supply voltage and handle wafer connection DREF 18 Decoupling internal 5V regulator for logic supply HVP2 19 Half supply voltage output for charging single-ended capacitor for channel 2 VDDP2 20 Positive power supply voltage for channel 2 BOOT2 21 Bootstrap capacitor for channel 2 OUT2 22 PWM output channel 2 VSSP2 23 Negative power supply voltage for channel 2 STAB2 24 Decoupling internal 12V regulator for the drivers channel 2 STAB1 25 Decoupling internal 12V regulator for the drivers channel 1 VSSP1 26 Negative power supply voltage for channel 1 OUT1 27 PWM output channel 1 BOOT1 28 Bootstrap capacitor for channel 1 VDDP1 29 Positive power supply voltage for channel 1 HVP1 30 Half supply voltage output for charging single-ended capacitor for channel 1 OSCIO 31 Input/output for external oscillator (slave-setting) VSSD / HW 32 Negative digital supply voltage and handle wafer connection September 2005, version 1.7 11 Philips Semiconductors Objective Device Specification Confidential 2 × 10..25 W class-D amplifier TDA8932 8 FUNCTIONAL DESCRIPTION 8.1 General The TDA8932 is a mono full bridge (BTL) or stereo half bridge (SE) audio power amplifier using class-D technology. The audio input signal is converted into a Pulse Width Modulated (PWM) signal via an analog input stage and PWM modulator. To enable the output power DMOS transistors to be driven, this digital PWM signal is applied to a control and handshake block and driver circuits for both the high side and low side. A 2nd-order low-pass filter converts the PWM signal to an analog audio signal across the loudspeakers. The TDA8932 contains two independent half bridges with full differential input stages. The loudspeakers can be connected in the following configurations: • Mono full bridge (Bridge-Tied Load, BTL) • Stereo half-bridge (Single-Ended, SE) The TDA8932 contains common circuits to both channels such as the oscillator, all reference sources, the mode functionality and a digital timing manager. The following protections are built-in: thermal fold back, temperature, current and voltage protections. 8.2 Mode selection / interfacing The TDA8932 can be switched in three operating modes via POWER UP and ENGAGE inputs: • Sleep mode; with a very low supply current • Mute mode; the amplifiers are switching idle (50% duty cycle), but the audio signal at the output is suppressed by disabling the Vl-converter input stages. In this mode the reference currents and voltages are present. The HVP capacitors have been charged to half the supply voltage (asymmetrical supply only). • Operating mode; the amplifiers are fully operational with output signal. Both pins POWER UP and ENGAGE refer to pin CGND. In the table 4 below the different modes are given as function of the voltages on the POWER UP and ENGAGE pins. Mode selection Sleep Mute Operating POWER UP ENGAGE Vpower up< 0.8 V X (don’t care) 2 V < Vpower up < 6.5 V Note1 Vengage< 0.8 V Note1 2 V < Vpower up < 6.5 V Note1 3 V < Vengage < 6.5 V Note1 Table 4: Mode selection TDA8932 Note 1 in case of symmetrical supply conditions the voltage applied on the POWER UP and ENGAGE inputs must never exceed the supply voltage VDDx September 2005, version 1.7 12 Philips Semiconductors Objective Device Specification Confidential 2 × 10..25 W class-D amplifier TDA8932 If the transition between mute and operating mode is controlled via a time-constant, the start-up will be pop-free since the DC output offset voltage is applied gradually to the output between mute mode and operating mode. The bias current setting of the VI converters is related to the voltage on the ENGAGE pin; in mute mode the bias current setting of the VI converters is zero (VI converters disabled) and in operating mode the bias current is at maximum. The time constant required to apply the DC output offset voltage gradually between mute and operating can be generated by applying a decoupling capacitor on the ENGAGE pin. The value of the time-constant should be dimensioned for 500 ms using a capacitor of 1µF on the ENGAGE pin. 8.3 Pulse width modulation frequency The output signal of the amplifier is a PWM signal with a carrier frequency of approximately 320 kHz. Using a 2nd-order LC demodulation filter in the application results in an analog audio signal across the loudspeaker. The PWM switching frequency can be set by an external resistor Rosc connected between pin OSCREF and VSSD. The carrier frequency can be set between 300 kHz and 500 kHz. Using an external resistor of 39kΩ on the OSCREF pin, the carrier frequency is set to an optimized value of 320 kHz. If two or more TDA8932 devices are used in the same audio application, it is recommended to synchronize the switching frequency of all devices. This is described in chapter 17.4 External Clock. 8.4 Protections The following protections are included in TDA8932: • • • • • Thermal foldback (TF) Over temperature protection (OTP) Over current protection (OCP) Window protection (WP) Supply voltage protections - Under voltage protection (UVP) - Over voltage protection (OVP) - Un Balance Protection (UBP) The reaction of the device on the different fault conditions differs per protection and is described in the following sections. 8.4.1 Thermal foldback 0 If the junction temperature Tj > 140 C, then the gain is gradually reduced resulting in a smaller output 0 signal and less dissipation. At Tj > 150 C the outputs are fully muted. 8.4.2 Over temperature protection (OTP) 0 If the junction temperature Tj > 160 C, then the power stage will shut down immediately. September 2005, version 1.7 13 Philips Semiconductors Objective Device Specification Confidential 2 × 10..25 W class-D amplifier TDA8932 8.4.3 Over current protection (OCP) When the loudspeaker terminals are short-circuited or if one of the demodulated outputs of the amplifier is short-circuited to one of the supply lines, this will be detected by the over current protection (OCP). If the output current exceeds the maximum output current of 4A, this current will be limited by the amplifier to 4A while the amplifier outputs remain switching (the amplifier is NOT shut-down completely). The amplifier can distinguish between an impedance drop of the loudspeaker and low-ohmic short across the load or to one of the supply lines. This impedance threshold (Zth) depends on the supply voltage used. When a short is made across the load causing the impedance to drop below the threshold level (<Zth) the audio amplifier is switched off completely and after a time of 100ms it will try to restart again. If the short circuit condition is still present after this time this cycle will be repeated. The average dissipation will be low because of this low duty cycle. A short to one of the supply lines will trigger the over current protection (OCP) and the amplifier will be shut down. During restart the window protection will be activated. As a result the amplifier will not start-up after 100ms until the short to the supply lines is removed. In case of impedance drop (e.g. due to dynamic behavior of the loudspeaker) the same protection will be activated; the maximum output current is again limited to 4A, but the amplifier will NOT switch-off completely (thus preventing audio holes from occurring). Result will be a clipping output signal without any artifacts. 8.4.4 Window protection (WP) The window protection (WP) checks the PWM output voltage before switching from sleep to mute mode (outputs switching) and is activated: • During the start-up sequence, when pin POWER UP is switched from sleep to mute. In the event of a short-circuit at one of the output terminals to VDD or Vss the start-up procedure is interrupted and the TDA8932 waits for open-circuit outputs. Because the check is done before enabling the power stages, no large currents will flow in the event of a short-circuit. • When the amplifier is completely shut-down due to activation of the over current protection (OCP) because a short to one of the supply lines is made, then during restart (after 100ms) the window protection will be activated. As a result the amplifier will not start-up until the short to the supply lines is removed. September 2005, version 1.7 14 Philips Semiconductors Objective Device Specification Confidential 2 × 10..25 W class-D amplifier TDA8932 8.4.5 Supply voltage protections If the supply voltage drops below 10V, the under voltage protection circuit (UVP) is activated and the system will shut down correctly. If the internal clock is used, this switch-off will be silent and without pop noise. When the supply voltage rises above the threshold level, the system is restarted again after 100 ms. If the supply voltage exceeds 36V the over voltage protection circuit (OVP) is activated and the power stages will shut down. It is re-enabled as soon as the supply voltage drops below the threshold level. So in this case no timer of 100ms is started. Note that supply voltages above the maximum voltage of 40V may damage the TDA8932. Two conditions should be distinguished: 1. If the supply voltage is pumped to higher values by the TDA8932 application itself (see also section 17.6), the OVP is triggered and the TDA8932 is shutdown. The supply voltage will decrease and the TDA8932 is protected against any overstress. 2. If a supply voltage > 40V is caused by other/external causes than the TDA8932 will shut down, but the device can still be damaged since the supply voltage will remain > 40V in this case. The OVP protection is not a supply clamp. An additional Un Balance Protection (UBP) circuit compares the positive analog (VDDA) and the negative analog (VSSA) supply voltage and is triggered if the voltage difference between them exceeds a certain level. This level depends on the sum of both supply voltages. An expression for the unbalance threshold level is as follows: Vth(ubp) ≈ 0.25 x (VDDA + VSSA) In table 5 below an overview is given of all protections and the effect on the output signal Protection name Complete Restart shut-down when fault is removed 3) Restart DIAG every 100ms active LOW minimal 50ms Thermal foldback (TF) N Y N Over temperature protection (OTP) Y N Y 1 1 1 Over current protection (OCP) N) Y) N) 2 Window protection (WP) Y) Y N Under voltage protection (UVP) Y N Y Over voltage protection (OVP) Y N Y Un Balance Protection (UBP) Y N Y Table 5: Overview protections TDA8932 N Y 1 Y) Y Y Y Y Notes: 1. Only complete shutdown of amplifier if short-circuit impedance is below the threshold of TBF. In all other cases current limiting: resulting in clipping output signal. 2. Fault condition detected during (every) transition between sleep-to-mute and during restart after activation of OCP (short to one of the supply lines) 3. Amplifier gain will depend on junction temperature and heat sink size. September 2005, version 1.7 15 Philips Semiconductors Objective Device Specification Confidential 2 × 10..25 W class-D amplifier 8.5 TDA8932 Diagnostic Output Whenever one of the protections is triggered except for thermal foldback (TF) as summarized in table 5, the DIAG output is activated low. The diagnostic output signal during different short conditions is illustrated in figure 3. The DIAG pin refers to CGND. An internal reference supply will pull-up the opendrain DIAG output to approximately 2.4V. This internal reference supply can deliver approximately 50µA. Using the DIAG as input a voltage smaller than 0.8V will put the device into sleep mode. Shorted load Short to supply line Amplifier restart 2.4V No restart CGND = 0V ≈50ms ≈50ms Figure 3: Diagnostic Output for different kind of short circuit conditions. 8.6 Differential inputs For a high common mode rejection ratio and a maximum of flexibility in the application, the audio inputs are fully differential. By connecting the inputs anti-parallel the phase of one of the two channels can be inverted, so that a load can be connected between the two sets of output filters. In this case the system operates as a mono BTL amplifier. The input configuration for a mono BTL application is illustrated in Fig.4. In single-ended configuration it is also recommended to connect the two differential inputs in anti-phase. This has advantages for the current handling of the power supply at low signal frequencies and minimizes supply pumping (see also section 17.6). IN1+ OUT1 IN1- + - IN2+ + - AUDIO IN1 OUT2 IN2- September 2005, version 1.7 16 Philips Semiconductors Objective Device Specification Confidential 2 × 10..25 W class-D amplifier TDA8932 Figure 4: Input configuration for mono BTL application. 8.7 Half supply voltage output When the POWER UP is high the half supply voltage output charges the Single-Ended capacitor. The start-up will be pop free since the device starts switching when the SE capacitors are completely charged. The time required for charging the SE capacitor is depending on its value. The half supply voltage output is disabled when the TDA8932 is used in combination with a symmetrical supply. September 2005, version 1.7 17 Philips Semiconductors Objective Device Specification Confidential 2 × 10..25 W class-D amplifier TDA8932 9 INTERNAL CIRCUITRY Pin Symbol 1, 16 17, 32 VSSD/HW Equivalent circuit VDDA 1, 16, 17,32 VSSA 2, 15 3, 14 12 IN1P, IN2P IN1N, IN2N INREF VDDA 2k +/- 20% 2, 15 48k +/- 20% 12 HVPREF 48k +/- 20% 3, 14 2k +/- 20% VSSA September 2005, version 1.7 18 Philips Semiconductors Objective Device Specification Confidential 2 × 10..25 W class-D amplifier Pin Symbol 4 DIAG TDA8932 Equivalent circuit VDDA Vref 4 CGND VSSA 5 ENGAGE VDDA Iref 5 VSSA 6 CGND POWERUP VDDA 6 VSSA September 2005, version 1.7 19 CGND Philips Semiconductors Objective Device Specification Confidential 2 × 10..25 W class-D amplifier Pin Symbol 7 CGND TDA8932 Equivalent circuit VDDA 7 VSSA 8 VDDA 8 VSSD VSSA 9 VSSA VDDA 9 VSSD September 2005, version 1.7 20 Philips Semiconductors Objective Device Specification Confidential 2 × 10..25 W class-D amplifier Pin Symbol 10 OSCREF TDA8932 Equivalent circuit VDDA Iref 10 VSSA 11 HVPREF VDDA 11 VSSA 12 INREF VDDA 11 HVPREF VSSA September 2005, version 1.7 21 Philips Semiconductors Objective Device Specification Confidential 2 × 10..25 W class-D amplifier Pin Symbol 13 TEST TDA8932 Equivalent circuit VDDA 13 VSSA 18 DREF 18 VSSD 19, 30 HVP1, 2 VDDA 19, 30 VSSA September 2005, version 1.7 22 Philips Semiconductors Objective Device Specification Confidential 2 × 10..25 W class-D amplifier Pin Symbol 20, 29 23, 26 VDDP2, 1 VSSP2, 1 TDA8932 Equivalent circuit 20, 29 23, 26 21, 28 BOOT 21, 28 OUT1, 2 22, 27 OUT1, 2 VDDP1, 2 22, 27 VSSP1, 2 September 2005, version 1.7 23 Philips Semiconductors Objective Device Specification Confidential 2 × 10..25 W class-D amplifier Pin Symbol 24, 25 STAB1, 2 TDA8932 Equivalent circuit VDDA 24, 25 VSSP1, 2 31 OSCIO DREF 31 VSSD September 2005, version 1.7 24 Philips Semiconductors Objective Device Specification Confidential 2 × 10..25 W class-D amplifier TDA8932 10 LIMITING VALUES Table 6: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL PARAMETER CONDITION MIN. Vp Supply voltage Asymmetrical 10 operating mode Symmetrical +/-5 operating mode Iorm repetitive peak current in output note 1; maximum 4 pin output current limiting Tj Tstg Tamb Junction temperature Storage temperature range Ambient temperature range -55 -40 MAX. 40 UNIT V +/-20 V A °C °C °C 150 150 85 Notes 1. Current limiting concept. 11 THERMAL CHARACTERISTICS Table 7: Thermal characteristics SYMBOL PARAMETER Rth(j-a) SO32 Thermal resistance junction to ambient Rth(j-l) SO32 Thermal resistance junction to leadfinger Rth(j-c) SO32 Thermal resistance junction to case CONDITION In free air [1] In free air [1] In free air [2] MAX. 35 16 3 UNIT K/W K/W K/W [1] Measured in the application board [2] Strongly depends on where you measure on the case 12 QUALITY SPECIFICATION In accordance with ‘SNW-FQ-611-D’. The number of the quality specification can be found in the “Quality Reference Handbook”. The handbook can be ordered using the code 9398 510 63011. September 2005, version 1.7 25 Philips Semiconductors Objective Device Specification Confidential 2 × 10..25 W class-D amplifier TDA8932 13 STATIC CHARACTERISTICS Table 8: Static characteristics Vp = 22V; fosc =320 kHz; Tamb = 25 °C; unless otherwise specified. SYMBOL Supply PARAMETER Vp Single (a-symmetrical supply Operating mode voltage note 1 Symmetrical supply voltage CONDITIONS Operating mode note 1 Sleep mode MIN. TYP. MAX. UNIT 10 22 36 +/- 5 +/-11 +/-18 V V - 80 TBF µA Operating mode No load, snubbers and filter connected - 40 80 mA Series resistance output switches Rds,on25 Drain-source resistance power switch Tj=25 °C - 150 - mΩ Rds,on125 Tj=125 °C - 234 - mΩ Reference to CGND note 5 VPOWER UP = 3 V Reference to CGND 0 - 6.5 V 0 1 - 20 0.8 µA V Reference to CGND note 5 2 - 6.5 V Reference to CGND note 5 VENGAGE = 3 V 0 - 6.5 V - 20 40 µA Isleep Sleep supply current Iq(tot) Total quiescent supply current in operating mode Drain-source resistance power switch Power up input: POWER UP w.r.t. CGND VPOWER UP Input voltage IPOWER UP Vlow Input current Input voltage low level Vhigh Input voltage high level mode Engage input: ENGAGE w.r.t. CGND VENGAGE Input voltage IENGAGE Input current Vlow Input voltage low level Reference to CGND note 3 0 - 0.8 V Vhigh Input voltage high level mode Reference to CGND Notes 3 and 5 3 - 6.5 V Activated protection (see table 5). Reference to CGND. - - 0.8 V 5 V - V Diagnostic output: DIAG w.r.t. CGND VDIAG-LOW Voltage on DIAG pin VDIAG-HIGH Voltage on DIAG pin Operating mode Reference to CGND. Audio inputs; pins IN1M, IN1P, IN2M and IN2P 2 Vi DC input voltage - September 2005, version 1.7 Note 2 26 2.9 Philips Semiconductors Objective Device Specification Confidential 2 × 10..25 W class-D amplifier TDA8932 Half supply voltage: HVP1, HVP2, HVPREF VHVP1,2 IHVP1,2 VHVPREF Half supply voltage to charge SE-capacitor Charge current for HVP capacitor Half supply reference voltage Mute and operating mode Mute mode HVP = ½ Vp – 1V Mute and operating ½Vp- ½ Vp ½Vp+ 0.5V 0.5V 45 ½Vp- ½ Vp ½Vp+ 0.5V 0.5V V mA V Amplifier outputs; pins OUT1 and OUT2 |Voo(SE)| |Voo(BTL)| Output offset voltage with respect to HVPx Output offset voltage SE; mute; - - 15 mV SE; operating; note 4 BTL; mute; BTL; operating; note 4 - - 150 20 210 mV mV mV 10 11 12 V Stabilizer output; pin STAB1, STAB2 Vo(stab) Stabilizer output voltage Mute and operating; with respect to \/SSPX Voltage protections VUVP Under voltage protection 7.5 8.5 9.5 V VOVP Over voltage protection 36 38.5 40 V VUBP Un balance protection Operating when HVPREF within VUBP levels 8 11 14 V Current limiting 4 - - A 155 - 160 °C 140 - 150 °C 4.0 - 5 V 0 - 0.8 V 12 - - - Current protections IOCPlim Over current protection Temperature protection Tprot Temperature protection activation TTF Thermal foldback activation Oscillator reference Voscio_high Oscillator I/O level voltage high Voscio_low Oscillator I/O level voltage low Smax Number of slaves driven by one master Notes 1. The circuit is DC adjusted at Vp = 10V to 36V. 2. With respect to VSSA and with asymmetrical supply. 3. The transition between mute and operating mode is determined by the time-constant on the ENABLE pin. 4. DC output offset voltage is applied to the output during the transition between mute and operating mode in a gradual way. The dVoo/dt caused by any DC output offset is determined by the time-constant on the ENGAGE pin. 5. The maximum voltage applied on POWER UP and ENGAGE pin must never exceed the supply voltage VDDx September 2005, version 1.7 27 Philips Semiconductors Objective Device Specification Confidential 2 × 10..25 W class-D amplifier TDA8932 14 SWITCHING CHARACTERISTICS Table 9: Switching characteristics Vp=22V; Tamb = 25 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Internal oscillator fosc Typical internal oscillator frequency fosc(int) Internal oscillator frequency range Rosc = 39kΩ - 320 - kHz 300 - 500 kHz Timing trise Rise-time PWM output Iout=0 - 10 - ns tfall Fall-time PWM output Iout=0 - 10 - ns tmin Minimum pulse width Iout=0 - 80 - ns September 2005, version 1.7 28 Philips Semiconductors Objective Device Specification Confidential 2 × 10..25 W class-D amplifier TDA8932 15 DYNAMIC SE AC CHARACTERISTICS Table 10: Dynamic AC SE characteristics Vp = 22V; RL = 2 x 4Ω; f = 1kHz; fosc = 320 kHz; RSL < 0.05Ω (note 1); Tamb = 25°C; unless otherwise specified. SYMBOL PARAMETER Po THD Gv(cl) αcs SVRR Output power per channel CONDITIONS 4Ω; Vp = 22V; note 2 Continuous-time output power THD = 0.5%, f = 1kHz THD = 0.5%, f = 100Hz THD =10%, f = 1kHz THD =10%, f = 100Hz RL = 8Ω; Vp = 30V; note 2 Continuous-time output power THD = 0.5%, f = 1kHz THD = 0.5%, f = 100Hz THD = 10%, f = 1kHz THD = 10%, f = 100Hz RL = 4Ω; Vp = 29V; note 2 Maximum output power (short-time) THD = 0.5% THD =10% RL = 8Ω; Vp = 24V; note 2 Continuous-time output power THD = 0.5% THD =10% Total harmonic distortion Po = 1W; note 3 fi = 1kHz fi= 10kHz Closed loop voltage gain Vi=100mV; no load fi = 1kHz, Po=1W Channel separation Supply voltage ripple rejection MIN. TYP. MAX. UNIT RL = Operating; note 4 fi=100Hz fi = 1kHz Differential Operating, Rs=0Ω, note 5 mute; note 6 |Zi| Vno input impedance Noise output voltage |DGV| Vo(mute) CMRR Channel unbalance Output signal in mute Mute; Vi=TBF Common mode rejection Vi(CM) = 1VRMS ratio 11 14 - 12 12 15 15 - W W W W 11 14 - 12 12 15 15 - W W W W 19 23 20 25 - W W 7 9 8 10 - W W 29 56 0.04 0.04 30 70 0.1 0.1 31 - % % dB dB 70 - 50 45 100 70 100 dB dB kΩ µV - 50 1 75 70 500 - µV dB µV dB Notes 1. RSL is the series resistance of inductor of low-pass LC filter in the application. 2. Output power is measured indirectly; based on RDSon measurement. 3. Total harmonic distortion is measured in a bandwidth of 22 Hz to 20 kHz, AES17 brick wall. Maximum limit is guaranteed but not 100% tested. 4. Vripple = Vripple(max) = 2V(p-p); Rs=0ohm. 5. B = 22Hz – 20kHz, AES17 brick wall 6. B = 22Hz – 20kHz, AES17 brick wall, independent on Rs September 2005, version 1.7 29 Philips Semiconductors Objective Device Specification Confidential 2 × 10..25 W class-D amplifier TDA8932 16 DYNAMIC BTL AC CHARACTERISTICS Table 11: Dynamic AC BTL characteristics Vp = 22V; RL = 4Ω; f = 1kHz; fosc = 320 kHz; RsL < 0.05Ω (note 1); Tamb = 25 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS Po RL = THD Gv(cl) SVRR Output power 4Ω; Vp = 12V; note 2 Continuous-time output power THD = 0.5%, f = 1kHz THD = 0.5%, f = 100Hz THD =10%, f = 1kHz THD =10%, f = 100Hz RL = 8Ω; Vp = 22V; note 2 Continuous-time output power THD = 0.5%, f = 1kHz THD = 0.5%, f = 100Hz THD =10%, f = 1kHz THD =10%, f = 100Hz RL = 4Ω; Vp = 15V; note 2 Maximum output power (short-time) THD = 0.5% THD =10% RL = 8Ω; Vp = 30V; note 2 Maximum output power (short-time) THD = 0.5% THD =10% Total harmonic distortion Po = 1W; note 3 fi = 1kHz fi= 10kHz Closed loop voltage gain Operating; note 4 Supply voltage ripple rejection f =100Hz i fi = 1kHz Sleep; fi = 100Hz; note 4 Differential Operating, 18V, Rs=0 ohm, note 5 Mute; 18V, note 6 |Zi| Vno Input impedance Noise output voltage |DGV| Vo(mute) Channel unbalance Output signal in mute CMRR Common mode rejection Vi(CM) = 1 VRMS ratio Mute; Vi=TBF MIN. TYP. MAX. UNIT 11 14 - 12 12 15 15 - W W W W 23 28 - 24 24 30 30 - W W W W 19 23 20 25 - W W 38 47 40 50 - W W 35 0.04 0.04 36 0.1 0.1 37 % % dB - 50 45 80 - dB dB dB 35 - 50 100 70 1 - 150 100 500 kΩ µV µV dB µV - 75 - dB Notes 1. RSL is the series resistance of inductor of low-pass LC filter in the application. 2. Output power is measured indirectly; based on RDSon measurement. 3. Total harmonic distortion is measured in a bandwidth of 22 Hz to 20 kHz, AES17 brick wall. Maximum limit is guaranteed but may not be 100% tested. 4. Vripple = Vripple(max) = 2V(p-p); Rs=0ohm. 5. B = 22Hz – 20kHz, AES17 brick wall 6. B = 22Hz – 20kHz, AES17 brick wall, independent on Rs September 2005, version 1.7 30 Philips Semiconductors Objective Device Specification Confidential 2 × 10..25 W class-D amplifier TDA8932 2xSE : THD=10% Rl=4ohm Rl=6ohm Rl=8ohm Rl=16ohm 80.00 40 35 60.00 Pout (W) 25 20 40.00 15 10 Rthj-a (K/W) 30 20.00 5 0 0.00 8 12 16 20 24 28 32 36 Vp (V) Figure 5: Output power stereo SE (@ THD=10%) and required Rth(j-a) versus supply voltage (Tj=125°C, dT=70°C) 1xBTL : THD=10% Rl=4ohm Rl=6ohm Rl=8ohm Rl=16ohm 70 80.00 60 Pout (W) 40 40.00 30 20 Rthj-a (K/W) 60.00 50 20.00 10 0 0.00 8 12 16 20 24 28 32 36 Vp (V) Figure 6: Output power mono BTL application (@ THD=10%) and required Rth(j-a) versus supply voltage (Tj=125°C, dT=70°C) September 2005, version 1.7 31 Philips Semiconductors Objective Device Specification Confidential 2 × 10..25 W class-D amplifier TDA8932 17 APPLICATION INFORMATION 17.1 Thermal behaviour (PCB considerations) The heat sink in the application with the TDA8932 is made with the copper on the Printed Circuit Board (PCB). The TDA8932T uses the four corner leads (pins 1, 16, 17 and 32) for heat transfer from die to PCB. The limiting factor is the maximum junction temperature [Tj(max)]. In case of thermal foldback this maximum junction temperature is limited to 140 degrees for full gain. The formula below shows the relation between the maximum allowable power dissipation and the thermal resistance from junction to ambient. Rth ( j − a ) = T j (max) −Ta Pdiss Pdiss is determined by the efficiency of the TDA8932. In figures 5 and 6 the output power (for stereo SE and mono BTL application, both for THD=10%) is given as a function of supply voltage for different load impedances (4, 6, 8 and 16 ohm). The y-axis to the left in combination with solid lines applies to the output power levels. In the same figures the secondary y-axis on the right in combination with the dashed lines indicates the required Rth(j-a) value to apply these output powers continuously. All values are calculated taking into account a maximum temperature difference of 70 degrees between ambient and junction, while at the same time the maximum junction temperature is 125 degrees. Example: Vp=22V Pout = 2 x 15W into 4 ohm (THD=10%) Tj(max) = 125°C Tamb = 55°C The required Rth(j-a) = 22 K/W. If music output power instead of continuous sine wave output power is considered the maximum achievable output power with the same Rth(j-a) can be much higher. 17.2 Thermal foldback The TDA8932 has a built-in thermal foldback protection. In case the junction temperature of the TDA8932 exceeds the threshold level (e.g. 140°C) the gain of the amplifier is decreased to a level were the combination of dissipation and Rth(j-a) result in a junction temperature around the threshold level. This means that the device will not completely switch off, but remains operational at lower output power levels. Especially with music output signals this feature enables high peak output powers while still operating without any external heat sink other than the PCB area. If the junction temperature still increases due to external causes a second temperature protection threshold level is built in which shuts down the amplifier completely. September 2005, version 1.7 32 Philips Semiconductors Objective Device Specification Confidential 2 × 10..25 W class-D amplifier TDA8932 17.3 Output Power estimation The achievable output powers in several applications (SE and BTL) can be estimated using the following expressions: SE : Po ( 0.5%) ⎛ RL ⎞ ⎜⎜ x1 / 2VP x(1 − t min xf osc )⎟⎟ R + Rs ⎠ =⎝ L 2 xRL BTL : Po ( 0.5%) 2 ⎛ ⎞ RL ⎜⎜ xVP x(1 − t min xf osc )⎟⎟ R + 2 xRs ⎠ =⎝ L 2 xRL 2 Maximum current internally limited to 4A: SE : I o ( peak ) = 1 / 2VP x(1 − t min xf osc ) RL + Rs BTL : I o ( peak ) = VP x(1 − t min xf osc ) RL + 2 xRs Variables: RL = load impedance fosc = oscillator frequency (typical 350 kHz) = minimum pulse width (typical 80 ns) tmin = single sided supply voltage (or 0.5*(VDD + |VSS|)) VP PO(0.5%) = output power at the onset of clipping Rs = total series resistance consisting of bond wires, leads, Rdson_switch, series resistance of coil (typical 0.3Ω @ Tj=25°C) Note that Io(peak) should be below 4 A (section 9). Io(peak) is the sum of the current through the load and the ripple current. The value of the ripple current is dependent on the coil inductance and voltage drop over the coil. 17.4 External clock If two or more class D amplifiers are used it is recommended that all devices run at the same switching frequency. This can be realized by connecting all OSCIO pins together and configure one of the TDA8932 in the application as CLOCK MASTER, while the other TDA8932 devices are configured in SLAVE MODE. The OSCIO pin is a tri-state input output buffer. September 2005, version 1.7 33 Philips Semiconductors Objective Device Specification Confidential 2 × 10..25 W class-D amplifier TDA8932 In MASTER MODE the OSCIO pin is configured as oscillator OUTPUT. In SLAVE MODE the OSCIO pin is configured as oscillator INPUT. MASTER MODE is enabled by applying a resistor between OSCREF pin and VSSD, while SLAVE MODE is entered by directly connecting the OSCREF pin to VSSD (so without any resistor). This is illustrated in figure 7. The value of the resistor also sets the frequency of the carrier and can be estimated by following expression: f osc = 12.45 x109 ROSC 45 40 35 Rosc [kΩ] 30 25 20 15 10 5 0 300 350 400 450 500 fosc [kHz] The table below summarizes how to configure the TDA8932 in Master or Slave configuration. Table 12: Master/Slave configuration Configuration OSCREF Master Rosc > 25kΩ Slave Rosc=0Ω; Shorted to VSSD MASTER SLAVE IC1 IC2 TDA8932 TDA8932 OSCREF COSCREF 100nF OSCIO OUTPUT INPUT OSCIO OSCIO ROSCREF 39kΩ OSCREF VSSD VSSD Figure 7: Master slave concept in two chip application September 2005, version 1.7 34 Philips Semiconductors Objective Device Specification Confidential 2 × 10..25 W class-D amplifier TDA8932 17.5 Pumping effects When the amplifier is used in a SE configuration, a so-called 'pumping effect' can occur. During one switching interval, energy is taken from one supply (e.g. VDD), while a part of that energy is delivered back to the other supply line (e.g. Vss) and visa versa. When the power supply cannot sink energy, the voltage across the output capacitors of that power supply will increase. The voltage increase caused by the pumping effect depends on: • Speaker impedance • Supply voltage • Audio signal frequency • Value of decoupling capacitors on supply lines • Source and sink currents of other channels. The pumping effect should not cause a malfunction of either the audio amplifier and/or the power supply. For instance, this malfunction can be caused by triggering of the under voltage or over voltage protection of the amplifier. Best remedy for pumping effects is to use the TDA8932 in the mono full-bridge application or in case of stereo half-bridge application, adapt the power supply (e.g. increase supply decoupling capacitors). In a stereo half bridge application pumping effects can be minimized by connecting audio inputs in antiphase and change the polarity of one speaker. This is illustrated in figure 8. IN1+ AUDIO IN1 IN1- OUT1 + - + - AUDIO IN2 IN2IN2+ OUT2 + + Figure 8: Input/speaker configuration for stereo SE application for reducing pumping effects. September 2005, version 1.7 35 Philips Semiconductors Objective Device Specification Confidential 2 × 10..25 W class-D amplifier TDA8932 17.6 Gain setting The input signal in combination with the speaker impedance determines the required gain. The TDA8932 has a fixed gain of 30dB for SE applications. By adding a resistor of 12kΩ the gain is reduced by 6dB. 5k6 470nF 100k 12k Audio in 5k6 470nF Figure 9: Input configuration for reducing gain. 17.7 Low pass filter considerations For a flat frequency response (second order Butterworth filter) it is necessary to change the LC-filter components (Lx and Cx) according the speaker impedance. Table 13 shows the required components values in case of a 4Ω, 6Ω or 8Ω speaker impedance. Table 13: Filter components value Speaker impedance [Ω] 4 6 8 Lx value [µH] 22 33 47 Cx value [nF] 680 470 330 17.8 Curves measured in reference design tbd September 2005, version 1.7 36 Philips Semiconductors Objective Device Specification Confidential 2 × 10..25 W class-D amplifier TDA8932 17.9 Typical application schematics 1 VSSD/HW 470nF 470nF 2 IN1P VSSD/HW 32 100nF OSCIO 31 TDA8932HVP1 30 3 IN1N Audio in 1 22k 470nF 3V3 100nF VDDP 100nF 220uF VDDP1 29 5 ENGAGE BOOT1 28 6 POWER UP 10R VP 4 DIAG 39k 47µF 470nF 470nF Audio in 2 100nF 15nF VDDP OUT1 OUT1 27 7 CGND VSSP1 26 8 VDDA STAB1 25 9 VSSA STAB2 24 10 OSCREF VSSP2 23 11 HVPREF OUT2 22 12 INREF BOOT2 21 13 TEST VDDP2 20 14 IN2N HVP2 19 15 IN2P DREF 18 470pF 10R 100nF 470pF 10R 15nF OUT2 VDDP 100nF 100nF 16 VSSD/HW VSSD/HW 17 100nF Figure 10: Typical application diagram for 2 x SE (asymmetrical supply) 1 VSSD/HW 470nF 470nF Audio in 1 2 IN1P VSSD/HW 32 OSCIO 31 TDA8932HVP1 30 3 IN1N 22k 470nF 3V3 100nF VDDP 100nF 39k 220uF VDDP1 29 5 ENGAGE BOOT1 28 6 POWER UP 10R VP 4 DIAG 47µF 470nF 470nF 15nF OUT1 27 7 CGND VSSP1 26 8 VDDA STAB1 25 9 VSSA STAB2 24 10 OSCREF VSSP2 23 11 HVPREF 100nF VDDP OUT2 22 12 INREF BOOT2 21 13 TEST VDDP2 20 14 IN2N HVP2 19 15 IN2P DREF 18 16 VSSD/HW VSSD/HW 17 470pF 10R 100nF 470pF 10R Out 1 15nF VDDP 100nF 100nF Figure 11: Typical application diagram for 1 x BTL (asymmetrical supply) September 2005, version 1.7 37 Philips Semiconductors Objective Device Specification Confidential 2 × 10..25 W class-D amplifier 1 VSSD/HW 470nF 470nF 2 IN1P TDA8932 VSSD/HW 32 Synchronize OSCIO 31 100nF TDA8932HVP1 30 3 IN1N Audio in 1 22k 470nF 3V3 100nF VDDP 100nF 39k VDDP1 29 5 ENGAGE BOOT1 28 6 POWER UP 10R VP 4 DIAG 47µF 220uF 470nF 470nF Audio in 2 VSSP1 26 8 VDDA STAB1 25 9 VSSA STAB2 24 10 OSCREF VSSP2 23 OUT2 22 12 INREF BOOT2 21 13 TEST VDDP2 20 14 IN2N HVP2 19 15 IN2P DREF 18 1 VSSD/HW 470nF 2 IN1P 47µF 470nF 470nF Audio in 3 Out 1 470pF 10R 100nF 470pF 10R 15nF Out 2 VDDP 100nF 100nF 100nF VSSD/HW 32 Synchronize OSCIO 31 TDA8932HVP1 30 3 IN1N 4 DIAG VDDP1 29 5 ENGAGE BOOT1 28 6 POWER UP 100nF VDDP 15nF 16 VSSD/HW VSSD/HW 17 470nF 220µF OUT1 27 7 CGND 11 HVPREF 100nF VDDP 15nF OUT1 27 7 CGND VSSP1 26 8 VDDA STAB1 25 9 VSSA STAB2 24 10 OSCREF VSSP2 23 11 HVPREF 100nF 220µF OUT2 22 12 INREF BOOT2 21 13 TEST VDDP2 20 14 IN2N HVP2 19 15 IN2P DREF 18 16 VSSD/HW VSSD/HW 17 470pF 10R Out 3 100nF 470pF 10R 15nF VDDP 100nF 100nF Figure 12: Typical application diagram for 2 x SE + 1 x BTL (asymmetrical supply) September 2005, version 1.7 38 Philips Semiconductors Objective Device Specification Confidential 2 × 10..25 W class-D amplifier TDA8932 18 PACKAGE OUTLINE SO32: plastic small outline package; 32 leads; body width 7.5 mm SOT287-1 D E A X c y HE v M A Z 17 32 Q A2 A (A 3) A1 pin 1 index θ Lp L 16 1 0 detail X w M bp e 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. A1 A2 2.65 0.3 0.1 2.45 2.25 0.1 0.012 0.096 0.004 0.089 A3 bp c D (1) E (1) 0.25 0.49 0.36 0.27 0.18 20.7 20.3 7.6 7.4 0.01 0.02 0.01 0.011 0.007 0.81 0.80 0.30 0.29 e HE 1.27 10.65 10.00 0.05 0.419 0.394 L Lp Q 1.4 1.1 0.4 1.2 1.0 0.043 0.055 0.016 0.047 0.039 v 0.25 0.01 w 0.25 0.01 y Z (1) 0.1 0.95 0.55 0.004 0.037 0.022 θ Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION REFERENCES IEC SOT287-1 September 2005, version 1.7 JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 00-08-17 03-02-19 MO-119 39 o 8 0o Philips Semiconductors Objective Device Specification Confidential 2 × 10..25 W class-D amplifier TDA8932 19 SOLDERING September 2005, version 1.7 40