SAMSUNG KS57C3316

KS57C3316/P3316
1
PRODUCT OVERVIEW
PRODUCT OVERVIEW
OVERVIEW
The KS57C3316 single-chip CMOS microcontroller has been designed for high performance using Samsung's
newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers).
With features such as LCD direct drive capability, 4-channel A/D converter, 8-bit timer/counter, watch timer and
PLL frequency synthesizer, it offers you an excellent design solution for a wide variety of applications that require
LCD functions and audio applications.
Up to 56 pins of the 80-pin QFP package, it can be dedicated to I/O. Eight vectored interrupts provide fast
response to internal and external events. In addition, the KS57C3316's advanced CMOS technology provides for
low power consumption and a wide operating voltage range.
OTP
The KS57C3316 microcontroller is also available in OTP (One Time Programmable) version, KS57P3316. The
KS57P3316 microcontroller has an on-chip 16-Kbyte one-time-programmable EPROM instead of masked ROM.
The KS57P3316 is comparable to KS57C3316, both in function and in pin configuration.
1-1
PRODUCT OVERVIEW
KS57C3316/P3316
FEATURES
Memory
Watch Timer
•
512-nibble RAM
•
•
16K-byte ROM
Time interval generation
: 0.5 s, 3.9 ms at 32.768 kHz
•
Frequency outputs to BUZ pin
•
Clock source generation for LCD
I/O Pins
•
Input only: 4 pins
•
Output only: 28 pins
•
I/O: 24 pins
8-Bit Serial I/O Interface
•
8-bit transmit/receive mode
•
8-bit receive mode
LCD Controller/Driver
•
Data direction selectable (LSB-first or MSB-first)
•
Maximum 14-digit LCD direct drive capability
•
Internal or external clock source
•
28 segment x 4 common signals
•
Display modes: Static, 1/2 duty (1/2 bias)
1/3 duty (1/2 or 1/3 bias), 1/4 duty (1/3 bias)
A/D Converter
•
4-channels with 8-bit resolution
8-Bit Basic Timer
Bit Sequential Carrier Buffer
•
Programmable interval timer functions
•
•
Watch-dog timer function
Support 16-bit serial data transfer in arbitrary
format
PLL Frequency Synthesizer
8-Bit Timer/Counter
•
Level = 300 mVp-p (min)
•
Programmable 8-bit timer
•
AMVCO range = 0.5 MHz to 30 MHz
•
External event counter
•
FMVCO range = 30 MHz to 150 MHz
•
Arbitrary clock frequency output
•
External clock signal divider
•
Serial I/O interface clock generator
1-2
16-Bit Intermediate Frequency (IF) Counter
•
Level = 300 mVp-p (min)
•
AMIF range = 100 kHz to 1 MHz
•
FMIF range = 5 MHz to 15 MHz
KS57C3316/P3316 (Preliminary Spec)
PRODUCT OVERVIEW
FEATURES (Continued)
Interrupts
Instruction Execution Times
•
Four internal vectored interrupts
•
0.9, 1.8, 14.2 µs at 4.5 MHz
•
Four external vectored interrupts
•
122 µs at 32.768 kHz (subsystem)
•
Two quasi-interrupts
Operating Temperature
Memory-Mapped I/O Structure
•
•
– 40 °C to 85 °C
Data memory bank 15
Operating Voltage Range
Three Power-Down Modes
•
1.8 V to 5.5 V at 3MHz
•
Idle: Only CPU clock stops
•
PLL/IFC operation: 2.5V to 3.5V or 4.0V to 5.5V
•
Stop1: Main system or subsystem clock stops
•
Stop2: Main system and subsystem clock stop
•
CE low: PLL and IFC stop
Package Type
•
80-pin QFP
Oscillation Sources
•
Crystal or ceramic oscillator for main system
clock
•
Crystal for subsystem clock
•
Main system clock frequency: 4.5 MHz (Typ)
•
Subsystem clock frequency: 32.768 kHz (Typ)
•
CPU clock divider circuit (by 4, 8, or 64)
1-3
PRODUCT OVERVIEW
KS57C3316/P3316
BLOCK DIAGRAM
P0.0/BTCO
P0.1/TCLO0
P0.2/TCL0
P0.3/BUZ
P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/INT4
P2.0
P2.1
P2.2
P2.3
P3.0
P3.1
P3.2
P3.3
INT0-INT4
I/O Port 0
CE
XTIN
RESET XIN
XOUT XTOUT
Basic
Timer
I/O Port 3
Serial
I/O Port
P4.0/SCK
P4.1/SO
P4.2/SI
P4.3/CLO
I/O Port 4
P5.0/ADC0
P5.1/ADC1
P5.2/ADC2
P5.3/ADC3
I/O Port 5
A/D
Converter
Watchdog
Timer
Timer/
Counter 0
Input Port 1
I/O Port 2
Watch
Timer
Interrupt
Control
Block
Clock
Internal
Interrupts
Instruction Decoder
Arithmetic
and
Logic Unit
Instruction
Register
Program
Counter
Program
Status Word
Stack
Pointer
IF
Counter
PLL
Synthesizer
LCD Driver/
Controller
Output Port
11,12,13
Output Port
7,8,9,10
512 x 4-Bit
Data Memory
16K-Byte
Program Memory
I/O Port 6
Figure 1-1. KS57C3316 Simplified Block Diagram
1-4
AMIF
FMIF
VCOAM
VCOFM
EO
BIAS
VLC0-VLC2
COM0-COM3
P13.0-P13.3
/SEG24-SEG27
P12.0-P12.3
/SEG20-SEG23
P11.0-P11.3
/SEG16-SEG19
P10.0-P10.3
/SEG12-SEG15
P9.0-P9.3
/SEG8-SEG11
P8.0-P8.3
/SEG4-SEG7
P7.0-P7.3
/SEG0-SEG3
P6.0-P6.3
KS0-KS3
KS57C3316/P3316 (Preliminary Spec)
PRODUCT OVERVIEW
PIN ASSIGNMENTS
VDD1
E0
CE
P3.0
P3.1
P3.2
P3.3
P0.0/BTCO
P0.1/TCLO0
P0.2/TCL0
P0.3/BUZ
P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/INT4
P4.0/SCK
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
P4.1/SO
P4.2/SI
P4.3/CLO
P5.0/ADC0
P5.1/ADC1
P5.2/ADC2
P5.3/ADC3
P6.0/KS0
P6.1/KS1
P6.2/KS2
P6.3/KS3
VDD0
VSS0
XOUT
XIN
TEST
XTIN
XTOUT
RESET
BIAS
VLC0
VLC1
VLC2
COM0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
KS57C3316
(80-QFP-Top View)
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
FMIF
AMIF
VSS1
VCOAM
VCOFM
P2.3
P2.2
P2.1
P2.0
SEG27/P13.3
SEG26/P13.2
SEG25/P13.1
SEG24/P13.0
SEG23/P12.3
SEG22/P12.2
SEG21/P12.1
SEG20/P12.0
SEG19/P11.3
SEG18/P11.2
SEG17/P11.1
SEG16/P11.0
SEG15/P10.3
SEG14/P10.2
SEG13/P10.1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
SEG12/P10.0
SEG11/P9.3
SEG10/P9.2
SEG9/P9.1
SEG8/P9.0
SEG7/P8.3
SEG6/P8.2
SEG5/P8.1
SEG4/P8.0
SEG3/P7.3
SEG2/P7.2
SEG1/P7.1
SEG0/P7.0
COM3
COM2
COM1
Figure 1-2. KS57C3316 80-QFP Pin Assignment
1-5
PRODUCT OVERVIEW
KS57C3316/P3316
PIN DESCRIPTIONS
Table 1-1. KS57C3316 Pin Descriptions
Pin Name
Pin
Type
Description
Number
Share
Pin
Reset
Value
Circuit
Type
P0.0
P0.1
P0.2
P0.3
I/O
4-bit I/O port.
1-bit or 4-bit read, write, and test are possible.
Pull-up resistors can be configured by software.
72
73
74
75
BTCO
TCLO0
TCL0
BUZ
Input
D-2
D-2
D-4
D-2
P1.0
P1.1
P1.2
P1.3
I
4-bit input port.
1-bit or 4-bit read and test are possible.
Pull-up resistors can be configured by software.
76
77
78
79
INT0
INT1
INT2
INT4
Input
A-4
P2.0-P2.3
P3.0-P3.3
I/O
4-bit I/O ports.
1-bit, 4-bit or 8-bit read, write and test are possible.
Pull-up resistors can be configured by software.
Ports 2 and 3 can be paired to support 8-bit data
transfer.
56-59
68-71
–
Input
D-2
P4.0
P4.1
P4.2
P4.3
I/O
4-bit I/O ports.
1-bit, 4-bit or 8-bit read, write and test are possible.
Pull-up resistors can be configured by software.
80
1
2
3
SCK
Input
SO
SI
CLO
D-4
D-2
D-4
D-2
P5.0
P5.1
P5.2
P5.3
I/O
Ports 4 and 5 can be paired to support 8-bit data
transfer.
4
5
6
7
ADC0
ADC1
ADC2
ADC3
Input
F-10
P6.0
P6.1
P6.2
P6.3
I/O
4-bit I/O port.
1-bit, 4-bit or 8-bit read, write and test are possible.
Pull-up resistors can be configured by software.
8
9
10
11
KS0
KS1
KS2
KS3
Input
D-7
P7.0
P7.1
P7.2
P7.3
O
1-bit or 4-bit output port.
Alternatively used for LCD segment output.
28
29
30
31
SEG0
SEG1
SEG2
SEG3
Output
H-28
P8.0
P8.1
P8.2
P8.3
O
1-bit or 4-bit output port.
Alternatively used for LCD segment output.
32
33
34
35
SEG4
SEG5
SEG6
SEG7
Output
H-28
P9.0
P9.1
P9.2
P9.3
O
1-bit or 4-bit output port.
Alternatively used for LCD segment output.
36
37
38
39
SEG8 Output
SEG9
SEG10
SEG11
H-28
P10.0
P10.1
P10.2
P10.3
O
1-bit or 4-bit output port.
Alternatively used for LCD segment output.
40
41
42
43
SEG12 Output
SEG13
SEG14
SEG15
H-28
1-6
KS57C3316/P3316 (Preliminary Spec)
PRODUCT OVERVIEW
Table 1-1. KS57C3316 Pin Descriptions (Continued)
Pin Name
Pin
Type
Description
Number
Share
Pin
Reset
Value
Circuit
Type
P11.0
P11.1
P11.2
P11.3
O
1-bit or 4-bit output port.
Alternatively used for LCD segment output.
44
45
46
47
SEG16 Output
SEG17
SEG18
SEG19
H-28
P12.0
P12.1
P12.2
P12.3
O
1-bit or 4-bit output port.
Alternatively used for LCD segment output.
48
49
50
51
SEG20 Output
SEG21
SEG22
SEG23
H-28
P13.0
P13.1
P13.2
P13.3
O
1-bit or 4-bit output port.
Alternatively used for LCD segment output.
52
53
54
55
SEG24 Output
SEG25
SEG26
SEG27
H-28
COM0COM3
O
Common signal output for LCD display
BIAS
I
VLC0
24-27
–
Output
H
LCD power control
20
–
Input
–
I
LCD power supply.
Voltage dividing resistors are assignable by software
21
22
23
–
Input
–
VDD0
–
Main power supply
12
–
–
–
VSS0
–
Main Ground
13
–
–
–
RESET
I
System reset pin
19
–
Input
B
XOUT
–
Crystal, or ceramic oscillator pin for main system
clock. (For external clock input, use XIN and input
XIN’s reverse phase to XOUT)
14
15
–
–
–
–
Crystal oscillator pin for subsystem clock. (For
external clock input, use XTIN and input XTIN’s
reverse phase to XTOUT)
18
17
–
–
–
TEST
I
Test signal input (must be connected to VSS for
normal operation)
16
–
–
–
CE
I
Input pin for checking device power.
Normal operation is high level and PLL/IFC
operation is stopped at low level.
67
–
Input
B-5
VCOFM
VCOAM
I
External VCOFM/AM signal inputs.
60
61
–
Input
B-4
EO
O
PLL’s phase error output
66
–
Output
A-2
FMIF
AMIF
I
FM/AM intermediate frequency signal inputs.
64
63
Input
–
B-4
VDD1
–
PLL/IFC power supply
65
–
–
–
VSS1
–
PLL/IFC ground
62
–
–
–
VLC1
VLC2
XIN
XTOUT
XTIN
1-7
PRODUCT OVERVIEW
KS57C3316/P3316
Table 1-1. KS57C3316 Pin Descriptions (Concluded)
Pin Name
Pin
Type
Description
Number
Share
Pin
Reset
Value
Circuit
Type
BTCO
I/O
Basic timer overflow output signal
72
P0.0
Input
D-2
TCLO0
I/O
Timer/counter 0 clock output signal
73
P0.1
Input
D-2
TCL0
I/O
External clock input for timer/counter 0
74
P0.2
Input
D-4
BUZ
I/O
2,4,8 or 16 kHz frequency output for buzzer sound
for 4.19 MHz main system clock or 32.768 kHz
subsystem clock
75
P0.3
Input
D-2
INT0
INT1
I
External interrupt. The triggering edges
(rising/falling) are selectable. Only INT0 is
synchronized with system clock.
76
77
P1.0
P1.1
Input
A-4
INT2
I
Quasi-interrupt with detection of rising edge signal.
78
P1.2
INT4
I
External interrupt input with detection of rising or
falling edges.
79
P1.3
SCK
I/O
SIO interface clock signal
80
P4.0
Input
D-4
SI
I/O
SIO interface data input signal
1
P4.2
SO
I/O
SIO interface data output signal
2
P4.1
CLO
I/O
CPU clock output
3
P4.3
KS0-KS3
I/O
Quasi-interrupt input with falling edge detection
8-11
P6.0P6.3
Input
D-7
ADC0ADC3
I/O
ADC input ports.
4-7
P5.0P5.3
Input
F-10
SEG0SEG3
O
LCD segment signal output.
28-31
P7.0P7.3
Output
H-28
SEG4SEG27
O
LCD segment signal output.
32-55
P8-P13
Output
H-28
1-8
KS57C3316/P3316 (Preliminary Spec)
PRODUCT OVERVIEW
PIN CIRCUIT DIAGRAMS
VDD
VDD
Pull-Up
Resistor
P-Channel
In
In
N-Channel
Schmitt Trigger
Figure 1-3. Pin Circuit Type A
Figure 1-6. Pin Circuit Type B (RESET)
VDD
In
Type A
Up
P-Channel
Feedback
Enable
Out
Down
N-Channel
Figure 1-4. Pin Circuit Type A-2(EO)
N-CH
Pull-Down
Enable
Figure 1-7. Pin Circuit Type B-4
VDD
In
Pull-Up
Enable
In
Figure 1-5. Pin Circuit Type A-4 (P1)
Figure 1-8. Pin Circuit Type B-5(CE)
1-9
PRODUCT OVERVIEW
KS57C3316/P3316
VDD
VDD
Pull-up
Enable
P-Channel
P-Channel
Data
Out
N-Channel
Output
Disable
Data
Output
Disable
Circuit
Type C
I/O
Schmitt Trigger
Figure 1-9. Pin Circuit Type C
Figure 1-11. Pin Circuit Type D-4
VDD
VDD
Pull-up
Enable
P-Channel
Pull-up
Enable
Data
Data
Output
Disable
Circuit
Type C
I/O
Output
Disable
P-Channel
I/O
Circuit
Type C
Port
Enable
Schmitt Trigger
Figure 1-10. Pin Circuit Type D-2
1-10
Figure 1-12. Pin Circuit Type D-7 (P6)
KS57C3316/P3316 (Preliminary Spec)
PRODUCT OVERVIEW
VDD
VLC0
Pull-up
Enable
Data
Output
Disable
VLC1
Circuit
Type C
I/O
SEG
ADCEN
Out
Output
Disable
ADC Select
Data
VLC2
TO ADC
Figure1-13. Pin Circuit Type F-10 (P5)
Figure 1-15. Pin Circuit Type H-4
VLC0
PNE
VDD
VLC1
P-CH
Output
Data
LCD
COM
Out
VLC2
SEG
Figure 1-14. Pin Circuit Type H (COM0-COM3)
N-CH
Output
DIsable
Circuit
Type H-4
Figure 1-16. Pin Circuit Type H-28 (P7-P13)
1-11
KS57C3316/P3316
17
ELECTRICAL DATA
ELECTRICAL DATA
OVERVIEW
In this section, information on KS57C3316 electrical characteristics is presented as tables and graphics. The
information is arranged in the following order:
Standard Electrical Characteristics
— Absolute maximum ratings
— D.C. electrical characteristics
— System clock oscillator characteristics
— I/O capacitance
— A.C. electrical characteristics
— Operating voltage range
Miscellaneous Timing Waveforms
— A.C timing measurement point
— Clock timing measurement at XIN
— Clock timing measurement at XTIN
— Input timing for RESET
— Input timing for external interrupts and Quasi-Interrupts
Stop Mode Characteristics and Timing Waveforms
— RAM data retention supply voltage in stop mode
— Stop mode release timing when initiated by RESET
— Stop mode release timing when initiated by an interrupt request
17-1
KS57C3316/P3316
18
KS57P3316 OTP
KS57P3316 OTP
OVERVIEW
The KS57P3316 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the
KS57C3316 microcontroller. It has an on-chip EPROM instead of masked ROM. The EPROM is accessed by a
serial data format.
The KS57P3316 is fully compatible with the KS57C3316, both in function and in pin configuration. Because of its
simple programming requirements, the KS57P3316 is ideal for use as an evaluation chip for the KS57C3316.
18-1
KS57P3316 OTP
KS57C3316/P3316
VDD1
E0
CE
P3.0
P3.1
P3.2
P3.3
P0.0/BTCO
P0.1/TCLO0
P0.2/TCL0
P0.3/BUZ
P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/INT4
P4.0/SCK
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
P4.1/SO
P4.2/SI
P4.3/CLO
P5.0/ADC0
P5.1/ADC1
P5.2/ADC2
P5.3/ADC3
P6.0/KS0
P6.1/KS1
SDAT/P6.2/KS2
SCLK/P6.3/KS3
VDD/VDD0
VSS/VSS0
XOUT
XIN
VPP/TEST
XTIN
XTOUT
RESET/RESET
BIAS
VLC0
VLC1
VLC2
COM0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
KS57P3316
(80-QFP Top View)
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
SEG12/P10.0
SEG11/P9.3
SEG10/P9.2
SEG9/P9.1
SEG8/P9.0
SEG7/P8.3
SEG6/P8.2
SEG5/P8.1
SEG4/P8.0
SEG3/P7.3
SEG2/P7.2
SEG1/P7.1
SEG0/P7.0
COM3
COM2
COM1
Figure 18-1. KS57P3316 Pin Assignments (80-QFP)
18-2
FMIF
AMIF
VSS1
VCOAM
VCOFM
P2.3
P2.2
P2.1
P2.0
SEG27/P13.3
SEG26/P13.2
SEG25/P13.1
SEG24/P13.0
SEG23/P12.3
SEG22/P12.2
SEG21/P12.1
SEG20/P12.0
SEG19/11.3
SEG18/P11.2
SEG17/P11.1
SEG16/P11.0
SEG15/P10.3
SEG14/P10.2
SEG13/P10.3
KS57C3316/P3316
KS57P3316 OTP
Table 18-1. Pin Descriptions Used to Read/Write the EPROM
Main Chip
During Programming
Pin Name
Pin Name
Pin No.
I/O
Function
P6.2
SDAT
10
I/O
Serial data pin. Output port when reading and input port
when writing. Can be assigned as a Input or push-pull
output port.
P6.3
11
I/O
Serial clock pin. Input only pin.
TEST
SCLK
VPP (TEST)
16
I
Power supply pin for EPROM cell writing (indicates that
OTP enters into the writing mode). When 12.5 V is
applied, OTP is in writing mode and when 5 V is applied,
OTP is in reading mode.
RESET
RESET
19
I
Chip initialization
VDD / VSS
VDD / VSS
12/13
I
Logic power supply pin. VDD should be tied to +5 V during
programming.
Table 18-2. Comparison of KS57P3316 and KS57C3316 Features
Characteristic
KS57P3316
KS57C3316
Program Memory
16K bytes EPROM
16K bytes mask ROM
Operating Voltage (VDD)
1.8 V to 5.5 V
2.5 V to 3.5 V or 4.0 V to 5.5 V
at PLL/IFC operation
1.8 V to 5.5 V
2.5 V to 3.5 V or 4.0 V to 5.5 V
at PLL/IFC operation
OTP Programming Mode
VDD = 5 V, VPP (TEST) = 12.5 V
Pin Configuration
80 QFP
80 QFP
EPROM Programmability
User Program 1 time
Programmed at the factory
–
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the Vpp (TEST) pin of the KS57P3316, the EPROM programming mode is entered.
The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 17-3 below.
Table 18-3. Operating Mode Selection Criteria
VDD
Vpp(TEST)
REG/MEM
Address(A15-A0)
R/W
5V
5V
0
0000H
1
EPROM read
12.5 V
0
0000H
0
EPROM program
12.5 V
0
0000H
1
EPROM verify
12.5 V
1
0E3FH
0
EPROM read protection
Mode
NOTE: "0" means low level; "1" means high level.
18-3
KS57P3316 OTP
KS57C3316/P3316
Table 18-4. D.C. Electrical Characteristics
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Input high
voltage
Symbol
Conditions
Min
Typ
Max
Units
–
VDD
V
VIH1
All input pins except those specified
below
0.7 VDD
VIH2
P0.2, P1, P4.0, P4.2, P5, P6, CE and
0.8 VDD
VDD
VDD–0.1
VDD
RESET
Input low
voltage
VIH3
XIN, XOUT, XTIN, and XTOUT
VIL1
All input pins except those specified
below
VIL2
P0.2, P1, P4.0, P4.2, P5, P6, CE and
–
–
0.3 VDD
0.2 VDD
RESET
Output high
voltage
Output low
voltage
VIL3
XIN, XOUT, XTIN, and XTOUT
VOH1
VDD = 4.5 V to 5.5 V, EO;
IOH = – 1 mA
VDD–2.0
VOH2
VDD = 4.5 V to 5.5 V;
Other output ports;
IOH = – 1 mA
VDD–1.0
VOL1
VDD = 4.5 V to 5.5 V, EO;
IOL = 1 mA,
–
–
2.0
VOL2
VDD = 4.5 V to 5.5 V
Other output ports; IOL = 10 mA
–
–
2
0.1
–
VDD
VDD
Input high
leakage
current(note)
ILIH
VIN = VDD
All input pins
–
–
3
Input low
leakage
current(note)
ILIL
VIN = 0 V
All input pins
–
–
–3
Output high
leakage
current(note)
ILOH
VOUT = VDD
All output pins
–
–
3
Output low
leakage
current (note)
ILOL
VOUT = 0 V
All output pins
–
–
–3
NOTE:
18-4
Except for XIN, XOUT, XTIN, and XTOUT
µA
KS57C3316/P3316
KS57P3316 OTP
Table 18-4. D.C. Electrical Characteristics (Continued)
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
V
VLC0 output
voltage
VLC0
TA = 25 °C
0.6 VDD–
0.2
0.6 VDD
0.6 VDD
+ 0.2
VLC1 output
voltage
VLC1
TA = 25 °C
0.4 VDD–
0.2
0.4 VDD
0.4 VDD
+ 0.2
VLC2 output
voltage
VLC2
TA = 25 °C
0.2 VDD–
0.2
0.2 VDD
0.2 VDD
+ 0.2
COM output
voltage
deviation
VDC
VDD = 5V, (VLC0 - COMi I = 0 - 3 )
IO = ± 15 µA (I = 0 - 3)
–
± 45
± 120
SEG output
voltage
deviation
VDS
VDD = 5V, (VLC0 - COMi I = 0 - 3 )
IO = ± 15 µA (I = 0 - 3)
± 45
± 120
LCD output
voltage
deviation
RLCD
TA = 25 °C
70
100
150
ROSC1
VDD = 5.0 V, TA = 25 °C
XIN = VDD, XOUT = 0 V
300
600
1500
ROSC2
VDD = 5.0 V, TA = 25 °C
XTIN = VDD, XTOUT = 0 V
1500
3000
4500
Oscillator
feed back
resistors
Pull-down
resistor
RD
VDD = 5.0 V, VIN = VDD;
VCOFM, VCOAM, AMIF, and FMIF
15
30
45
Pull-up
resistor
RL1
VIN = 0 V; VDD = 5 V
Ports 1, 2, 3, 4, 5, and 6
25
47
100
VDD = 3 V
50
95
200
VIN = 0 V; VDD = 5 V
100
220
400
200
450
800
RL2
mV
kΩ
RESET
VDD = 3 V
18-5
KS57P3316 OTP
KS57C3316/P3316
Table 18-4. D.C. Electrical Characteristics (Concluded)
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Supply
Current(1)
Symbol
Conditions
Min
Typ
Max
Units
mA
IDD1 (2)
Main operating:
PCON = 0011B, SCMOD = 0000B
CE = VDD;
Crystal oscillator
C1 = C2 = 22 pF
VDD = 5 V ± 10%
4.5 MHz
–
5.5
27
IDD2 (2)
CE Low mate:
6.0 MHz
–
3.5
8
PCON = 0011B, SCMOD = 0000B
CE = 0 V
Crystal oscillator
C1 = C2 = 22 pF
VDD = 5 V ± 10%
4.5 MHz
2.5
5.5
VDD = 3 V ± 10%
6.0 MHz
1.6
4
4.5 MHz
1.2
3
1.0
2.5
IDD3 (2)
IDD4(2)
IDD5 (2)
IDD6(2)
IDD7(2)
Main idle mode:
6.0 MHz
–
PCON = 0111B, SCMOD =0000B
Crystal oscillator
C1 = C2 = 22 pF
VDD = 5 V ± 10%
4.5 MHz
0.9
2.0
VDD = 3 V ± 10%
6.0 MHz
0.5
1.0
4.5MHz
0.4
0.8
Sub operating mode:
PCON = 0011B, SCMOD = 1001B
CE = 0 V;
VDD = 3 V ± 10%
32 kHz crystal oscillator
Sub idle mode:
PCON = 0111B, SCMOD = 1001B
CE = 0 V;
VDD = 3 V ± 10%
32 kHz crystal oscillator
Stop mode:
CPU = fxt/4, SCMOD = 1101B
CE = 0 V;
VDD = 5 V ± 10%
–
15
30
–
6
15
–
0.5
3
Stop mode:
CPU = fx/4, SCMOD = 0100B
VDD = 5 V ± 10%
–
NOTES:
1. Supply current does not include current drawn through internal pull-up resistors and LCD voltage dividing resistors.
2. Data includes the power consumption for sub-system clock oscillation.
18-6
uA
KS57C3316/P3316
KS57P3316 OTP
Table 18-5. Main System Clock Oscillator Characteristics
(TA = – 40 °C + 85 °C, VDD = 1.8 V to 5.5 V)
Oscillator
Ceramic
Oscillator
Clock
Configuration
XOUT
XIN
C1
Crystal
Oscillator
C1
Test Condition
Min
Typ
Max
Units
VDD = 2.7 V to 5.5 V
0.4
–
6
MHz
Stabilization time (2)
Stabilization occurs
when VDD is equal to
the minimum oscillator
voltage range.
–
–
4
ms
Oscillation frequency
VDD = 2.7 V to 5.5 V
0.4
–
6
MHz
VDD = 4.5 V to 5.5 V
–
–
10
ms
VDD = 1.8 V to 4.5 V
–
–
30
XIN input frequency (1)
–
0.4
–
6
MHz
XIN input high and low
level width (tXH, tXL)
–
83.3
–
–
ns
Oscillation frequency
(1)
C2
XOUT
XIN
Parameter
(1)
C2
Stabilization time (2)
External
Clock
XIN
XOUT
NOTES:
1. Oscillation frequency and XIN input frequency data are for oscillator characteristics only.
2.
Stabilization time is the interval required for oscillator stabilization after a power-on occurs, or when stop mode is
terminated.
18-7
KS57P3316 OTP
KS57C3316/P3316
Table 18-6. Subsystem Clock Oscillator Characteristics
(TA = – 40 °C + 85 °C, VDD = 1.8 V to 5.5 V)
Oscillator
Crystal
Oscillator
Clock
Configuration
XTIN XTOUT
C1
Parameter
Test Condition
Min
Typ
Max
Units
–
32
32.768
35
kHz
VDD = 2.7 V to 5.5 V
–
1.0
2
s
VDD = 1.8 V to 4.5 V
–
–
10
XTIN input frequency (1)
–
32
–
100
kHz
XTIN input high and low
level width (tXTL, tXTH)
–
5
–
15
µs
Oscillation frequency
(1)
C2
Stabilization time (2)
External
Clock
XTIN XTOUT
NOTES:
1. Oscillation frequency and XTIN input frequency data are for oscillator characteristics only.
2.
Stabilization time is the interval required for oscillator stabilization after a power-on occurs.
18-8
KS57C3316/P3316
KS57P3316 OTP
Table 18-7. Input/Output Capacitance
(TA = 25 °C, VDD = 0 V )
Parameter
Symbol
Condition
Min
Typ
Max
Units
Input
capacitance
CIN
fCLK = 1 MHz; Unmeasured
pins are returned to VSS
–
–
15
pF
Output
capacitance
COUT
–
–
15
pF
CIO
–
–
15
pF
Min
Typ
Max
Units
VDD = 2.7 V to 5.5 V
0.67
–
64
µs
VDD = 1.8 V to 5.5 V
1.3
INT0
(2)
INT1, INT2, INT4, KS0–KS2
10
Input
10
I/O capacitance
Table 18-8. A.C. Electrical Characteristics
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Instruction cycle
Symbol
tCY
time (1)
Interrupt input
tINTH, tINTL
high, low width
and CE
Input Low Width
RESET
tRSL
Conditions
64
–
–
µs
1
–
µs
NOTES:
1. Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock/4 (fx/4) source.
2. Minimum value for INT0 is based on a clock of 2tCY or 128/fxx as assigned by the IMOD0 register setting.
Table 18-8. A.C. Electrical Characteristics (continued)
(TA = – 10 °C to + 70 °C, VDD = 3.5 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
A/D converting
Resolution
–
–
–
8
–
bits
Absolute accuracy
–
–
–
–
±2
LSB
AD conversion
time
tCON
–
17
34/fxx (note)
–
µs
Analog input
voltage
VIAN
–
VSS
–
VDD
V
Analog input
impedance
RAN
VDD = 5 V
2
1000
–
MΩ
NOTE: fxx stands for the system clock (fx or fxt).
18-9
KS57P3316 OTP
KS57C3316/P3316
Table 18-8. A.C. Electrical Characteristics (Continued)
(TA = – 40 °C to + 85 °C, VDD = 2.5 V to 3.5 V or VDD = 4.0 V to 5.5 V)
Parameter
VCOFM, VCOAM,
FMIF and AMIF
Input Voltage
(Peak to Peak)
Frequency
18-10
Symbol
Min
Typ
Max
Units
Sine wave input
0.3
–
VDD
V
fVCOAM
VCOAM mode, sine wave input;
VIN = 0.3VP-P
0.5
–
30
MHz
fVCOFM
VCOFM mode, sine wave input;
VIN = 0.3VP-P
30
150
fAMIF
AMIF mode, sine wave input;
VIN = 0.3VP-P
0.1
1.0
fFMIF
FMIF mode, sine wave input;
VIN = 0.3VP-P
5
15
VIN
Conditions
KS57C3316/P3316
KS57P3316 OTP
Table 18-8. A.C. Electrical Characteristics (continued)
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Instruction cycle
time (1)
TCL0 input
frequency
Symbol
tCY
fTI
Conditions
Min
Typ
Max
Units
VDD = 2.7 V to 5.5 V
0.67
–
64
µs
VDD = 1.8 V to 5.5 V
1.3
–
64
With subsystem clock (fxt)
114
122
125
0
–
1.5
VDD = 2.7 V to 5.5 V
VDD = 1.8 V to 5.5 V
TCL0 input high,
low width
SCK cycle time
SCK high, low
tTIH, tTIL
tKCY
tKH, tKL
width
0.48
VDD = 1.8. V to 5.5 V
1.8
VDD = 2.7 V to 5.5 V
External SCK source
800
Internal SCK source
650
VDD = 1.8 V to 5.5 V
External SCK source
3200
Internal SCK source
3800
VDD = 2.7 V to 5.5 V
External SCK source
400
VDD = 1.8 V to 5.5 V
External SCK source
SI setup time to
tSIK
SCK high
SI hold time to
tKSI
SCK high
Output delay for
SCK to SO
tKSO
1
VDD = 2.7. V to 5.5 V
Internal SCK source
–
–
µs
–
–
ns
–
–
–
–
–
–
–
300
tKCY/2- 50
1600
Internal SCK source
tKCY/2-150
External SCK source
100
Internal SCK source
150
External SCK source
400
Internal SCK source
400
VDD = 2.7 V to 5.5 V
External SCK source
MHz
–
Internal SCK source
250
VDD = 1.8 V to 5.5 V
External SCK source
1000
Internal SCK source
1000
NOTE: Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock/4 (fx/4) source.
18-11
KS57P3316 OTP
KS57C3316/P3316
Main Oscillator Frequency
CPU Clock
1.5 MHz
6 MHz
1.0475 MHz
1 MHz
4.19 MHz
750 kHz
3 MHz
250 kHz
400 kHz
15.6 kHz
1
2
3
4
5
6
7
Supply Voltage (V)
CPU Clock = 1/n x oscillator frequency (n = 4, 8 or 64)
When PLL/IFC operation, operating voltage range is 2.5 V
to 3.5 V or 4.0 V to 5.5 V.
Figure 18-2. Standard Operating Voltage Range
Table 18-9. RAM Data Retention Supply Voltage in Stop Mode
(TA = – 40 °C to + 85 °C)
Parameter
Symbol
Conditions
Data retention supply voltage
VDDDR
Normal operation
Data retention supply current
IDDDR
VDDDR = 1.8 V
18-12
Min
Typ
Max
Unit
1.8
–
5.5
V
–
0.1
1
µA
KS57C3316/P3316
KS57P3316 OTP
TIMING WAVEFORMS
Internal RESET
Operation
~
~
Idle Mode
Stop Mode
Operating Mode
Data Retention Mode
~
~
VDD
VDDDR
Execution of
STOP Instruction
RESET
tWAIT
tSREL
Figure 18-3. Stop Mode Release Timing When Initiated by RESET
Idle Mode
~
~
Normal
Operating
Mode
Stop Mode
Data Retention
~
~
VDD
VDDDR
Execution of
STOP Instruction
tSREL
tWAIT
Power-down Mode Terminating Signal
(Interrupt Request)
Figure 18-4. Stop Mode Release Timing When Initiated by an Interrupt Request
18-13
KS57P3316 OTP
KS57C3316/P3316
0.8 VDD
0.8 VDD
Measurement
Points
0.2 VDD
0.2 VDD
Figure 18-5. A.C. Timing Measurement Points (Except for XIN and XTIN)
1/fx
tXL
tXH
XIN
VDD - 0.1 V
0.1 V
Figure 18-6. Clock Timing Measurement at XIN
1/fxt
tXTL
tXTH
XTIN
VDD - 0.1 V
0.1 V
Figure 18-7. Clock Timing Measurement at XTIN
18-14
KS57C3316/P3316
KS57P3316 OTP
tRSL
RESET
0.2 VDD
Figure 18-8. Input Timing for RESET Signal
tINTL
INT0, 1, 2, 4,
KS0 to KS2
tINTH
0.8 VDD
0.2 VDD
Figure 18-9. Input Timing for External Interrupts and Quasi-Interrupts
18-15
KS57P3316 OTP
KS57C3316/P3316
NOTES
18-16
ELECTRICAL DATA
KS57C3316/P3316
Table 17-1. Absolute Maximum Ratings
(TA = 25 °C)
Parameter
Symbol
Conditions
Rating
Units
Supply voltage
VDD
–
- 0.3 to + 6.5
V
Input voltage
VIN
Output voltage
VO
–
Output current high
IOH
One I/O port active
- 15
All I/O ports active
-30
One I/O port active
+ 30 (peak value)
Output current low
IOL
Applies to all I/O ports
- 0.3 to VDD + 0.3
- 0.3 to VDD + 0.3
mA
+ 15 (note)
Total value for output ports
+ 100 (peak value)
+ 60 *
Operating temperature
Storage temperature
TA
- 40 to + 85
TSTG
- 65 to + 150
NOTE: The values for output current low ( IOL ) are calculated as Peak Value × Duty .
17-2
°C
KS57C3316/P3316
ELECTRICAL DATA
Table 17-2. D.C. Electrical Characteristics
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Input high
voltage
Symbol
Conditions
Min
Typ
Max
Units
–
VDD
V
VIH1
All input pins except those specified
below
0.7 VDD
VIH2
P0.2, P1, P4.0, P4.2, P5, P6, CE and
0.8 VDD
VDD
VDD–0.1
VDD
RESET
Input low
voltage
VIH3
XIN, XOUT, XTIN, and XTOUT
VIL1
All input pins except those specified
below
VIL2
P0.2, P1, P4.0, P4.2, P5, P6, CE and
–
–
0.3 VDD
0.2 VDD
RESET
Output high
voltage
Output low
voltage
VIL3
XIN, XOUT, XTIN, and XTOUT
VOH1
VDD = 4.5 V to 5.5 V, EO;
IOH = – 1 mA
VDD–2.0
VOH2
VDD = 4.5 V to 5.5 V;
Other output ports;
IOH = – 1 mA
VDD–1.0
VOL1
VDD = 4.5 V to 5.5 V, EO;
IOL = 1 mA,
–
–
2.0
VOL2
VDD = 4.5 V to 5.5 V
Other output ports; IOL = 10 mA
–
–
2
0.1
–
VDD
VDD
Input high
leakage
current(note)
ILIH
VIN = VDD
All input pins
–
–
3
Input low
leakage
current(note)
ILIL
VIN = 0 V
All input pins
–
–
-3
Output high
leakage
current(note)
ILOH
VOUT = VDD
All output pins
–
–
3
µA
NOTE: Except for XIN , XOUT, XTIN and XTOUT.
17-3
ELECTRICAL DATA
KS57C3316/P3316
Table 17-2. D.C. Electrical Characteristics (Continued)
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
V
VLC0 output
voltage
VLC0
TA = 25 °C
0.6 VDD–
0.2
0.6 VDD
0.6 VDD
+ 0.2
VLC1 output
voltage
VLC1
TA = 25 °C
0.4 VDD–
0.2
0.4 VDD
0.4 VDD
+ 0.2
VLC2 output
voltage
VLC2
TA = 25 °C
0.2 VDD–
0.2
0.2 VDD
0.2 VDD
+ 0.2
COM output
voltage
deviation
VDC
VDD = 5V, (VLC0 - COMi I = 0 - 3 )
IO = ± 15 µA (I = 0 - 3)
–
± 45
± 120
SEG output
voltage
deviation
VDS
VDD = 5V, (VLC0 - COMi I = 0 - 3 )
IO = ± 15 µA (I = 0 - 3)
± 45
± 120
LCD output
voltage
deviation
RLCD
TA = 25 °C
70
100
150
ROSC1
VDD = 5.0 V, TA = 25 °C
XIN = VDD, XOUT = 0 V
300
600
1500
ROSC2
VDD = 5.0 V, TA = 25 °C
XTIN = VDD, XTOUT = 0 V
1500
3000
4500
Oscillator
feed back
resistors
Pull-down
resistor
RD
VDD = 5.0 V, VIN = VDD;
VCOFM, VCOAM, AMIF, and FMIF
15
30
45
Pll-up
Resistor
RL1
VIN = 0 V; VDD = 5 V
Ports 1, 2, 3, 4, 5, and 6
25
47
100
VDD = 3 V
50
95
200
VIN = 0 V; VDD = 5 V
100
220
400
200
450
800
RL2
RESET
VDD = 3 V
17-4
mV
KΩ
KS57C3316/P3316
ELECTRICAL DATA
Table 17-2. D.C. Electrical Characteristics (Concluded)
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Supply
Current(1)
Symbol
Conditions
Min
Typ
Max
Units
mA
IDD1 (2)
Main operating, PLL operating:
PCON = 0011B, SCMOD = 0000B
CE = VDD;
Crystal oscillator
C1 = C2 = 22 pF
VDD = 5 V ± 10%
4.5 MHz
–
5.5
27
IDD2 (2)
CE Low,
6.0 MHz
–
3.5
8
PCON = 0011B, SCMOD = 0000B
CE = 0 V
Crystal oscillator
C1 = C2 = 22 pF
VDD = 5 V ± 10%
4.5 MHz
2.5
5.5
VDD = 3 V ± 10%
6.0 MHz
1.6
4
4.5 MHz
1.2
3
1.0
2.5
IDD3 (2)
IDD4(2)
IDD5 (2)
IDD6(2)
IDD7(2)
Main idle mode,
6.0 MHz
–
PCON = 0111B, SCMOD =0000B
Crystal oscillator
C1 = C2 = 22 pF
VDD = 5 V ± 10%
4.5 MHz
0.9
2.0
VDD = 3 V ± 10%
6.0 MHz
0.5
1.0
4.5MHz
0.4
0.8
Sub operating mode:
PCON = 0011B, SCMOD = 1001B
CE = 0 V;
VDD = 3 V ± 10%
32 kHz crystal oscillator
Sub idle mode:
PCON = 0111B, SCMOD = 1001B
CE = 0 V;
VDD = 3 V ± 10%
32 kHz crystal oscillator
Stop mode:
CPU = fxt/4, SCMOD = 1101B
CE = 0 V;
VDD = 5 V ± 10%
–
15
30
–
6
15
–
0.5
3
Stop mode:
CPU = fx/4, SCMOD = 0100B
VDD = 5 V ± 10%
–
uA
NOTES:
1. Supply current does not include current drawn through internal pull-up resistors and LCD voltage dividing resistors.
2. Data includes the power consumption for sub-system clock oscillation.
17-5
ELECTRICAL DATA
KS57C3316/P3316
Table 17-3. Main System Clock Oscillator Characteristics
(TA = – 40 °C + 85 °C, VDD = 1.8 V to 5.5 V)
Oscillator
Ceramic
Oscillator
Clock
Configuration
XOUT
XIN
C1
Crystal
Oscillator
C1
Test Condition
Min
Typ
Max
Units
VDD = 2.7 V to 5.5 V
0.4
–
6
MHz
Stabilization time (2)
Stabilization occurs
when VDD is equal to
the minimum oscillator
voltage range.
–
–
4
ms
Oscillation frequency
VDD = 2.7 V to 5.5 V
0.4
–
6
MHz
VDD = 4.5 V to 5.5 V
–
–
10
ms
VDD = 1.8 V to 4.5 V
–
–
30
XIN input frequency (1)
–
0.4
–
6
MHz
XIN input high and low
level width (tXH, tXL)
–
83.3
–
–
ns
Oscillation frequency
(1)
C2
XOUT
XIN
Parameter
(1)
C2
Stabilization time (2)
External
Clock
XIN
XOUT
NOTES:
1. Oscillation frequency and XIN input frequency data are for oscillator characteristics only.
2.
Stabilization time is the interval required for oscillator stabilization after a power-on occurs, or when stop mode is
terminated.
17-6
KS57C3316/P3316
ELECTRICAL DATA
Table 17-4. Subsystem Clock Oscillator Characteristics
(TA = – 40 °C + 85 °C, VDD = 1.8 V to 5.5 V)
Oscillator
Crystal
Oscillator
Clock
Configuration
XTIN XTOUT
C1
Parameter
Test Condition
Min
Typ
Max
Units
Oscillation frequency (1)
–
32
32.768
35
kHz
VDD = 2.7 V to 5.5 V
–
1.0
2
s
VDD = 1.8 V to 4.5 V
–
–
10
–
32
–
100
kHz
–
5
–
15
µs
C2
Stabilization time (2)
External
Clock
XTIN XTOUT
XTIN input frequency
(1)
XTIN input high and
low level width (tXTL,
tXTH)
NOTES:
1. Oscillation frequency and XTIN input frequency data are for oscillator characteristics only.
2.
Stabilization time is the interval required for oscillator stabilization after a power-on occurs.
17-7
ELECTRICAL DATA
KS57C3316/P3316
Table 17-5. Input/Output Capacitance
(TA = 25 °C, VDD = 0 V )
Parameter
Symbol
Condition
Min
Typ
Max
Units
Input
capacitance
CIN
fCLK = 1 MHz; Unmeasured
pins are returned to VSS
–
–
15
pF
Output
capacitance
COUT
–
–
15
pF
CIO
–
–
15
pF
Min
Typ
Max
Units
VDD = 2.7 V to 5.5 V
0.67
–
64
µs
VDD = 1.8 V to 5.5 V
1.3
INT0
(2)
INT1, INT2, INT4, KS0–KS2
10
Input
10
I/O capacitance
Table 17-6. A.C. Electrical Characteristics
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Instruction cycle
Symbol
tCY
time (1)
Interrupt input
tINTH, tINTL
high, low width
and CE
Input Low Width
RESET
tRSL
Conditions
64
–
–
µs
1
–
µs
NOTES:
1. Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock/4 (fx/4) source.
2. Minimum value for INT0 is based on a clock of 2tCY or 128/fxx as assigned by the IMOD0 register setting.
Table 17-6. A.C. Electrical Characteristics (Continued)
(TA = – 10 °C to + 70 °C, VDD = 3.5 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
A/D converting
Resolution
–
–
–
8
–
bits
Absolute accuracy
–
–
–
–
±2
LSB
AD conversion
time
tCON
–
17
34/fxx (note)
–
µs
Analog input
voltage
VIAN
–
VSS
–
VDD
V
Analog input
impedance
RAN
VDD = 5 V
2
1000
–
MΩ
NOTE: fxx stands for the system clock (fx or fxt).
17-8
KS57C3316/P3316
ELECTRICAL DATA
Table 17-6. A.C. Electrical Characteristics (Continued)
(TA = – 40 °C to + 85 °C, VDD = 2.5 V to 3.5 V or VDD = 4.0 V to 5.5 V)
Parameter
VCOFM, VCOAM,
FMIF and AMIF
Input Voltage
(Peak to Peak)
Frequency
Symbol
Min
Typ
Max
Units
Sine wave input
0.3
–
VDD
V
fVCOAM
VCOAM mode, sine wave input;
VIN = 0.3VP-P
0.5
–
30
MHz
fVCOFM
VCOFM mode, sine wave input;
VIN = 0.3VP-P
30
150
fAMIF
AMIF mode, sine wave input;
VIN = 0.3VP-P
0.1
1.0
fFMIF
FMIF mode, sine wave input;
VIN = 0.3VP-P
5
15
VIN
Conditions
17-9
ELECTRICAL DATA
KS57C3316/P3316
Table 17-6. A.C. Electrical Characteristics (Concluded)
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Instruction cycle
time (1)
TCL0 input
frequency
Symbol
tCY
fTI
Conditions
Min
Typ
Max
Units
VDD = 2.7 V to 5.5 V
0.67
–
64
µs
VDD = 1.8 V to 5.5 V
1.3
–
64
With subsystem clock (fxt)
114
122
125
0
–
1.5
VDD = 2.7 V to 5.5 V
VDD = 1.8 V to 5.5 V
TCL0 input high,
low width
SCK cycle time
SCK high, low
tTIH, tTIL
tKCY
tKH, tKL
width
0.48
VDD = 1.8. V to 5.5 V
1.8
VDD = 2.7 V to 5.5 V
External SCK source
800
Internal SCK source
650
VDD = 1.8 V to 5.5 V
External SCK source
3200
Internal SCK source
3800
VDD = 2.7 V to 5.5 V
External SCK source
400
VDD = 1.8 V to 5.5 V
External SCK source
SI setup time to
tSIK
SCK high
SI hold time to
tKSI
SCK high
Output delay for
SCK to SO
tKSO
1
VDD = 2.7. V to 5.5 V
Internal SCK source
–
–
µs
–
–
ns
–
–
–
–
–
–
–
300
tKCY/2- 50
1600
Internal SCK source
tKCY/2-150
External SCK source
100
Internal SCK source
150
External SCK source
400
Internal SCK source
400
VDD = 2.7 V to 5.5 V
External SCK source
MHz
–
Internal SCK source
250
VDD = 1.8 V to 5.5 V
External SCK source
1000
Internal SCK source
1000
NOTE: Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock/4 (fx/4) source.
17-10
KS57C3316/P3316
ELECTRICAL DATA
CPU Clock
Main Oscillator Frequency
1.5 MHz
6 MHz
1.0475 MHz
1 MHz
4.19 MHz
750 kHz
3 MHz
250 kHz
400 kHz
15.6 kHz
1
2
3
4
5
6
7
Supply Voltage (V)
CPU Clock = 1/n x oscillator frequency (n = 4, 8 or 64)
When PLL/IFC operation, operating voltage range is 2.5 V
to 3.5 V or 4.0 V to 5.5 V.
Figure 17-1. Standard Operating Voltage Range
Table 17-7. RAM Data Retention Supply Voltage in Stop Mode
(TA = – 40 °C to + 85 °C)
Parameter
Symbol
Conditions
Data retention supply voltage
VDDDR
Normal operation
Data retention supply current
IDDDR
VDDDR = 1.8 V
Min
Typ
Max
Unit
1.8
–
5.5
V
–
0.1
1
µA
17-11
ELECTRICAL DATA
KS57C3316/P3316
TIMING WAVEFORMS
Internal RESET
Operation
~
~
Idle Mode
Stop Mode
Operating Mode
Data Retention Mode
~
~
VDD
VDDDR
Execution of
STOP Instruction
RESET
tWAIT
tSREL
Figure 17-2. Stop Mode Release Timing When Initiated by RESET
Idle Mode
~
~
Normal
Operating
Mode
Stop Mode
Data Retention
~
~
VDD
VDDDR
Execution of
STOP Instruction
tSREL
tWAIT
Power-down Mode Terminating Signal
(Interrupt Request)
Figure 17-3. Stop Mode Release Timing When Initiated by an Interrupt Request
17-12
KS57C3316/P3316
ELECTRICAL DATA
0.8 VDD
0.8 VDD
Measurement
Points
0.2 VDD
0.2 VDD
Figure 17-4. A.C. Timing Measurement Points (Except for XIN and XTIN)
1/fx
tXL
tXH
XIN
VDD - 0.1 V
0.1 V
Figure 17-5. Clock Timing Measurement at XIN
1/fxt
tXTL
tXTH
XTIN
VDD - 0.1 V
0.1 V
Figure 17-6. Clock Timing Measurement at XTIN
17-13
ELECTRICAL DATA
KS57C3316/P3316
tRSL
RESET
0.2 VDD
Figure 17-7. Input Timing for RESET Signal
tINTL
INT0, 1, 2, 4,
KS0 to KS2
tINTH
0.8 VDD
0.2 VDD
Figure 17-8. Input Timing for External Interrupts and Quasi-Interrupts
17-14
KS57C3316/P3316
MECHANICAL DATA
18
MECHANICAL DATA
OVERVIEW
This section contains the following information about the device package:
— Package dimensions in millimeters
— Pad diagram
— Pad/pin coordinate data table
23.90 ± 0.30
0-8
20.00
± 0.20
+ 0.10
± 0.20
14.00
0.10 MAX
80-QFP-1420C
0.80 ± 0.20
± 0.30
17.90
0.15 - 0.05
#80
#1
0.80
0.35 + 0.10
0.05 MIN
0.15 MAX
(0.80)
2.65 ± 0.10
3.00 MAX
0.80
± 0.20
NOTE: Dimensions are in millimeters.
Figure 18-1. 80-QFP-1420C Package Dimensions
18-1
KS57C3316/P3316
19
KS57P3316 OTP
KS57P3316 OTP
OVERVIEW
The KS57P3316 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the
KS57C3316 microcontroller. It has an on-chip EPROM instead of masked ROM. The EPROM is accessed by a
serial data format.
The KS57P3316 is fully compatible with the KS57C3316, both in function and in pin configuration. Because of
its simple programming requirements, the KS57P3316 is ideal for use as an evaluation chip for the KS57C3316.
19-1
KS57P3316 OTP
KS57C3316/P3316
VDD1
E0
CE
P3.0
P3.1
P3.2
P3.3
P0.0/BTCO
P0.1/TCLO0
P0.2/TCL0
P0.3/BUZ
P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/INT4
P4.0/ SCK
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
P4.1/SO
P4.2/SI
P4.3/CLO
P5.0/ADC0
P5.1/ADC1
P5.2/ADC2
P5.3/ADC3
P6.0/KS0
P6.1/KS1
SDAT/P6.2/KS2
SCLK/P6.3/KS3
VDD/VDD0
VSS/VSS0
XOUT
XIN
VPP/TEST
XTIN
XTOUT
RESET /RESET
BIAS
VLC0
VLC1
VLC2
COM0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
KS57P3316
(80-QFP Top View)
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
SEG12/P10.0
SEG11/P9.3
SEG10/P9.2
SEG9/P9.1
SEG8/P9.0
SEG7/P8.3
SEG6/P8.2
SEG5/P8.1
SEG4/P8.0
SEG3/P7.3
SEG2/P7.2
SEG1/P7.1
SEG0/P7.0
COM3
COM2
COM1
Figure 19-1. KS57P3316 Pin Assignments (80-QFP)
19-2
FMIF
AMIF
VSS1
VCOAM
VCOFM
P2.3
P2.2
P2.1
P2.0
SEG27/P13.3
SEG26/P13.2
SEG25/P13.1
SEG24/P13.0
SEG23/P12.3
SEG22/P12.2
SEG21/P12.1
SEG20/P12.0
SEG19/11.3
SEG18/P11.2
SEG17/P11.1
SEG16/P11.0
SEG15/P10.3
SEG14/P10.2
SEG13/P10.3
KS57C3316/P3316
KS57P3316 OTP
Table 19-1. Pin Descriptions Used to Read/Write the EPROM
Main Chip
During Programming
Pin Name
Pin Name
Pin No.
I/O
Function
P6.2
SDAT
10
I/O
Serial data pin. Output port when reading and input port
when writing. Can be assigned as a Input or push-pull
output port.
P6.3
11
I/O
Serial clock pin. Input only pin.
TEST
SCLK
VPP (TEST)
16
I
Power supply pin for EPROM cell writing (indicates that
OTP enters into the writing mode). When 12.5 V is
applied, OTP is in writing mode and when 5 V is applied,
OTP is in reading mode.
RESET
RESET
19
I
Chip initialization
VDD / VSS
VDD / VSS
12/13
I
Logic power supply pin. VDD should be tied to +5 V
during programming.
Table 19-2. Comparison of KS57P3316 and KS57C3316 Features
Characteristic
KS57P3316
KS57C3316
Program Memory
16K bytes EPROM
16K bytes mask ROM
Operating Voltage (VDD)
1.8 V to 5.5 V
2.5 V to 3.5 V or 4.0 V to 5.5 V
at PLL/IFC operation
1.8 V to 5.5 V
2.5 V to 3.5 V or 4.0 V to 5.5 V
at PLL/IFC operation
OTP Programming Mode
VDD = 5 V, VPP (TEST) = 12.5 V
Pin Configuration
80 QFP
80 QFP
EPROM Programmability
User Program 1 time
Programmed at the factory
–
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the Vpp (TEST) pin of the KS57P3316, the EPROM programming mode is entered.
The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed
in Table 17-3 below.
Table 19-3. Operating Mode Selection Criteria
VDD
5V
Vpp(TEST)
REG/MEM
Address(A15-A0)
R/W
Mode
5V
0
0000H
1
EPROM read
12.5 V
0
0000H
0
EPROM program
12.5 V
0
0000H
1
EPROM verify
12.5 V
1
0E3FH
0
EPROM read protection
NOTE: "0" means low level; "1" means high level.
19-3
KS57P3316 OTP
KS57C3316/P3316
Table 19-4. D.C. Electrical Characteristics
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Input high
voltage
Symbol
Conditions
Min
Typ
Max
Units
–
VDD
V
VIH1
All input pins except those specified
below
0.7 VDD
VIH2
P0.2, P1, P4.0, P4.2, P5, P6, CE and
0.8 VDD
VDD
VDD–0.1
VDD
RESET
Input low
voltage
VIH3
XIN, XOUT, XTIN, and XTOUT
VIL1
All input pins except those specified
below
VIL2
P0.2, P1, P4.0, P4.2, P5, P6, CE and
–
–
0.3 VDD
0.2 VDD
RESET
Output high
voltage
Output low
voltage
VIL3
XIN, XOUT, XTIN, and XTOUT
VOH1
VDD = 4.5 V to 5.5 V, EO;
IOH = – 1 mA
VDD–2.0
VOH2
VDD = 4.5 V to 5.5 V;
Other output ports;
IOH = – 1 mA
VDD–1.0
VOL1
VDD = 4.5 V to 5.5 V, EO;
IOL = 1 mA,
–
–
2.0
VOL2
VDD = 4.5 V to 5.5 V
Other output ports; IOL = 10 mA
–
–
2
0.1
–
VDD
VDD
Input high
leakage
current(note)
ILIH
VIN = VDD
All input pins
–
–
3
Input low
leakage
current(note)
ILIL
VIN = 0 V
All input pins
–
–
–3
Output high
leakage
current(note)
ILOH
VOUT = VDD
All output pins
–
–
3
Output low
leakage
current (note)
ILOL
VOUT = 0 V
All output pins
–
–
–3
NOTE:
19-4
Except for XIN, XOUT, XTIN, and XTOUT
µA
KS57C3316/P3316
KS57P3316 OTP
Table 19-4. D.C. Electrical Characteristics (Continued)
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
V
VLC0 output
voltage
VLC0
TA = 25 °C
0.6 VDD–
0.2
0.6 VDD
0.6 VDD
+ 0.2
VLC1 output
voltage
VLC1
TA = 25 °C
0.4 VDD–
0.2
0.4 VDD
0.4 VDD
+ 0.2
VLC2 output
voltage
VLC2
TA = 25 °C
0.2 VDD–
0.2
0.2 VDD
0.2 VDD
+ 0.2
COM output
voltage
deviation
VDC
VDD = 5V, (VLC0 - COMi I = 0 - 3 )
IO = ± 15 µA (I = 0 - 3)
–
± 45
± 120
SEG output
voltage
deviation
VDS
VDD = 5V, (VLC0 - COMi I = 0 - 3 )
IO = ± 15 µA (I = 0 - 3)
± 45
± 120
LCD output
voltage
deviation
RLCD
TA = 25 °C
70
100
150
Oscillator
feed back
resistors
ROSC1
VDD = 5.0 V, TA = 25 °C
XIN = VDD, XOUT = 0 V
300
600
1500
ROSC2
VDD = 5.0 V, TA = 25 °C
XTIN = VDD, XTOUT = 0 V
1500
3000
4500
Pull-down
resistor
RD
VDD = 5.0 V, VIN = VDD;
VCOFM, VCOAM, AMIF, and FMIF
15
30
45
Pull-up
resistor
RL1
VIN = 0 V; VDD = 5 V
Ports 1, 2, 3, 4, 5, and 6
25
47
100
VDD = 3 V
50
95
200
VIN = 0 V; VDD = 5 V
100
220
400
200
450
800
RL2
mV
kΩ
RESET
VDD = 3 V
19-5
KS57P3316 OTP
KS57C3316/P3316
Table 19-4. D.C. Electrical Characteristics (Concluded)
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Supply
Current(1)
Symbol
IDD1
(2)
IDD2
(2)
IDD3
(2)
IDD4(2)
IDD5 (2)
IDD6(2)
IDD7(2)
Conditions
Min
Typ
Max
Units
Main operating:
PCON = 0011B, SCMOD = 0000B
CE = VDD;
Crystal oscillator
C1 = C2 = 22 pF
VDD = 5 V ± 10%
4.5 MHz
–
5.5
27
mA
CE Low mate:
6.0 MHz
–
3.5
8
PCON = 0011B, SCMOD = 0000B
CE = 0 V
Crystal oscillator
C1 = C2 = 22 pF
VDD = 5 V ± 10%
4.5 MHz
2.5
5.5
VDD = 3 V ± 10%
6.0 MHz
1.6
4
4.5 MHz
1.2
3
1.0
2.5
Main idle mode:
6.0 MHz
–
PCON = 0111B, SCMOD =0000B
Crystal oscillator
C1 = C2 = 22 pF
VDD = 5 V ± 10%
4.5 MHz
0.9
2.0
VDD = 3 V ± 10%
6.0 MHz
0.5
1.0
4.5MHz
0.4
0.8
Sub operating mode:
PCON = 0011B, SCMOD = 1001B
CE = 0 V;
VDD = 3 V ± 10%
32 kHz crystal oscillator
Sub idle mode:
PCON = 0111B, SCMOD = 1001B
CE = 0 V;
VDD = 3 V ± 10%
32 kHz crystal oscillator
Stop mode:
CPU = fxt/4, SCMOD = 1101B
CE = 0 V;
VDD = 5 V ± 10%
–
15
30
–
6
15
–
0.5
3
Stop mode:
CPU = fx/4, SCMOD = 0100B
VDD = 5 V ± 10%
–
NOTES:
1. Supply current does not include current drawn through internal pull-up resistors and LCD voltage dividing resistors.
2. Data includes the power consumption for sub-system clock oscillation.
19-6
uA
KS57C3316/P3316
KS57P3316 OTP
Table 19-5. Main System Clock Oscillator Characteristics
(TA = – 40 °C + 85 °C, VDD = 1.8 V to 5.5 V)
Oscillator
Ceramic
Oscillator
Clock
Configuration
XIN
C1
Crystal
Oscillator
XIN
C1
XOUT
Parameter
Test Condition
Min
Typ
Max
Units
Oscillation frequency
VDD = 2.7 V to 5.5 V
0.4
–
6
MHz
Stabilization time (2)
Stabilization occurs
when VDD is equal to
the minimum oscillator
voltage range.
–
–
4
ms
Oscillation frequency
VDD = 2.7 V to 5.5 V
0.4
–
6
MHz
VDD = 4.5 V to 5.5 V
–
–
10
ms
VDD = 1.8 V to 4.5 V
–
–
30
XIN input frequency (1)
–
0.4
–
6
MHz
XIN input high and low
level width (tXH, tXL)
–
83.3
–
–
ns
(1)
C2
XOUT
(1)
C2
Stabilization time (2)
External
Clock
XIN
XOUT
NOTES:
1. Oscillation frequency and XIN input frequency data are for oscillator characteristics only.
2.
Stabilization time is the interval required for oscillator stabilization after a power-on occurs, or when stop mode is
terminated.
19-7
KS57P3316 OTP
KS57C3316/P3316
Table 19-6. Subsystem Clock Oscillator Characteristics
(TA = – 40 °C + 85 °C, VDD = 1.8 V to 5.5 V)
Oscillato
r
Clock
Configuration
Crystal
Oscillator
XTIN XTOUT
C1
Parameter
Test Condition
Min
Typ
Max
Units
–
32
32.768
35
kHz
VDD = 2.7 V to 5.5 V
–
1.0
2
s
VDD = 1.8 V to 4.5 V
–
–
10
XTIN input frequency (1)
–
32
–
100
kHz
XTIN input high and low
level width (tXTL, tXTH)
–
5
–
15
µs
Oscillation frequency
(1)
C2
Stabilization time (2)
External
Clock
XTIN XTOUT
NOTES:
1. Oscillation frequency and XTIN input frequency data are for oscillator characteristics only.
2.
19-8
Stabilization time is the interval required for oscillator stabilization after a power-on occurs.
KS57C3316/P3316
KS57P3316 OTP
Table 19-7. Input/Output Capacitance
(TA = 25 °C, VDD = 0 V )
Parameter
Symbol
Condition
Min
Typ
Max
Units
Input
capacitance
CIN
fCLK = 1 MHz; Unmeasured
pins are returned to VSS
–
–
15
pF
Output
capacitance
COUT
–
–
15
pF
CIO
–
–
15
pF
Min
Typ
Max
Units
VDD = 2.7 V to 5.5 V
0.67
–
64
µs
VDD = 1.8 V to 5.5 V
1.3
I/O capacitance
Table 19-8. A.C. Electrical Characteristics
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Instruction cycle
Symbol
tCY
time (1)
Interrupt input
tINTH, tINTL INT0
high, low width
and CE
Input Low Width
RESET
Conditions
tRSL
64
(2)
INT1, INT2, INT4, KS0–KS2
10
Input
10
–
–
µs
1
–
µs
NOTES:
1. Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock/4 (fx/4) source.
2. Minimum value for INT0 is based on a clock of 2tCY or 128/fxx as assigned by the IMOD0 register setting.
Table 19-8. A.C. Electrical Characteristics (continued)
(TA = – 10 °C to + 70 °C, VDD = 3.5 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
A/D converting
Resolution
–
–
–
8
–
bits
Absolute
accuracy
–
–
–
–
±2
LSB
AD conversion
time
tCON
–
17
34/fxx (note)
–
µs
Analog input
voltage
VIAN
–
VSS
–
VDD
V
Analog input
impedance
RAN
VDD = 5 V
2
1000
–
MΩ
NOTE: fxx stands for the system clock (fx or fxt).
19-9
KS57P3316 OTP
KS57C3316/P3316
Table 19-8. A.C. Electrical Characteristics (Continued)
(TA = – 40 °C to + 85 °C, VDD = 2.5 V to 3.5 V or VDD = 4.0 V to 5.5 V)
Parameter
Symbol
VCOFM, VCOAM,
FMIF and AMIF
Input Voltage
(Peak to Peak)
VIN
Frequency
19-10
Conditions
Min
Typ
Max
Units
Sine wave input
0.3
–
VDD
V
fVCOAM
VCOAM mode, sine wave input;
VIN = 0.3VP-P
0.5
–
30
MHz
fVCOFM
VCOFM mode, sine wave input;
VIN = 0.3VP-P
30
150
fAMIF
AMIF mode, sine wave input;
VIN = 0.3VP-P
0.1
1.0
fFMIF
FMIF mode, sine wave input;
VIN = 0.3VP-P
5
15
KS57C3316/P3316
KS57P3316 OTP
Table 19-8. A.C. Electrical Characteristics (continued)
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Instruction cycle
time (1)
TCL0 input
frequency
Symbol
tCY
fTI
Conditions
Min
Typ
Max
Units
VDD = 2.7 V to 5.5 V
0.67
–
64
µs
VDD = 1.8 V to 5.5 V
1.3
–
64
With subsystem clock (fxt)
114
122
125
0
–
1.5
VDD = 2.7 V to 5.5 V
VDD = 1.8 V to 5.5 V
TCL0 input high,
low width
SCK cycle time
SCK high, low
tTIH, tTIL
tKCY
tKH, tKL
width
0.48
VDD = 1.8. V to 5.5 V
1.8
VDD = 2.7 V to 5.5 V
External SCK source
800
Internal SCK source
650
VDD = 1.8 V to 5.5 V
External SCK source
3200
Internal SCK source
3800
VDD = 2.7 V to 5.5 V
External SCK source
400
VDD = 1.8 V to 5.5 V
External SCK source
SI setup time to
tSIK
SCK high
SI hold time to
tKSI
SCK high
Output delay for
SCK to SO
tKSO
1
VDD = 2.7. V to 5.5 V
Internal SCK source
–
–
µs
–
–
ns
–
–
–
–
–
–
–
300
tKCY/2- 50
1600
Internal SCK source
tKCY/2-150
External SCK source
100
Internal SCK source
150
External SCK source
400
Internal SCK source
400
VDD = 2.7 V to 5.5 V
External SCK source
MHz
–
Internal SCK source
250
VDD = 1.8 V to 5.5 V
External SCK source
1000
Internal SCK source
1000
NOTE: Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock/4 (fx/4) source.
19-11
KS57P3316 OTP
KS57C3316/P3316
CPU Clock
Main Oscillator Frequency
1.5 MHz
6 MHz
1.0475 MHz
1 MHz
4.19 MHz
750 kHz
3 MHz
250 kHz
400 kHz
15.6 kHz
1
2
3
4
5
6
7
Supply Voltage (V)
CPU Clock = 1/n x oscillator frequency (n = 4, 8 or 64)
When PLL/IFC operation, operating voltage range is 2.5 V
to 3.5 V or 4.0 V to 5.5 V.
Figure 19-2. Standard Operating Voltage Range
Table 19-9. RAM Data Retention Supply Voltage in Stop Mode
(TA = – 40 °C to + 85 °C)
Parameter
Symbol
Data retention supply voltage
VDDDR
Normal operation
Data retention supply current
IDDDR
VDDDR = 1.8 V
19-12
Conditions
Min
Typ
Max
Unit
1.8
–
5.5
V
–
0.1
1
µA
KS57C3316/P3316
KS57P3316 OTP
TIMING WAVEFORMS
Internal RESET
Operation
~
~
Idle Mode
Stop Mode
Operating Mode
Data Retention Mode
~
~
VDD
VDDDR
Execution of
STOP Instruction
RESET
tWAIT
tSREL
Figure 19-3. Stop Mode Release Timing When Initiated by RESET
Idle Mode
~
~
Normal
Operating
Mode
Stop Mode
Data Retention
~
~
VDD
VDDDR
Execution of
STOP Instruction
tSREL
tWAIT
Power-down Mode Terminating Signal
(Interrupt Request)
Figure 19-4. Stop Mode Release Timing When Initiated by an Interrupt Request
19-13
KS57P3316 OTP
KS57C3316/P3316
0.8 VDD
0.8 VDD
Measurement
Points
0.2 VDD
0.2 VDD
Figure 19-5. A.C. Timing Measurement Points (Except for XIN and XTIN)
1/fx
tXL
tXH
XIN
VDD - 0.1 V
0.1 V
Figure 19-6. Clock Timing Measurement at XIN
1/fxt
tXTL
tXTH
XTIN
VDD - 0.1 V
0.1 V
Figure 19-7. Clock Timing Measurement at XTIN
19-14
KS57C3316/P3316
KS57P3316 OTP
tRSL
RESET
0.2 VDD
Figure 19-8. Input Timing for RESET Signal
tINTL
INT0, 1, 2, 4,
KS0 to KS2
tINTH
0.8 VDD
0.2 VDD
Figure 19-9. Input Timing for External Interrupts and Quasi-Interrupts
19-15
KS57P3316 OTP
KS57C3316/P3316
NOTES
19-16