S3C7031/7032 1 PRODUCT OVERVIEW PRODUCT OVERVIEW OVER VIEW The S3C7031/7032 single-chip CMOS microcontroller has been designed for high performance using Samsung's newest 4-bit CPU core. With comparator inputs, high-current LED direct-drive pins, serial I/O interface, and a versatile 8-bit timer/counter, the S3C7031/7032 offers an excellent design solution for a wide range of applications such as mouse controllers, subsystem controllers, and toys. Up to 15 pins of the 20-pin DIP or 20-pin SOP package can be dedicated to I/O. Pull-up resistors are assignable to all of the pins by software. Four vectored interrupts provide fast response to internal and external events. In addition, the S3C7031/7032's advanced CMOS technology provides for very low power consumption and a wide operating voltage range. DEVELOPMENT SUPPORT The Samsung Microcontroller Development System, SMDS, provides you with a complete PC-based development environment for KS57-series microcontrollers that is powerful, reliable, and portable. In addition to its easy to use window-oriented program development structure, the SMDS toolset includes versatile debugging, trace, instruction timing, and performance measurement applications. The Samsung Generalized Assembler (SAMA) has been designed specifically for the SMDS environment and accepts assembly language sources in a variety of microprocessor formats. SAMA generates industry-standard object files that also contain program control data for SMDS compatibility. 1-1 PRODUCT OVERVIEW FEATURES S3C7031/7032 8-Bit Serial I/O Interface — 8-bit transmit/receive mode Memory — 8-bit receive-only mode — 1024 × 8-bit program memory (S3C7031) (ROM) — LSB-first or MSB-first transmission selectable — 2048 × 8-bit program memory (S3C7032) (ROM) — 128 × 4-bit data memory (S3C7031) (RAM) — 256 × 4-bit data memory (S3C7032) (RAM) I/O Pins — Up to 15 pins for 20-DIP and 20-SOP package — Internal or external clock source Interrupts — One external interrupt vector — Three internal interrupt vectors — Two quasi-interrupts Memory-Mapped I/O Structure Comparator Inputs Two Power-Down Modes — 4-channel mode Internal reference: 4-bit resolution — Idle mode: Only the CPU clock stops — 3-channel mode External reference — Stop mode: Main system clock stops On-Chip Crystal, Ceramic, Or RC Oscillator — Crystal/ceramic: 4.19 MHz (typical) 8-Bit Basic Timer — Programmable interval timer 8-Bit Timer/Counter — Programmable interval timer — RC: 1 MHz (typical) — CPU clock divider circuit (by 4, 8, or 64) Frequency Outputs — Eight frequency outputs to the CLO pin — External event counter function — Timer clock output to TIO pin Instruction Execution Times Watch Timer — 0.95, 1.91, 15.3 µs at 4.19 MHz (5 V), 4 µs at 1 MHz (2.7 V) — Time interval generation: 0.5 s, 3.9 ms at 4.19 MHz Operating Temperature: — Four frequency outputs to BUZ pin — – 40°C to 85°C Bit Sequential Carrier Operating Voltage Range: — 16-bit serial data transfer in arbitrary format — 2.7 V to 6.0 V Package Type: — 20-DIP, 20-SOP 1-2 S3C7031/7032 PRODUCT OVERVIEW BLOCK DIAGRAM XIN RESET XOUT Basic Timer I/O Port 0 Interrupt Control Block Clock Watch Timer Internal Interrupts P2.0 - P2.3 P3.0/SCK P3.1/SO P3.2/SI P3.3/BUZ Stack Pointer Program Counter 8-Bit Timer/ Counter Program Status Word Comparator P0.0/CLO P0.1/TIO P0.2/INT1 I/O Port 2 Instruction Decoder I/O Port 3 Arithmetic and Logic Unit Flags Serial I/O Port Data Memory (2) I/O Port 1 P0.0/KS0/CIN0 P0.1/KS1/CIN1 P0.2/KS2/CIN2 P0.3/KS3/CIN3 Program Memory (1) NOTES: 1. Program Memory is 1-KByte (S3C7031) and 2-KByte (S3C7032). 2. Data Memory is 128 x 4bit (S3C7031) and 256 x 4bit (S3C7032). Figure 1-1. S3C7031/7032 Block Diagram 1-3 PRODUCT OVERVIEW S3C7031/7032 PIN ASSIGNMENTS P0.0/CLO 1 20 VDD P0.1/TIO 2 19 P3.3/BUZ P0.2/INT1 3 18 P3.2/SI P0.0/KS0/CIN0 4 17 P3.1/SO P0.1/KS1/CIN1 5 16 P3.0/SCK P0.2/KS2/CIN2 6 15 P2.3 P0.3/KS3/CIN3 7 14 P2.2 XOUT 8 13 P2.1 XIN 9 12 P2.0 VSS 10 11 RESET NOTE: KS57C7031/ KS57C7032 (Top view) Pin assignments are identical for the 20-pin DIP and SOP package. Figure 1-2. S3C7031/7032 Pin Assignment Diagram (20-pin DIP/SOP Package) PIN DESCRIPTIONS Table 1-1. S3C7031/7032 Pin Descriptions Pin Name Pin Type Description Number Share Pin P0.0 P0.1 P0.2 I/O 3-bit I/O port. 1-bit or 3-bit read/write and test is possible. Pull-up resistors are individually assignable to input pins by software and are automatically disabled for output pins. Pins are individually configurable as input or output. 1 2 3 CLO TIO INT1 P1.0 P1.1 P1.2 P1.3 I/O Same as port 0 except that port 1 is a 4-bit I/O port. 4 5 6 7 KS0/CIN0 KS1/CIN1 KS2/CIN2 KS3/CIN3 1-4 S3C7031/7032 PRODUCT OVERVIEW Table 1-1. S3C7031/7032 Pin Descriptions (Continued) Pin Name Pin Type Description Number Share Pin P2.0-P2.3 P3.0 P3.1 P3.2 P3.3 I/O 4-bit I/O port. 1-bit, 4-bit or 8-bit read/write and test is possible. Pins are individually configurable as input or output. Pull-up resistors are individually assignable to input pins by software and are automatically disabled for output pins. Ports are software configurable as n-channel open-drain outputs or push-pull output by software. Ports 2 and 3 can be paired to enable 8-bit data transfer. 12-15 16 17 18 19 –SCK SO SI BUZ CLO I/O Eight frequency outputs 1 P0.0 TIO I/O External clock input or timer clock output 2 P0.1 INT1 I/O External interrupts with rising or falling edge detection 3 P0.2 KS0-KS3 I/O Quasi-interrupts with falling edge detection 4-7 P1.0-P1.3 CIN0-CIN3 I/O 4-channel comparator input. CIN0-CIN2: comparator input only. CIN3: comparator input or external reference input 4-7 P1.0-P1.3 SCK I/O Serial interface clock signal 16 P3.0 SO I/O Serial data output 17 P3.1 SI I/O Serial data input 18 P3.2 BUZ I/O 2 kHz, 4 kHz, 8 kHz, or 16 kHz frequency output at 4.19 MHz for buzzer sound 19 P3.3 XIN, XOUT –- Crystal, ceramic, or RC signal for system clock 9, 8 –- RESET I Reset signal 11 –- VDD –- Power supply 20 –- VSS –- Ground 10 –- Table 1-2. Overview of S3C7031/7032 Pin Data Pin Numbers Pin Names Share Pins I/O Type Reset Value Circuit Type 1-3 P0.0-P0.2 CLO, TIO, INT1 I/O Input 2 4-7 P1.0-P1.3 KS0/CIN0-KS3/CIN3 I/O Input 4 12-5 P2.0-P2.3 I/O Input 3 16-19 P3.0-P3.3 I/O Input 3 11 RESET –- I –- 1 20, 10 VDD, VSS –- –- –- –- –- –- –- –- 9, 8 XIN, XOUT – SCK, SO, SI, BUZ 1-5 PRODUCT OVERVIEW S3C7031/7032 PIN CIRCUIT DIAGRAMS In Schmitt Trigger Figure 1-3. Pin Circuit Type 1 VDD Pull-up Registor Typical 50 KΩ (VDD = 5V) Pull-up Enable VDD Data I/O Output DIsable VSS Schmit Trigger Figure 1-4. Pin Circuit Type 2 1-6 S3C7031/7032 PRODUCT OVERVIEW VDD Pull-up Registor Typical 50 KΩ (VDD =5V) Pull-up Enable VDD Data Open-drain I/O Output Disable VSS Schmit Trigger Figure 1-5. Pin Circuit Type 3 1-7 PRODUCT OVERVIEW S3C7031/7032 VDD Pull-up Registor Pull-up Enable Typical 50 KΩ (VDD =5V) P-CH VDD Data Open-drain I/O Output Disable VSS Schmit Trigger (Digital) In Intk (Quasi) REF (P1.3 Only) + In (Analog) Comparator REF Digital or Analog Selectable by Software Figure 1-6. Pin Circuit Type 4 1-8 S3C7031/7032 14 ELECTRICAL DATA ELECTRICAL DATA OVERVIEW In this section, information on S3C7031/7032 electrical characteristics is presented as tables and graphics. The information is arranged in the following order: Standard Electrical Characteristics — Absolute maximum ratings — D.C. electrical characteristics — Oscillators characteristics — I/O capacitance — Comparator electrical characteristics — A.C. electrical characteristics — Operating voltage range Oscillation Characteristics — System clock oscillator frequencies and stabilization time Stop Mode Characteristics and Timing Waveforms — RAM data retention supply voltage in stop mode — Stop mode release timing when initiated by RESET — Stop mode release timing when initiated by an interrupt request 14-1 ELECTRICAL DATA Miscellaneous Timing Waveforms — Clock timing measurement at XIN — TIO timing — Input timing for RESET — Input timing for external interrupts and quasi-interrupts — Serial data transfer timing Characteristic Curves — IDD vs Frequency — IDD vs VDD — IOL vs VOL (P0.0) — IOL vs VOL (P1.1) — IOL vs VOL (P2.0) — IOH vs VOH (P0.0) — IOH vs VOH (P1.1) 14-2 S3C7031/7032 S3C7031/7032 ELECTRICAL DATA Table 14-1. Absolute Maximum Ratings (TA = 25 °C) Parameter Supply Voltage Symbol Conditions Rating Units VDD – - 0.3 to + 7.0 V - 0.3 to VDD + 0.3 V - 0.3 to VDD + 0.3 V One I/O port active -5 mA All I/O ports active - 15 One I/O port active 25 All I/O port, total 100 Input Voltage VI Output Voltage VO Output Current High I OH Output Current Low All I/O ports I OL – mA Operating Temperature TA – - 40 to + 85 °C Storage Temperature Tstg – - 65 to + 150 °C Table 14-2. D.C. Electrical Characteristics (TA = - 40 °C to + 85 °C, VDD = 2.7 V to 6.0 V) Parameter Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Symbol Conditions Min Typ Max Units V VIH1 Ports 0, 1, 2, 3, RESET 0.7 VDD – VDD VIH2 XIN, XOUT VDD - 0.5 – VDD VIL1 Ports 0, 1, 2, 3, RESET – – 0.3 VDD VIL2 XIN, XOUT VOH1 VDD = 4.5 V to 6.0 V IOH = - 3 mA Ports 0, 1, 2, 3 except P0.0 VDD - 1.0 VDD - 0.4 – VDD = 4.5 V to 6.0 V IOH = - 6 mA Ports 0, 1, 2, 3 except P0.0 VDD - 2.0 VDD - 0.9 – VOH2 VDD = 4.5 V to 6.0 V IOH = - 10 mA P0.0 VDD - 2.0 – – VOL1 VDD = 4.5 V to 6.0 V IOL = 25 mA Ports 0, 1, 2, 3 except P0.0 – 1.4 2.0 V VOL2 VDD = 4.5 V to 6.0 V IOL = 50 mA P0.0 – 1.6 2.0 V V 0.4 V 14-3 ELECTRICAL DATA S3C7031/7032 Table 14-2. D.C. Electrical Characteristics (Continued) (TA = - 40 °C to + 85 °C, VDD = 2.7 V to 6.0 V) Parameter Input High Leakage Current Input Low Leakage Current Output High Leakage Current Output Low Leakage Current Pull- Up Resistor Supply Current (2) Symbol Conditions Min Typ Max Units – – 3 µA 15 20 – -3 -15 - 20 ILIH1 VIN = VDD All input pins except ILIH2 ILIH2 VIN = VDD XIN, XOUT ILIL1 VIN = 0 V All input pins except ILIL2 ILIL2 VIN = 0 V XIN, XOUT ILOH VO = VDD All output pins – – 3 µA ILOL VO = 0 V All output pins – – -3 µA VIN = 0 V; VDD = 5 V - 10 % Ports 0, 1, 2, 3 VIN = 0 V; VDD = 3 V - 10 % Ports 0, 1, 2, 3 15 50 80 KΩ 30 100 200 VDD = 5 V ± 10 % (2) 4.19 MHz crystal oscillator C1 = C2 = 22 pF – 1.7 8.0 0.6 1.2 0.5 1.8 0.2 1.0 0.2 5 0.1 3 RL IDD1 IDD2 IDD3 VDD = 3 V ± 10 % (3) 4.19 MHz crystal oscillator C1 = C2 = 22 pF Idle mode; VDD = 5 V ± 10 % 4.19 MHz crystal oscillator C1 = C2 = 22 pF Idle mode; VDD = 3 V ± 10 % 4.19 MHz crystal oscillator C1 = C2 = 22 pF Stop mode VDD = 5 V - 10 % Stop mode VDD = 3 V - 10 % – – µA mA mA µA NOTES: 1. D.C. electrical values for Supply Current (IDD1 to IDD3) do not include current drawn through internal pull-up resistors. 2. 3. For high-speed controller operation, set the PCON register to 0011B. For low-speed controller operation, set the PCON register to 0000B. 14-4 S3C7031/7032 ELECTRICAL DATA Table 14-3. Oscillators Characteristics (TA = - 40 °C to + 85 °C, VDD = 5 V) Oscillator Ceramic Oscillator Clock Configuration XIN XOUT C1 Parameter Test Condition Min Typ Max Units Oscillation frequency(1) – 0.4 – 4.5 MHz After VDD reaches the minimum level of its variable range – – 4 ms – 0.4 4.19 4.5 MHz VDD = 2.7 V to 4.5 V – – 30 ms VDD = 4.5 V to 6.0 V – – 10 XIN input frequency (1) – 0.4 – 4.5 MHz XIN input high and low level width (tXH, tXL) – 111 – 1250 ns VDD = 5 V 0.6 1 2.3 MHz VDD = 3 V 0.4 0.8 1.5 C2 Stabilization time (2) Crystal Oscillator Oscillation frequency(1) XIN XOUT C1 C2 Stabilization time (2) External Clock RC Oscillator XIN XOUT Frequency XIN XOUT R NOTES: 1. Oscillation frequency and XIN input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is terminated. 14-5 ELECTRICAL DATA S3C7031/7032 Table 14-4. Input/Output Capacitance (TA = 25 °C, VDD = 0 V ) Parameter Symbol Condition Min Typ Max Units Input Capacitance CIN f = 1 MHz; Unmeasured pins are returned to VSS – – 15 pF Output Capacitance COUT – – 15 pF CIO – – 15 pF I/O Capacitance Table 14-5. Comparator Electrical Characteristics (TA = - 40 °C to + 85 °C, VDD = 4.0 V to 6.0 V) Parameter Symbol Condition Min Typ Max Units – – 0 – VDD V Reference Voltage Range VREF – 0 – VDD V Input Voltage Accuracy Internal Reference VCIN1 – – – - 150 mV External Reference VCIN2 – – – - 50 ICIN, IREF – -3 – 3 Input Voltage Range Input Leakage Current 14-6 µA S3C7031/7032 ELECTRICAL DATA Table 14-6. A.C. Electrical Characteristics (TA = - 40 °C to + 85 °C, VDD = 2.7 V to 6.0 V) Parameter Symbol Instruction Cycle Time tCY TIO Input Frequency f TI Conditions Min Typ Max Units VDD = 4.5 V to 6.0 V 0.95 – 64 µs VDD = 2.7 V to 4.5 V 3.8 VDD = 4.5 V to 6.0 V 0 – 1 MHz 275 kHz – – µs – – ns – – ns – – ns – – ns – 300 ns VDD = 2.7 V to 4.5 V TIO Input High, Low Width SCK Cycle Time SCK High, Low Width tTIH, tTIL tKCY tKH, tKL VDD = 4.5 V to 6.0 V 0.48 VDD = 2.7 V to 4.5 V 1.8 VDD = 4.5 V to 6.0 V; Input 800 VDD = 4.5 V to 6.0 V; Output 950 VDD = 2.7 V to 4.5 V; Input 3200 VDD = 2.7 V to 4.5 V; Output 3800 VDD = 4.5 V to 6.0 V; Input 400 VDD = 4.5 V to 6.0 V; Output tKCY/2-50 VDD = 2.7 V to 4.5 V; Input 1600 VDD = 2.7 V to 4.5 V; Output tKCY/2-50 SI Setup Time to SCK High SI Hold Time to SCK High Output Delay for SCK to SO Interrupt Input High, Low Width RESET Input Low Width tSIK tKSI tKSO tINTH, tINTL tRSL Input 100 Output 150 Input 400 Output 400 VDD = 4.5 V to 6.0 V; Input – VDD = 4.5 V to 6.0 V; Output 250 VDD = 2.7 V to 4.5 V; Input 1000 VDD = 2.7 V to 4.5 V; Output 1000 INT1, KS0-KS3 10 – – µs Input 10 – – µs 14-7 ELECTRICAL DATA S3C7031/7032 CPU Clock 1.0475MHz 1.00MHz 750kHz 500kHz 250kHz 15.6kHz 1 2 3 4 5 6 7 Supply Voltage (V) CPU Clock = 1/n x oscillator frequency (n =4, 8 or 64) Figure 14-1. Standard Operating Voltage Range Table 14-7. RAM Data Retention Supply Voltage in Stop Mode (TA = - 40 °C to + 85 °C) Parameter Symbol Condition Min Typ Max Units Data Retention Supply voltage VDDDR – 2.0 — 6.0 V Data Retention Supply Current IDDDR – 0.1 10 µA Release Signal Set Time tSREL 0 — – µs Oscillation Stabilization Wait Time (1) tWAIT Released by RESET – 217 / fx – ms Released by interrupt – (2) – VDDDR = 2.0 V – NOTES: 1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator start-up. 2. Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time. 14-8 S3C7031/7032 ELECTRICAL DATA TIMING WAVEFORMS Internal RESET Operation ~ ~ Stop Mode Idle Mode Operating Mode Data Retention Mode ~ ~ VDD VDDDR Execution Of Stop Instrction RESET tSREL tWAIT Figure 14-2.Stop Mode Release Timing When Initiated By RESET Idle Mode ~ ~ ~ ~ VDD Execution Of Stop Instrction Stop Mode Normal Mode Data Retention Mode VDDDR Power - Down Mode Terminating Signal (Interrupt Request) tSREL tWAIT Figure 14-3. Stop Mode Release Timing When Initiated By Interrupt Request 14-9 ELECTRICAL DATA S3C7031/7032 0.7 VDD 0.7 VDD Measurement Points 0.3 VDD 0.3 VDD Figure 14-4. A.C. Timing Measure Points (Except for XIN) 1/fx tXL tXH VDD - 0.5V XIN 0.4 V Figure 14-5. Clock Timing Measurement at XIN 1/fTCL tTIL tTIH 0.7 VDD TIO 0.3 VDD Figure 14-6. TIO Timing 14-10 S3C7031/7032 ELECTRICAL DATA tRSL RESET 0.3 VDD Figure 14-7. Input Timing for RESET Signal tINTL INT1 KS0 to KS3 tINTH 0.7 VDD 0.3 VDD Figure 14-8. Input Timing for External Interrupts 14-11 ELECTRICAL DATA S3C7031/7032 tKCY tKL tKH SCK 0.7 VDD 0.3 VDD tKSO tKIS 0.7 VDD SI Input Data 0.3 VDD tKSO SO Output Data Figure 14-9. Serial Data Transfer Timing 14-12 S3C7031/7032 ELECTRICAL DATA CHARACTERISTIC CURVES NOTE The characteristic values shown in the following graphs are based on actual test measurements. They do not, however, represent guaranteed operating values. 70 63 54 VDD = 6.0V IOL (mA) 49 42 35 VDD = 4.5V 28 21 14 7 0.0 0.6 1.2 1.8 2.4 3.0 3.6 4.2 4.8 5.4 6.0 VOL (V) Figure 14-10. IOL vs. VOL (Port 0,1,2,3) 14-13 ELECTRICAL DATA S3C7031/7032 100 VDD = 6.0V 90 80 IOL (mA) 70 VDD = 4.5V 60 50 40 30 20 10 0.0 0.6 1.2 1.8 2.4 3.0 3.6 4.2 4.8 5.4 6.0 4.8 5.4 6.0 VOL (V) Figure 14-11. IOL vs. VOL (Port 0.0) -30.0 -27.0 -24.0 IOL (mA) -21.0 VDD = 6.0V -18.0 -15.0 VDD = 4.5V -12.0 -9.0 -6.0 -3.0 0.0 0.6 1.2 1.8 2.4 3.0 3.6 4.2 VOL (V) Figure 14-12. IOH vs. VOH (Port 0,1,2,3except P0.0) 14-14 S3C7031/7032 ELECTRICAL DATA 3.0 2.5 IDD (mA) 2 IDD1 (/4) 1.5 1 IDD2 0.5 ~ ~ 0 0 3.0 4.0 5.0 6.0 VDD (V) Figure 14-13. IDD vs. VDD 2.5 IDD1(mA) 2 VDD = 5.5V(/4) 1.5 1 0.5 0 0 1.0 2.0 3.0 4.0 5.0 fx (MHz) Figure 14-14. IDD vs. Frequency 14-15 S3C7031/7032 MECHANICAL DATA 15 MECHANICAL DATA This section contains the following information about the device package: — A 20-pin DIP package is available for S3C7031/7032. — A 20-pin SOP package is available for S3C7031/7032. 6.40 ± 0.20 #20 20-DIP-300A #10 2.54 5.08 MAX 1.52 ± 0.10 3.30 ± 0.30 ± 0.20 3.52 ± 0.20 26.40 (1.77) 0-15 0.51 MIN #1 0.46 ± 0.10 7.62 #11 0.25 +- 0.10 0.05 NOTE: Dimensions are in millimeters Figure 15-1. 20-pin DIP-300A Package Dimensions 15-1 MECHANICAL DATA S3C7031/7032 #20 #11 10.30 ± 0.30 7.50 ± 0.20 20-SOP-375 0.203 + 0.10 - 0.05 9.53 #10 2.30 ± 0.10 #1 12.74 ± 0.20 (0.66) 0.85 ± 0.20 0.40 +- 0.10 0.05 1.27 0.05 MIN 2.50 MAX NOTE: Dimensions are in millimeters Figure 15-2. 20-pin SOP-375 Package Dimensions 15-2 0-8