CXD1176Q 8-bit 20MSPS Video A/D Converter with Clamp Function Description The CXD1176Q is an 8-bit CMOS A/D converter for video use that features a sync clamp function. The adoption of a 2 step-parallel method realizes low power consumption and a maximum conversion speed of 20MSPS. Features • Resolution power: 8-bit ± 1/2LSB (DL) • Maximum sampling frequency: 20MSPS • Low power consumption: 60mW (at 20MSPS typ.) (Reference current excluded) • Built-in sync type clamp function • Built-in monostable multivibrator for clamp pulse • • • • • • • • • generation Built-in sync pulse polarity selection function Clamp pulse direct input possible Built-in clamp ON/OFF function Built-in reference voltage self-bias circuit Input CMOS compatible 3-state TTL compatible output Single 5 V power supply Low input capacity: 11 pF Reference impedance: 330 Ω (typ.) Absolute Maximum Ratings (Ta=25 °C) • Supply voltage VDD 7 • Reference voltage VRT, VRB VDD + 0.5 to VSS – 0.5 • Input voltage VIN VDD + 0.5 to VSS – 0.5 (Analog) • Input voltage VI VDD + 0.5 to VSS – 0.5 (Digital) • Output voltage VO (Digital) • Storage temperature Tstg Applications TV and VCR digital systems and a wide range of applications where high-speed A/D conversion is required. Structure Silicon gate CMOS IC 32 pin QFP (Plastic) V V V V VDD + 0.5 to VSS – 0.5 V –55 to +150 °C Recommended Operating Conditions • Supply voltage AVDD, AVSS 4.75 to 5.25 V DVDD, DVSS | DVSS – AVSS | 0 to 100 mV • Reference input voltage VRB 0 to V VRT to 2.7 V • Analog input VIN 1.8Vp-p above • Clock pulse width Tpw1, Tpw0 22.5 ns (min) to 1.1 µs (max) • Operating ambient temperature Topr –40 to +85 °C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. —1— E90167J04-TE CXD1176Q Block Diagram and Pin Configuration DVss 28 OE 30 Reference supply 25 VRBS DVss 31 24 VRB D0 (LSB) 1 23 AVss D1 D2 2 3 Lower data latch Lower encoder (4 BIT) Lower sampling comparator (4 BIT) 22 AVss 21 VIN D3 D4 4 Lower encoder (4 BIT) 5 20 AVDD Lower sampling comparator (4 BIT) 19 AVDD D5 6 D6 7 D7 (MSB) 8 Upper data latch Upper encoder (4 BIT) 18 VRT Upper sampling comparator (4 BIT) 17 VRTS 16 AVDD DVDD 10 DVDD 11 CLK 12 NC Clock generator 9 15 PW 14 Sync NC 32 M·M 29 27 26 CLE CCP VREF —2— 13 SEL CXD1176Q Pin Description Pin No. Symbol Equivalent circuit 1 to 8 D0 to D7 D0 (LSB) to D7 (MSB) output 9, 32 NC NC pin 10, 11 DVDD Digital +5 V Di Description DVDD 12 CLK Clock input 12 DVSS DVDD 13 SEL 13 DVSS When SEL is at low, with the falling edge of Pin 14 (sync) as trigger, the monostable multivibrator generates clamp pulses. When SEL is at high, with the rising edge of Pin 14 (sync) as trigger, it generates clamp pulses. DVDD 14 Sync Trigger pulse input to the monostable multivibrator. Trigger polarity can be selected through Pin 13 (SEL). 14 DVSS —3— CXD1176Q Pin No. Symbol Equivalent circuit Description DVDD 15 PW When a clamp pulse is generated at the monostable multivibrator, the pulse width is determined by the external R and C. When the clamp pulse is directly input, it is input to Pin 15 (PW). The signal voltage of the low period is clamped. (Here, Pin 14 (sync) is fixed to either low or high.) 15 DVSS 16, 19, 20 AVDD Analog +5 V AVDD 17 When shorted with VRT, generates approx. +2.6 V. VRTS 17 18 AVDD VRT Reference voltage (top) 18 24 24 VRB Reference voltage (bottom) AVSS AVDD 21 VIN Analog input 21 AVSS 22, 23 Analog ground AVSS AVSS 25 When shorted with VRB, generates approx. +0.5 V. VRBS 25 —4— CXD1176Q Pin No. Symbol Equivalent circuit Description AVDD 26 Clamp reference voltage input. Clamps to provide a clamp period input signal equal to the reference voltage. 26 VREF AVSS AVDD 27 Integrates the voltage for clamp control. CCP and VIN voltage changes are in positive phase. 27 CCP AVSS 28, 31 Digital ground. DVSS DVDD 29 CLE 29 CLAMP PULSE DVSS When CLE is at low, clamp function is activated. When CLE is at high, clamp function is OFF and only the usual A/D converter function is active. By connecting CLE pin to DVDD via a several hundred Ω resistance, the clamp pulse can be tested. DVDD 30 OE When OE is at low, Data is output. When OE ia at high, D0 to D7 pins turn to high impedance. 30 DVSS —5— CXD1176Q Digital Output Correspondence between the analog input voltage and the digital output code is indicated in the chart below. TPW1 Input signal voltage Step Digital output code MSB LSB V.RT .. .. .. .. .. . VRB 0. .. 127 128 .. . 255 1 1 1 1.1 .. 1 0 0 0 0 0 1 1 1.1 .. 0 0 0 0 0 1 1 1 0 0 0 1 1 1 0 0 0 TPW0 Clock Analog input N N+1 N–3 Data output N+2 N–2 N–1 N+3 N N+4 N+1 Td = 18ns : Points where analog signals are sampled. Timing Chart. I tr = 4.5ns tf = 4.5ns 5V 90% OE input 2.5V 10% tPZL tPLZ 0V VOH 1.3V Output 1 10% tPHZ VOL (≠ DVSS) tPZH VOH (≠ DVDD) 90% Output 2 1.3V VOL Timing Chart. II —6— CXD1176Q Electrical Characteristics Analog characteristics (Fc = 20 MSPS, VDD = 5 V, VRB = 0.5 V, VRT = 2.5 V, Ta = 25 °C) Item Symbol Conditions Min. 0.5 Typ. Max. Unit 20 MSPS Conversion speed Fc VDD = 4.75 to 5.25 V Ta = –40 to +85 °C VIN = 0.5 to 2.5 V fIN = 1 kHz ramp Analog input band width (–1dB) BW Envelope Offset voltage∗1 EOT Potential difference to VRT –60 –40 –20 EOB Potential difference to VRB +20 +40 +60 Integral non-linearity error EL +0.5 +1.3 ±0.3 ±0.5 MHz 18 End point Differential non-linearity error ED Differential gain error DG Differential phase error DP Aperture jitter Sampling delay taj tsd Clamp offset voltage∗2 Eoc VIN = DC, PWS = 3 µs Clamp pulse width (Sync pin input) tcpw C = 100 pF, R = 130 kΩ (15 PIN) Clamp pulse delay tcpd NTSC 40 IRE mod ramp Fc = 14.3 MSPS mV LSB 1.0 % 0.5 deg 30 ps 4 ns VREF = 0.5 V 0 +20 +40 VREF = 2.5 V –50 –30 –10 1.75 2.75 3.75 25 mV µs ns ∗1 The offset voltage EOB is a potential difference between VRB and a point of position where the voltage drops equivalent to 1/2 LSB of the voltage when the output data changes from “00000000” to “00000001”. EOT is a potential difference between VRT and a potential of point where the voltage rises equivalent to 1/2LSB of the voltage when the output data changes from “11111111” to “11111110”. ∗2 Clamp offset voltage varies individually. When using with R, G, B 3 channels, color sliding may be generated. —7— CXD1176Q (Fc = 20 MSPS, VDD = 5 V, VRB = 0.5 V, VRT = 2.5 V, Ta = 25 °C) DC characteristics Item Conditions Supply current IDD Reference pin current IREF Analog input capacitance CIN Reference resistance (VRT to VRB) RREF VRB1 Self-bias I VRT1 to VRB1 Self-bias II VRT2 Digital input voltage Digital input current VIH VIL IIH IOH Digital output current Fc = 20 MSPS NTSC ramp wave input 4.5 VRB and VRBS are shorted VRT and VRTS are shorted IOL IOZH IOZL Max. Unit 12 18 mA 6.6 8.7 mA pF 230 300 450 0.48 0.52 0.56 1.96 2.08 2.22 VRB = AGND VRT and VRTS are shorted VDD = 4.75 to 5.25 V Ta = –40 to +85 °C Typ. 11 VIN = 1.5 V + 0.07 Vrms VDD = max IIL Min. 4.0 1.0 VIH = VDD 5 VIL = 0V 5 VOL = 0.4V OE = VDD VDD = max V V 2.32 VOH = VDD – 0.5 V –1.1 OE = VSS VDD = min Ω V µA mA 3.7 VOH = VDD 16 VOL = 0V 16 µA (Fc = 20 MSPS, VDD = 4.75 to 5.25 V, VRB = 0.5 V, VRT = 2.5 V, Ta = –40 to +85 °C) Timing Item Symbol Conditions Min. Typ. Max. Unit 18 30 ns Output data delay TDL with TTL 1 gate and 10pF load Tri-state output enable time tPZH tPZL tPHZ tPLZ RL = 1kΩ, CL = 20 pF OE = 3 V → 0 V 2.5 6 10 ns RL = 1 kΩ, CL = 20 pF OE = 0 V → 3 V 8 18 30 ns Tri-state output disable time —8— CXD1176Q Electrical Characteristics Measurement Circuit Integral non-linearity error Differential non-linearity error Offset voltage } Tri-state output measurement circuit measurement circuit +V Measurement point DVDD S2 S1: ON IF A < B S2: ON IF B > A RL S1 To output pin –V VIN DUT CXD1176Q 8 “0” DVM A<B A>B COMPARATOR A8 B8 to to A1 B1 A0 B0 CL 8 BUFFER “1” 8 CLK (20MHz) CONTROLLER Maximum operational speed Differential gain error Differential phase error } 000 · · · 00 to 111 · · · 10 Note) CL includes capacitance of the probe and others. measurement circuit 2.5V ERROR RATE Fc – 1kHz CX20202A-1 S.G. COUNTER H.P.F 0.5V 1 VIN CXD 1176Q AMP 100 NTSC TTL 8 ECL 1 10bit D/A 2 620 2.5V –5.2V BURST IAE SIGNAL SOURCE 8 2 40 IRE MODULATION VECTOR SCOPE CLK 0 0.5V –40 S.G. (CW) SYNC 620 D.G D.P. TTL FC –5.2V ECL Digital output current measurement circuit 2.5V 0.5V VDD VRT VIN VRB CLK OE GND RL 2.5V IOL 0.5V VOL VDD VRT VIN VRB CLK OE GND + – —9— IOH VOH + – CXD1176Q Vi (1) Vi (2) Vi (3) Vi (4) Analog input External clock Upper comparators block S (1) Digital output S (3) H (1) C (3) C (1) C (0) RV (3) S (3) H (3) C (3) LD (1) S (2) LD (–2) H (2) C (2) LD (0) Out (–2) C (4) MD (3) RV (2) LD (–1) H (0) S (4) MD (2) RV (1) S (1) Lower data A Lower data B C (2) MD (1) RV (0) Lower reference voltage Lower comparators B block S (2) MD (0) Upper data Lower comparators A block C (1) Out (–1) S (4) H (4) LD (2) Out (0) Out (1) Timing Chart 3 Operation (See Block Diagram and Timing Chart 3) 1. The CXD1176Q is a 2-step parallel system A/D converter featuring a 4-bit upper comparators group and 2 lower comparators groups of 4-bit each. The reference voltage that is equal to the voltage between VRT – VRB/16 is constantly applied to the upper 4-bit comparator block. Voltage that corresponded to the upper data is fed through the reference supply to the lower data. VRTS and VRBS pins serve for the self generation of VRT (Reference voltage top) and VRB (Reference voltage bottom). —10— CXD1176Q 2. This IC uses an offset cancel type comparator and operates synchronously with an external clock. It features the following operating modes which are respectively indicated on the timing chart with S, H, C symbols. That is input sampling (auto zero) mode, input hold mode and comparison mode. 3. The operation of respective parts is as indicated in the chart. For instance input voltage Vi (1) is sampled with the falling edge of the first clock by means of the upper comparator block and the lower comparator A block. The upper comparators block finalizes comparison data MD (1) with the rising edge of the first clock. Simultaneously the reference supply generates the lower reference voltage RV (1) that corresponded to the upper results. The lower comparator block finalizes comparison data LD (1) with the rising edge of the second clock. MD (1) and LD (1) are combined and output as Out (1) with the rising edge of the 3rd clock. Accordingly there is a 2.5 clock delay from the analog input sampling point to the digital data output. Operation Notes 1. VDD, VSS To reduce noise effects, separate the analog and digital systems close to the device. For both the digital and analog VDD pins, use a ceramic capacitor of about 0.1 µF set as close as possible to the pin to bypass to the respective GND’s. 2. Analog input Compared with the flash type A/D converter, the input capacitance of the analog input is rather small. However it is necessary to conduct the drive with an amplifier featuring sufficient band and drive capability. When driving with an amplifier of low output impedance, parasite oscillation may occur. That may be prevented by inserting a resistance of about 100 Ω in series between the amplifier output and A/D input. 3. Clock input The clock line wiring should be as short as possible also, to avoid any interference with other signals, separate it from other circuits. 4. Reference input Voltage between VRT to VRB is compatible with the dynamic range of the analog input. Bypassing VRT and VRB pins to GND, by means of a capacitor about 0.1 µF, stable characteristics are obtained. By shorting VRT and VRTS, VRB and VRBS, the self-bias function that generates VRT = 2.6 V and VRB = 0.6 V, is activated. 5. Timing Analog input is sampled with the falling edge of CLK and output as digital data with a delay of 2.5 clocks and with the following rising edge. The delay from the clock rising edge to the data output is about 18 ns. 6. OE pin By connecting OE to GND output mode is obtained. By connecting to VDD high impedance is obtained. 7. About latch up It is necessary that AVDD and DVDD pins be the common source of power supply. This is to avoid latch up due to the voltage difference between AVDD and DVDD pins when power is ON. —11— CXD1176Q Application Circuit (1) Case where clamp pulse is directly input (self-bias used) +5V (Digital) HCO4 0.1µ CLOCK IN CLAMP PULSE IN ∗ LATCH CK Q 0.01µ +5V (Analog) VIDEO IN 10µ 15 16 75Ω 0.1µ 10P 0.01µ 13 14 12 10 11 9 17 8 D7 18 7 D6 19 6 D5 20 5 D4 21 4 D3 22 3 D2 23 2 D1 24 1 D0 +5V (Analog) 26 25 27 VREF 20k 28 29 30 31 32 0.01µ GND (Digital) GND (Analog) (2) Example where pedestal clamp is executed by sync pulse (self-bias used) +5V (Digital) HCO4 0.1µ CLOCK IN SYNC IN ∗ LATCH CKQ 16 0.01µ +5V (Analog) VIDEO IN 10µ 75Ω 0.1µ 10P 0.01µ +5V (Analog) 15 14 13 12 10 11 9 17 8 D7 18 7 D6 19 6 D5 20 5 D4 21 4 D3 22 3 D2 23 2 D1 24 1 D0 25 26 27 VREF 28 29 30 31 32 0.01µ 20k GND (Digital) GND (Analog) ∗ The clamp pulse is latched by the ADC sampling clock, but that is not necessary for clamp basic operation. However, slight beat may be generated as vertical sag according to the relation between the sampling frequency and clamp pulse frequency. At such time, the latch circuit is effective. (See page 20 Notes on Operation 5.) —12— CXD1176Q (3) Digital clamp (self-bias used) +5V (Digital) HCO4 0.1µ CLOCK IN CLAMP PULSE IN 15 16 0.01µ +5V (Analog) VIDEO IN 10µ 75Ω 14 13 12 10 11 9 OPEN 17 8 18 7 19 6 20 5 21 4 22 3 23 2 24 1 0.1µ 10P 0.01µ 25 26 27 28 29 30 31 Latch, Subtracter, Comparator, etc. Clamp Level setting data 32 DAC, PWM, etc. GND (Digital) GND (Analog) (4) When clamp is not used (self-bias used) +5V (Digital) HCO4 0.1µ CLOCK IN 16 0.01µ +5V (Analog) VIDEO IN 75Ω 15 14 13 12 10 11 9 17 8 D7 18 7 D6 19 6 D5 20 5 D4 21 4 D3 22 3 D2 23 2 D1 24 1 D0 0.1µ 10P 0.01µ 25 26 27 28 29 30 +5V (Digital) GND (Analog) —13— 31 32 GND (Digital) CXD1176Q 8-bit 20MSPS ADC and DAC Evaluation Board Evaluation boards are available for the high speed, low power consumption CMOS converters, CXD1176Q (8bit 20MHz A/D) and CXD1171M (8-bit 40MHz D/A). The evaluation board is composed of a main board common to either type, to which is added sub board CXD1176Q or sub board CXD1171M. The junction is made through a socket. To the main board are mounted an input interface, clock buffer and latch. To each of the sub boards is mounted CXD1176Q and CXD1171M respectively. Those IC’s are mounted according to recommended print patterns designed to provide maximum performance to the A/D and D/A converters. Block Diagram ANALOG CIRCUIT MOUNT PORTION 8 ADC SOCKET V REF VIN ANALOG INPUT INTERFACE DIGITAL CIRCUIT MOUNT PORTION DATA LATCH DAC SOCKET VOUT 8 4 CLOCK BUFFER OSC ANALOG CIRCUIT MOUNT PORTION SW GND +5V –5V CLOCK OE SEL SYNC CLE Unnecessary at self-bias use Characteristics • Resolution • Maximum conversion rate • Digital input level • Supply voltage 8 bit 20 MHz CMOS level ±5.0 V (Single +5 V power supply possible at self bias use) Supply voltage Item Min. Typ. Max. Unit 150 20 mA +5 V –5 V Clock input CMOS compatible Pulse width TCW1 TCW0 22.5 ns (min) 22.5 ns (min) —14— BLK CXD1176Q Analog Output (CXD1171M) Item Analog output (RL > 10 kΩ) Min. Typ. Max. Unit 1.9 2.0 2.1 V Output Format (CXD1176Q) The table shows the output format of AD Converter. Analog input voltage Step V.RT .. .. .. .. .. . VRB 0. .. 127 128 .. . 255 Digital output code MSB LSB 1 1 1 1.1 .. 1 0 0 0 0 0 1 1 1.1 .. 0 0 0 0 0 1 1 1 0 0 0 1 1 1 0 0 0 Timing Chart Analog input External clock Tpw0 Tpw1 Tdc AD clock tPD (AD) AD output tDD Latch output DA input ts th DA clock DA output Item Symbol tPD (DA) Min. Typ. Max. Unit Clock High time TPW1 25 ns Clock Low time TPW0 25 ns Clock Delay Tdc Data delay AD tPD (AD) tDD tS th tPD (DA) Data delay (latch) Set up time Hold time Data delay DA 18 24 ns 30 ns 5 ns 5 ns 10 ns 10 —15— ns R1 100k C1 470µ VIDEO INPUT VR1 2k Q3 R6 510 R4 510 VRB ADJUST VR2 2k Q1 R2 75 Q2 CLAMP VOLTAGE ADJUST AVSS C2 R3 10µ 33 AVDD AVSS R5 510 AVDD VRT ADJUST 47µ VR3 20k C5 0.1 OUTPUT GAIN ADJUST VR4 20k 47µ SW3 C4 0.01 C3 0.01 SW2 V out (R) R7 200 (16R) R8 3.3k –5V +5V GND AVDD DVDD —16— D4 5 D3 4 20 AVDD 21 IO D1 4 25 VRBS 0.01 OE 1 D2 5 24 AVSS 28 CLE D3 6 23 AVSS D0 3 D4 7 22 VIN DVSS 2 D5 8 21 AVDD 27 VREF D6 9 20 AVDD 26 VRB D7 10 DVDD 11 18 VRT 19 VRTS SEL 13 CLK 12 16 NC 17 NC 15 PW SYNC 14 D0 1 24 DVDD SW1 D1 2 23 NC D2 3 D5 6 22 IO D6 7 19 AVDD 16 AVSS 18 VREF BLK 9 15 AVSS D7 8 CLK 10 14 NC 17 IREF NC 12 DVSS 11 13 NC DVDD DVDD DVSS DVSS DVDD DVDD CLK DVDD CLK 14 13 12 11 10 9 8 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 0.01µ 74S174 (LATCH) 0.01µ 74S174 (LATCH) 0.01µ 74S04 OR 74HC04 (INV BUFFER) CMOS ADC/DAC Peripheral Circuit Board (Main Board) 1 2 3 4 5 6 7 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 DVSS CLEAR DVSS CLEAR DVSS OE SEL CLE BLK SYNC OSC SWITCH EXT/INT OSC out 0.01µ R9 75 VR5 20k 47µ R10 75 SYNC INT (RIN = 75Ω) EXTERNAL CLOCK INPUT 1 8 7 DVSS 14 DVDD CXD1176Q CXD1176Q CMOS ADC/DAC Peripheral Circuit Board (Sub Board) PW 15 14 SYNC 13 SEL NC 16 16 15 NC 17 14 13 12 11 10 9 12 CLK VRTS 18 17 8 11 VRT 19 18 7 10 D7 AVDD 20 19 6 9 D6 5 8 D5 21 4 7 D4 22 3 6 D3 AVSS 24 23 2 5 D2 VRB 25 24 1 4 D1 3 D0 2 DVSS 1 OE C3 0.1µ AVDD 21 VIN 22 AVSS 23 C5 20 DVDD CXD1176Q VRBS 26 25 26 27 28 29 30 31 32 C2 0.1µ VREF 27 CLE 28 C1 0.01µ NC 13 13 12 NC 14 14 11 AVSS 15 15 10 10 CLK AVSS 16 16 9 9 BLK 17 8 8 D7 7 7 D6 IREF 17 VREF 18 C3 C2 18 12 NC C4 11 DVSS CXD1171M AVDD 19 19 6 6 D5 AVDD 20 20 5 5 D4 IO 21 21 4 4 D3 IO 22 22 3 3 D2 NC 23 23 2 2 D1 DVDD 24 24 1 1 D0 C1 —17— CXD1176Q List of Parts resistance R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 VR1 VR2 VR3 VR4 VR5 100 kΩ 75 Ω 75 Ω 510 Ω 510 Ω 510 Ω R = 200 Ω 18R ≈ 3.3 kΩ 75 Ω 75 Ω 2 kΩ 2 kΩ 20 kΩ 20 kΩ 20 kΩ transistor Q1 2SC2785 Q2 2SC2785 Q3 2SC2785 IC IC1 IC2 IC3 74S174 74S174 74S04 oscillator OSC others connector BNC071 SW AT1D2M3 capacitance C1 470 µF/6.3 V (chemical) C2 10 µF/16 V (chemical) C3 0.01 µF C4 0.01 µF C5 0.1 µF C6 0.1 µF C7 0.1 µF C8 0.1 µF C9 0.1 µF C10 0.1 µF C11 47 µF/10 V (chemical) C12 47 µF/10 V (chemical) C13 47 µF/10 V (chemical) C14 0.1 µF Adjustment 1. Vref adjustment (VR1, VR2) Adjustment of A/D converter reference voltage. VRB is adjusted through VR1 and VRT through VR2. When self-bias is used, there is no need for adjustment. Reference voltage is set through self-bias delivery. 2. Setting of clamp reference voltage (VR3) Clamp reference voltage is set. 3. DAC output full-scale adjustment (VR4) Full-scale voltage of D/A converter output is adjusted at the PCB shipment, the full-scale voltage is adjusted to approx. 2 V. 4. Sync (clamp) pulse interface (VR5) This adjustment enables interface with the signal generator and others at the PCB shipment, adjustment is performed to obtain a threshold of approx. 2.5 V to an H sync of 0 to 5 V. —18— CXD1176Q 5. OE, SEL, Sync, BLK, CLE, Sync INT The following pins are set on the main board: OE, SEL, Sync, CLE, Sync INT (CXD1176Q) and BLK (CXD1171M). For the pins function, refer to the specifications. The difference between Sync pin and Sync INT pin is that you input a horizontal synchronizing signal above 3.5 Vp-p Sync INT pin. The pulse threshold is set through VR5. For input through Sync pin, pulse is input at TTL or CMOS level. In this case cut off the junction line between Sync and Sync INT pin. At the PCB shipment the main board pins are set as follows. • OE ... Low (A/D output ON) • SEL ... Low (Pulse generated with Sync falling edge as trigger) • Sync ... Line junction with Sync INT pin • CLE ... Low (Clamp function ON) • BLK ... Low (Blanking OFF) 6. Clamp pulse input method One method, as shown in Application Circuit examples (1) and (2), is to directly input the clamp pulse. The other is to use the built-in monostable multivibrator. The method is selected through SW1. At the PCB shipment it is set to direct input. To use the built-in monostable multivibrator, it is necessary to mount on the CXD1176Q sub board, R and C that determine pulse width. (Ex. R = 130 k, C = 100 p, Tpw = 2.75 µs Typ.) Points on the PCB Pattern Layout 1. Set the layout not to have Digital current flow into Analog GND (Part 1). (For 1, See p. 23 Component side diagram.) 2. At CXD1176Q sub board, C2 and C3 capacitors serve the important role of bringing out CXD1176Q’s full performance. There are over 0.1 µF (ceramic) capacitors with good high frequency characteristics. Layout as close to the IC as possible. 3. Analog GND (AVSS) and Digital GND (DVSS) are on a common voltage and power source. Keeping ADC’s DVSS (Part 2) as close as possible to the voltage supply source will provide better results. That is, a layout where ADC is close to the voltage supply source, is recommended. (For 2, see p. 23 Component side diagram.) 4. ADC samples analog signals at the clock falling edge point. Accordingly clocks supplied to ADC should not have any jitter. 5. The PCB layout shows ADC and DAC’s Analog GND independently from the voltage generating source. On this PCB, the layout aims at providing an independent evaluation of ADC and DAC, as much as possible. On the actual board, common use will not cause any problems. —19— CXD1176Q Notes on Operation 1. Reference voltage Shorting VRT and VRTS, VRB and VRBS will activate the self-bias function that generates VRT = 2.6 V and VRB = 0.5 V. On the PCB, either self-bias or the external reference voltage can be selected depending on the junction method of the jumper line. At shipment from the factory, reference voltage is provided in selfbias. Also, to provide external reference voltage, adjust the dynamic range (VRT – VRB) to above 1.8 Vp-p. 2. Clock input There are 2 modes for the PCB clock input 1) Provided from the external signal generator. (External clock) 2) Using the crystal oscillator (built-in clock driver). (Internal clock) The 2 modes are selected using the switch on the PCB. 3. The 2 Latch IC’s (74S174) are not absolutely necessary for the evaluation of ADC and DAC. That is, operation will still be normal if ADC output data is directly input to DAC input. However, as ADC output data is hardly ever D/A converted without executing Digital signal processing, it was mounted to indicate an example layout of Digital signal processing IC. 4. When clamp is not used Turning CLE to H will set OFF the clamp function. In this case, the DC element is cut off by means of C2 on the main board and DC voltage on the ADC side of C2 turns to about 1/2 (VRT + VRB). To transfer DC elements of input signals, short C2. At that time, it is necessary to bias input signals, but keeping R2 open, Q3 can also be used as buffer. Use the open space for the bias circuit. 5. Clamp pulse latch On the evaluation board, the clamp pulse is latched with ADC sampling CLK and then input to either PW pin or Sync pin. This is to minimize Vsag due the synchronizing of noise and clamp pulse beat elements with GND sampling clock around ADC. If there are no problems with Vsag, latch is not necessary. 6. Peripheral through hole There is a group of through holes on the Analog input, output and Logic. There are to be used when mounting additional circuits to the PCB. Use when necessary. The connector hole on DAC part is used to mount the test chassis and the mount jack. —20— CXD1176Q Latch Up Prevention The CXD1176Q is a CMOS IC which requires latch up precautions. Latch up is mainly generated by the lag in the voltage rising time of AVDD (Pins 16, 19 and 20) and DVDD (Pin 10 and 11), when power supply is ON. 1. Correct usage a. When analog and digital supplies are from different sources DVDD AVDD 16 19 10 11 DVDD 20 AVDD C14 +5V +5V C6 DIGITAL IC CXD1176Q AVSS DVSS 22 23 28 31 AVSS DVSS b. When analog and digital supplies are from a common source (i) DVDD 16 19 10 11 DVDD 20 AVDD C14 +5V C6 DIGITAL IC CXD1176Q AVSS DVSS 22 23 28 31 AVSS DVSS (ii) DVDD 16 19 10 11 DVDD 20 AVDD C14 +5V DIGITAL IC CXD1176Q C6 AVSS 22 23 DVSS 28 31 AVSS DVSS —21— CXD1176Q 2. Example when latch up easily occurs a. When analog and digital supplies are from different sources DVDD AVDD 19 16 10 11 DVDD 20 AVDD +5V +5V CXD1176Q C6 DIGITAL IC AVSS DVSS 22 23 28 31 AVSS DVSS b. When analog and digital supplies are from a common source (i) DVDD AVDD 16 19 10 11 DVDD 20 AVDD +5V DIGITAL IC CXD1176Q C6 AVSS DVSS 22 23 28 31 AVSS DVSS (ii) DVDD AVDD 16 10 19 20 AVDD 11 DVDD +5V DIGITAL IC CXD1176Q AVSS 22 23 DVSS 28 31 AVSS DVSS —22— CXD1176Q Silk Side Component Side Soldering Side (Diagram seen from the component side) —23— CXD1176Q Package Outline Unit : mm 32PIN QFP (PLASTIC) 9.0 ± 0.2 24 0.1 + 0.35 1.5 – 0.15 + 0.3 7.0 – 0.1 17 16 32 9 (8.0) 25 1 + 0.2 0.1 – 0.1 0.8 + 0.15 0.3 – 0.1 0.24 M + 0.1 0.127 – 0.05 0° to 10° PACKAGE MATERIAL EPOXY RESIN SOLDER PLATING SONY CODE QFP-32P-L01 LEAD TREATMENT EIAJ CODE QFP032-P-0707 LEAD MATERIAL 42 ALLOY PACKAGE MASS 0.2g JEDEC CODE —24— 0.50 8 CXD1176Q Package Outline Unit : mm 32PIN QFP (PLASTIC) 9.0 ± 0.2 0.1 + 0.35 1.5 – 0.15 + 0.3 7.0 – 0.1 24 17 16 25 (8.0) A 9 32 1 M DETAIL A : SOLDER DETAIL A : PALLADIUM SONY CODE QFP-32P-L01 EIAJ CODE QFP032-P-0707 JEDEC CODE 0° to 10° b = 0.30 ± 0.03 0.125 ± 0.04 + 0.10 0.127 – 0.05 0.24 (0.127) ( 0.30) b 0.50 8 0.8 + 0.15 b = 0.30 – 0.10 + 0.2 0.1 – 0.1 PACKAGE MATERIAL EPOXY RESIN LEAD TREATMENT LEAD MATERIAL SOLDER / PALLADIUM PLATING 42 / COPPER ALLOY PACKAGE MASS 0.2g NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame). —25—