RFT1P06E
Data Sheet
August 1999
1.4A, 60V, 0.285 Ohm, ESD Rated,
P-Channel Power MOSFET
File Number
4495.1
Features
• 1.4A, 60V
These products are P-Channel power MOSFETs
manufactured using the MegaFET process. This process,
which uses feature sizes approaching those of LSI circuits,
gives optimum utilization of silicon, resulting in outstanding
performance. They were designed for use in applications
such as switching regulators, switching converters, motor
drivers, and relay drivers. These transistors can be operated
directly from integrated circuits.
• rDS(ON) = 0.285Ω
• 2kV ESD Protected
• Temperature Compensating PSPICE® Model
• SPICE Thermal Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
Formerly developmental type TA49044.
• 150oC Operating Temperature
Ordering Information
• Related Literature
- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”
PART NUMBER
RFT1P06E
PACKAGE
SOT-223
BRAND
R1P06E
Symbol
NOTE: RFT1P06E is available only in tape and reel.
D
G
S
Packaging
SOT-223
DRAIN
(FLANGE)
SOURCE
DRAIN
GATE
4-171
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
PSPICE® is a registered trademark of MicroSim Corporation.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999.
RFT1P06E
Absolute Maximum Ratings
TA = 25oC, Unless Otherwise Specified
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
Drain Current
Continuous (Figure 2) (Note 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg
RFT1P06E
-60
-60
±20V
UNITS
V
V
V
1.4
Figure 5
Figures 6, 14, 15
1.1
9.09
-55 to 150
A
W
mW/oC
oC
300
260
oC
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 125oC.
Electrical Specifications
TA = 25oC, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Drain to Source Breakdown Voltage
BVDSS
ID = 250µA, VGS = 0V (Figure 11)
-60
-
-
V
Gate to Source Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250µA (Figure 10)
-2
-
-4
V
Zero Gate Voltage Drain Current
IDSS
Gate to Source Leakage Current
Drain to Source On Resistance
IGSS
rDS(ON)
Turn-On Time
tON
Turn-On Delay Time
td(ON)
Rise Time
tr
Turn-Off Delay Time
VDS = -60V, VGS = 0V
-
-
-1
µA
VDS = -60V, VGS = 0V, TA = 150oC
-
-
-50
µA
VGS = ±10V
-
-
±100
nA
ID = 1.4A, VGS = -10V (Figure 9)
-
0.215
0.285
W
VDD = -30V, ID ≅ 1.4A,
RL = 21.4Ω, VGS = -10V,
RGS = 18Ω
-
-
51
ns
-
9
-
ns
-
25
-
ns
td(OFF)
-
35
-
ns
tf
-
28
-
ns
tOFF
-
-
95
ns
-
31
37
nC
-
17
20
nC
-
1.1
1.3
nC
VDS =-25V, VGS = 0V,
f = 1MHz
(Figure 12)
-
600
-
pF
-
175
-
pF
-
40
-
pF
Pad Area = 0.122in2 (Note 2)
-
-
110
oC/W
Pad Area = 0.071in2 (Note 2)
-
-
119
oC/W
Pad Area = 0.026in2 (Note 2)
-
-
137
oC/W
Fall Time
Turn-Off Time
Total Gate Charge
Qg(TOT)
VGS = 0V to -20V
Gate Charge at 10V
Qg(-10)
VGS = 0V to -10V
Threshold Gate Charge
Qg(TH)
VGS = 0V to -2V
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
Thermal Resistance Junction to Ambient
RθJA
VDD = -30V, ID ≅ 1.4A,
RL = 21.4Ω
IG(REF) = 1.0mA
(Figure 13)
NOTE:
2. 110oC/W measured using FR-4 board with 0.122in2 footprint at 1000 seconds (See Technical Brief 337).
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage
Reverse Recovery Time
Reverse Recovered Charge
4-172
SYMBOL
MIN
TYP
MAX
UNITS
ISD = -1.4A
-
-
-1.25
V
trr
ISD = -1.4A, dISD/dt = -100A/µs
-
-
71
ns
QRR
ISD = -1.4A, dISD/dt = -100A/µs
-
-
192
nC
VSD
TEST CONDITIONS
RFT1P06E
Typical Performance Curves
-1.5
RθJA = 110 oC/W
1.0
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
1.2
0.8
0.6
0.4
-1.125
-0.75
-0.375
0.2
-0
25
0
0
25
50
75
100
150
125
50
TA , AMBIENT TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT
TEMPERATURE
THERMAL IMPEDANCE
ZθJA, NORMALIZED
1
75
100
125
150
TA, AMBIENT TEMPERATURE (oC)
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
AMBIENT TEMPERATURE
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
RθJA = 110 oC/W
0.1
0.05
0.02
0.01
0.01
0.001
0.0001
PDM
t1
SINGLE PULSE
10-5
10-4
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
10-3
10-2
10-1
100
101
102
103
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
ID, DRAIN CURRENT (A)
TJ = MAX RATED
TA = 25oC
-10
100µs
1ms
-1
-0.1
10ms
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
-1
-30
TA = 25oC FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
IDM, PEAK CURRENT (A)
-100
I = I25
-10
150 - TA
125
VDSS(MAX) = -60V
-10
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
4-173
-100
-1
10-3
10-2
10-1
100
101
t, PULSE WIDTH (s)
102
FIGURE 5. PEAK CURRENT CAPABILITY
103
RFT1P06E
Typical Performance Curves
(Continued)
-10
-20
ID, DRAIN CURRENT (A)
IAS, AVALANCHE CURRENT (A)
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
STARTING TJ = 25oC
STARTING TJ = 150oC
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TA = 25oC
VGS = -20V
-15
VGS = -10V
VGS = -7V
-10
VGS = -6V
-5
VGS = -5V
0
-1
0
10
0.1
1
tAV, TIME IN AVALANCHE (ms)
0.01
-1.5
-3.0
-4.5
-6
-7.5
100
VDS , DRAIN TO SOURCE VOLTAGE (V)
NOTE: Refer to Intersil Application Notes AN9321 and AN9322.
FIGURE 7. SATURATION CHARACTERISTICS
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
-20
2.5
-55oC
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
ID, DRAIN CURRENT (A)
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = -15V
25oC
-15
-10
150oC
-5
0
-2
0
-4
-6
-8
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = -10V, ID = -1.4A
2.0
1.5
1.0
0.5
-80
-10
-40
VGS, GATE TO SOURCE VOLTAGE (V)
FIGURE 8. TRANSFER CHARACTERISTICS
0.8
0.6
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
4-174
80
120
160
1.2
VGS = VDS, ID = -250µA
1.0
0.4
-80
40
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
NORMALIZED GATE
THRESHOLD VOLTAGE
1.2
0
TJ, JUNCTION TEMPERATURE (oC)
ID = -250µA
1.1
1.0
0.9
0.8
-80
-40
0
40
80
120
160
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
RFT1P06E
Typical Performance Curves
(Continued)
800
VGS , GATE TO SOURCE VOLTAGE (V)
-10
C, CAPACITANCE (pF)
CISS
600
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS = CDS + CGD
400
COSS
200
CRSS
0
WAVEFORMS IN
DESCENDING ORDER:
ID = -1.4A
ID = -1.0A
ID = -0.5A
-8
VDD = -30V
-6
-4
-2
0
0
-10
-20
-30
-40
-50
VDS , DRAIN TO SOURCE VOLTAGE (V)
-60
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
0
5
10
Qg, GATE CHARGE (nC)
15
20
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
Test Circuits and Waveforms
VDS
tAV
L
0
VARY tP TO OBTAIN
REQUIRED PEAK IAS
-
RG
VDD
+
0V
VDD
DUT
tP
IAS
IAS
VDS
tP
0.01Ω
-VGS
BVDSS
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
VDS
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
VDS
Qg(TH)
0
RL
VGS = -2V
VGS = -10V
-VGS
VGS
-
Qg(-10)
VDD
+
VGS = -20V
VDD
DUT
Qg(TOT)
IG(REF)
0
IG(REF)
FIGURE 16. GATE CHARGE TEST CIRCUIT
4-175
FIGURE 17. GATE CHARGE WAVEFORM
RFT1P06E
Test Circuits and Waveforms
(Continued)
tON
tOFF
td(OFF)
td(ON)
tf
tr
0
RL
VDS
+
VGS
VDS
0V
0
RGS
10%
10%
-
90%
90%
10%
DUT
50%
-VGS
VGS
FIGURE 18. SWITCHING TIME TEST CIRCUIT
50%
PULSE WIDTH
90%
FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
Thermal Resistance vs Mounting Pad Area
The maximum rated junction temperature, TJ(MAX) , and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, PD(MAX) ,
in an application. Therefore the application’s ambient
temperature, TA (oC), and thermal impedance RθJA (oC/W)
must be reviewed to ensure that TJ(MAX) (oC) is never
exceeded. Equation 1 mathematically represents the
relationship and serves as the basis for establishing the
rating of the part.
( T JMAX – T A )
P DMAX = ---------------------------------------R θJA
state power with no air flow. This graph provides the
necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Intersil device Spice
thermal model or manually utilizing the normalized maximum
transient thermal impedance curve.
200
RθJA = 73.0 - 17.4 * ln(AREA)
In using surface mount devices such as the SOT-223
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
power dissipation ratings. Precise determination of the
PD(MAX) is complex and influenced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Intersil provides thermal information to assist the designer’s
preliminary application evaluation. Figure 20 defines the
RθJA for the device as a function of the top copper
(component side) area. This is for a horizontally positioned
FR-4 board with 1oz copper after 1000 seconds of steady
4-176
RθJA (oC/W)
(EQ. 1)
150
137oC/W - 0.026in2
110oC/W - 0.122in2
119oC/W - 0.071in2
100
50
0.01
0.1
1.0
AREA, TOP COPPER AREA (in2)
FIGURE 20. THERMAL RESISTANCE vs MOUNTING PAD AREA
Displayed on the curve are the three RθJA values listed in
the Electrical Specifications table. The three points where
chosen to depict the compromise between the copper board
area, the thermal resistance and ultimately the power
dissipation, PD(MAX) . Thermal resistances corresponding to
other component side copper areas can be obtained from
Figure 20 or by calculation using Equation 2. The area, in
square inches is the top copper area including the gate and
source pads.
R θJA = 73.0 – 17.4 × ln ( Area )
(EQ. 2)
RFT1P06E
PSPICE Electrical Model
SUBCKT RFT1P06E 2 1 3;
rev 10/16/97
CA 12 8 7.42e-10
CB 15 14 8.04e-10
CIN 6 8 5.5e-10
ESG
8
6
10
LDRAIN
DRAIN
2
5
+
RLDRAIN
DBODY 5 7DBODYMOD
DBREAK 7 11 DBREAKMOD
DPLCAP 10 6DPLCAPMOD
DESD1 91 9 DESD1MOD
DESD2 91 7DESD2MOD
RSLC1
51
+
5
ESLC
51
RSLC2
50
DPLCAP
EBREAK 5 11 17 18 -69.1
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 5 10 8 6 1
EVTHRES 6 21 19 8 1
EVTEMP 6 20 18 22 1
GATE
1
RGATE
9
IT 8 17 1
RDRAIN
16
EVTHRES
+ 19
8
EVTEMP
LGATE
RLGATE
20
18 +
22
DBODY
11
21
6
MWEAK
MMED
MSTRO
DESD1
91
DESD2
LDRAIN 2 5 1e-9
LGATE 1 9 1.73e-9
LSOURCE 3 7 3.9e-10
DBREAK
LSOURCE
CIN
RSOURCE
8
SOURCE
3
7
RLSOURCE
S1A
12
13
8
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
S2A
15
14
13
S1B
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 9.52e-2
RGATE 9 20 3.95
RLDRAIN 2 5 10
RLGATE 1 9 17.3
RLSOURCE 3 7 39
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD .144
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
RBREAK
18
17
S2B
13
S1A
S1B
S2A
S2B
+
17
18
EBREAK
CA
RVTEMP
CB
+
EGS
6
8
EDS
IT
14
+
19
VBAT
5
8
+
8
22
RVTHRES
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*22),9))}
.MODEL DBODYMOD D (IS = 4.15e-15 RS = 5.54e-2 TRS1 = -1.32e-3 TRS2 = -2.48e-6 CJO = 6.06e-10 TT = 7.54e-8)
.MODEL DBREAKMOD D (RS = 4.66e-1 TRS1 = 1.48e-3 TRS2 = -7.49e-6)
.MODEL DPLCAPMOD D (CJO = 2.49e-10 IS = 1e-30 N = 10)
.MODEL DESD1MOD D (BV=20.2 TBV1=-1.25e-3 TBV2=5.79e-7 RS=36 NBV=1 IBV=7e6)
.MODEL DESD2MOD D (BV=25.4 TBV1=-8.3e-4 TBV2=8.9e-7 NBV=1 IBV=7e6)
.MODEL MMEDMOD NMOS (VTO = -3.32 KP =.258 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MSTROMOD NMOS (VTO = -3.824 KP = 4.8 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = -3.0 KP = 0.05 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL RBREAKMOD RES (TC1 = 9.48e-4 TC2 = -1.42e-7)
.MODEL RDRAINMOD RES (TC1 = 5.4e-3 TC2 = 1.25e-5)
.MODEL RSLCMOD RES (TC1 = 1.75e-3 TC2 = 3.9e-6)
.MODEL RSOURCEMOD RES (TC1 = 5.4e-3 TC2 = 1.25e-5)
.MODEL RVTHRESMOD RES (TC1 = 0 TC2 = 0)
.MODEL RVTEMPMOD RES (TC1 = -3.55e-3 TC2 = -3.43e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5
.MODEL S1BMOD VSWITCH (RON = 1e-5
.MODEL S2AMOD VSWITCH (RON = 1e-5
.MODEL S2AMOD VSWITCH (RON = 1e-5
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
VON =5.1 VOFF= 3.1)
VON =3.1 VOFF= 5.1)
VON = 2.10 VOFF= -2.9)
VON = -2.9 VOFF= 2.10)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
4-177
RFT1P06E
SPICE Thermal Model
7
JUNCTION
rev 10/16/97
RFT1P06E
RTHERM1
CTHERM1 7 6 1.3e-4
CTHERM2 6 5 5.0e-4
CTHERM3 5 4 2.0e-3
CTHERM4 4 3 5.0e-3
CTHERM5 3 2 4.75e-2
CTHERM6 2 1 3.8e-1
CTHERM1
6
RTHERM2
RTHERM1 7 6 4.0e-2
RTHERM2 6 5 9.0e-2
RTHERM3 5 4 5.0e-1
RTHERM4 4 3 3.5
RTHERM5 3 2 20
RTHERM6 2 1 75
CTHERM2
5
RTHERM3
CTHERM3
4
RTHERM4
CTHERM4
3
RTHERM5
CTHERM5
2
RTHERM6
CTHERM6
1
CASE
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
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4-178
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