MCP14E3/MCP14E4/MCP14E5 4.0A Dual High-Speed Power MOSFET Drivers With Enable Features General Description • High Peak Output Current: 4.0A (typical) • Independent Enable Function for Each Driver Output • Low Shoot-Through/Cross-Conduction Current in Output Stage • Wide Input Supply Voltage Operating Range: - 4.5V to 18V • High Capacitive Load Drive Capability: - 2200 pF in 15 ns (typical) - 5600 pF in 26 ns (typical) • Short Delay Times: 50 ns (typical) • Latch-Up Protected: Will Withstand 1.5A Reverse Current • Logic Input Will Withstand Negative Swing Up To 5V • Space-Saving Packages: - 8-Lead 6x5 DFN, PDIP, SOIC The MCP14E3/MCP14E4/MCP14E5 devices are a family of 4.0A buffers/MOSFET drivers. Dual-inverting, dual-noninvertering, and complementary outputs are standard logic options offered. Additional control of the MCP14E3/MCP14E4/ MCP14E5 outputs is allowed by the use of separate enable functions. The ENB_A and ENB_B pins are active high and are internally pulled up to VDD. The pins maybe left floating for standard operation. The MCP14E3/MCP14E4/MCP14E5 dual-output 4.0A driver family is offered in both surface-mount and pinthrough-hole packages with a -40°C to +125°C temperature rating. The low thermal resistance of the thermally enhanced DFN package allows for greater power dissipation capability for driving heavier capacitive or resistive loads. Applications • • • • The MCP14E3/MCP14E4/MCP14E5 drivers are capable of operating from a 4.5V to 18V single power supply and can easily charge and discharge 2200 pF gate capacitance in under 15 ns (typical). They provide low impedance in both the ON and OFF states to ensure the MOSFET’s intended state will not be affected, even by large transients. The MCP14E3/ MCP14E4/MCP14E5 inputs may be driven directly from either TTL or CMOS (2.4V to 18V). Switch Mode Power Supplies Pulse Transformer Drive Line Drivers Motor and Solenoid Drive These devices are highly latch-up resistant under any conditions within their power and voltage ratings. They are not subject to damage when up to 5V of noise spiking (of either polarity) occurs on the ground pin. They can accept, without damage or logic upset, up to 1.5A of reverse current being forced back into their outputs. All terminals are fully protect against Electrostatic Discharge (ESD) up to 4 kV. Package Types MCP14E4 8-Pin MCP14E5 MCP14E3 PDIP/SOIC 2 7 6 4 5 OUT A VDD OUT B OUT A VDD OUT B OUT A VDD OUT B IN A 3 ENB_B ENB_B ENB_B OUT A OUT A VDD VDD OUT B OUT B GND VDD IN B OUT B 2 OUT A 5 ENB_A 6 ENB_B 7 ENB_B 8 ENB_B 4 8 3 1 1 ENB_A IN A GND IN B MCP14E4 MCP14E3 MCP14E5 8-Pin 6x5 DFN (1) Note 1: Exposed pad of the DFN package is electrically isolated. © 2008 Microchip Technology Inc. DS22062B-page 1 MCP14E3/MCP14E4/MCP14E5 Functional Block Diagram VDD Inverting VDD Output Internal Pull-up Non-inverting Enable 4.7 V Input Effective Input C = 20 pF (Each Input) 4.7 V MCP14E3 Dual Inverting MCP14E4 Dual Noninverting MCP14E5 One Inverting, One Noninverting GND DS22062B-page 2 © 2008 Microchip Technology Inc. MCP14E3/MCP14E4/MCP14E5 1.0 ELECTRICAL CHARACTERISTICS † Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings † Supply Voltage ................................................................+20V Input Voltage ............................... (VDD + 0.3V) to (GND – 5V) Enable Voltage .............................(VDD + 0.3V) to (GND - 5V) Input Current (VIN>VDD)................................................50 mA Package Power Dissipation (TA = 50°C) 8L-DFN ....................................................................... Note 3 8L-PDIP ........................................................................1.10W 8L-SOIC .....................................................................665 mW DC CHARACTERISTICS (NOTE 2) Electrical Specifications: Unless otherwise indicated, TA = +25°C, with 4.5V ≤ VDD ≤ 18V. Parameters Sym Min Typ Max Units Conditions Logic ‘1’, High Input Voltage VIH 2.4 1.5 — V Logic ‘0’, Low Input Voltage VIL — 1.3 0.8 V Input Current IIN –1 — 1 µA Input Voltage VIN -5 — VDD+0.3 V VOH VDD – 0.025 — — V DC Test Input 0V ≤ VIN ≤ VDD Output High Output Voltage Low Output Voltage VOL — — 0.025 V DC Test Output Resistance, High ROH — 2.5 3.5 Ω IOUT = 10 mA, VDD = 18V Output Resistance, Low ROL — 2.5 3.0 Ω IOUT = 10 mA, VDD = 18V Peak Output Current IPK — 4.0 — A VDD = 18V (Note 2) Latch-Up Protection Withstand Reverse Current IREV — >1.5 — A Duty cycle ≤ 2%, t ≤ 300 µs Rise Time tR — 15 30 ns Figure 4-1, Figure 4-2 CL = 2200 pF Fall Time tF — 18 30 ns Figure 4-1, Figure 4-2 CL = 2200 pF Propagation Delay Time tD1 — 46 55 ns Figure 4-1, Figure 4-2 Propagation Delay Time tD2 — 50 55 ns Figure 4-1, Figure 4-2 Switching Time (Note 1) Enable Function (ENB_A, ENB_B) High-Level Input Voltage VEN_H 1.60 1.90 2.90 V VDD = 12V, LO to HI Transition Low-Level Input Voltage VEN_L 1.30 2.20 2.40 V VDD = 12V, HI to LO Transition Hysteresis VHYST 0.10 0.30 0.60 V Enable Leakage Current IENBL 40 85 115 µA VDD = 12V, ENB_A = ENB_B = GND Propagation Delay Time tD3 — 60 — ns Figure 4-3 (Note 1) Propagation Delay Time tD4 — 50 — ns Figure 4-3 (Note 1) Note 1: 2: 3: Switching times ensured by design. Tested during characterization, not production tested. Package power dissipation is dependent on the copper pad area on the PCB. © 2008 Microchip Technology Inc. DS22062B-page 3 MCP14E3/MCP14E4/MCP14E5 DC CHARACTERISTICS (NOTE 2) (CONTINUED) Electrical Specifications: Unless otherwise indicated, TA = +25°C, with 4.5V ≤ VDD ≤ 18V. Parameters Sym Min Typ Max Supply Voltage VDD Supply Current IDD Units Conditions 4.5 — 18.0 V — 1.60 2.00 mA VIN_A = 3V, VIN_B = 3V, ENB_A = ENB_B = High IDD — 0.60 0.90 mA VIN_A = 0V, VIN_B = 0V, ENB_A = ENB_B = High IDD — 1.20 1.40 mA VIN_A = 3V, VIN_B = 0V, ENB_A = ENB_B = High IDD — 1.20 1.40 mA VIN_A = 0V, VIN_B = 3V, ENB_A = ENB_B = High IDD — 1.40 1.80 mA VIN_A = 3V, VIN_B = 3V, ENB_A = ENB_B = Low IDD — 0.55 0.75 mA VIN_A = 0V, VIN_B = 0V, ENB_A = ENB_B = Low IDD — 1.00 1.20 mA VIN_A = 3V, VIN_B = 0V, ENB_A = ENB_B = Low IDD — 1.00 1.20 mA VIN_A = 0V, VIN_B = 3V, ENB_A = ENB_B = Low Power Supply Note 1: 2: 3: Switching times ensured by design. Tested during characterization, not production tested. Package power dissipation is dependent on the copper pad area on the PCB. DS22062B-page 4 © 2008 Microchip Technology Inc. MCP14E3/MCP14E4/MCP14E5 DC CHARACTERISTICS (OVER OPERATING TEMPERATURE RANGE) Electrical Specifications: Unless otherwise indicated, operating temperature range with 4.5V ≤ VDD ≤ 18V. Parameters Sym Min Typ Max Units Logic ‘1’, High Input Voltage VIH 2.4 Logic ‘0’, Low Input Voltage VIL — Input Current IIN High Output Voltage Low Output Voltage Conditions — — V — 0.8 V –10 — +10 µA 0V ≤ VIN ≤ VDD VOH VDD – 0.025 — — V DC TEST VOL — — 0.025 V DC TEST Output Resistance, High ROH — 3.0 6.0 Ω IOUT = 10 mA, VDD = 18V Output Resistance, Low ROL — 3.0 5.0 Ω IOUT = 10 mA, VDD = 18V Rise Time tR — 25 40 ns Figure 4-1, Figure 4-2 CL = 2200 pF Fall Time tF — 28 40 ns Figure 4-1, Figure 4-2 CL = 2200 pF Delay Time tD1 — 50 70 ns Figure 4-1, Figure 4-2 Delay Time tD2 — 50 70 ns Figure 4-1, Figure 4-2 VEN_H 1.60 2.20 2.90 V VDD = 12V, LO to HI Transition Low-Level Input Voltage VEN_L 1.30 1.80 2.40 V VDD = 12V, HI to LO Transition Hysteresis VHYST — 0.40 — V Enable Leakage Current IENBL 40 87 115 µA VDD = 12V, ENB_A = ENB_B = GND Propagation Delay Time tD3 — 50 — ns Figure 4-3 Propagation Delay Time tD4 — 60 — ns Figure 4-3 Supply Voltage VDD 4.5 — 18.0 V Supply Current IDD — 2.0 3.0 mA VIN_A = 3V, VIN_B = 3V, ENB_A = ENB_B = High IDD — 0.8 1.1 mA VIN_A = 0V, VIN_B = 0V, ENB_A = ENB_B = High IDD — 1.5 2.0 mA VIN_A = 3V, VIN_B = 0V, ENB_A = ENB_B = High IDD — 1.5 2.0 mA VIN_A = 0V, VIN_B = 3V, ENB_A = ENB_B = High IDD — 1.8 2.8 mA VIN_A = 3V, VIN_B = 3V, ENB_A = ENB_B = Low IDD — 0.6 0.8 mA VIN_A = 0V, VIN_B = 0V, ENB_A = ENB_B = Low IDD — 1.1 1.8 mA VIN_A = 3V, VIN_B = 0V, ENB_A = ENB_B = Low IDD — 1.1 1.8 mA VIN_A = 0V, VIN_B = 3V, ENB_A = ENB_B = Low Input Output Switching Time (Note 1) Enable Function (ENB_A, ENB_B) High-Level Input Voltage Power Supply Note 1: Switching times ensured by design. © 2008 Microchip Technology Inc. DS22062B-page 5 MCP14E3/MCP14E4/MCP14E5 TEMPERATURE CHARACTERISTICS Electrical Specifications: Unless otherwise noted, all parameters apply with 4.5V ≤ VDD ≤ 18V. Parameters Sym Min Typ Max Units Specified Temperature Range TA –40 Maximum Junction Temperature TJ — — +125 °C — +150 °C Storage Temperature Range TA –65 — +150 °C Thermal Resistance, 8L-6x5 DFN θJA — 35.7 — °C/W Thermal Resistance, 8L-PDIP θJA — 89.3 — °C/W Thermal Resistance, 8L-SOIC θJA — 149.5 — °C/W Conditions Temperature Ranges Package Thermal Resistances DS22062B-page 6 Typical four-layer board with vias to ground plane © 2008 Microchip Technology Inc. MCP14E3/MCP14E4/MCP14E5 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, TA = +25°C with 4.5V ≤ VDD ≤ 18V. 100 120 10,000 pF 10,000 pF 80 Fall Time (ns) Rise Time (ns) 4,700 pF 2,200 pF 6,800 pF 100 pF 60 40 20 0 90 4,700 pF 2,200 pF 6,800 pF 100 pF 60 30 0 4 6 8 10 12 14 16 18 4 6 8 Supply Voltage (V) FIGURE 2-1: Voltage. 10 12 14 16 18 Supply Voltage (V) Rise Time vs. Supply FIGURE 2-4: Voltage. 60 Fall Time vs. Supply 60 12V 50 40 30 5V 20 18V Fall Time (ns) Rise Time (ns) 50 12V 40 18V 30 5V 20 10 10 0 100 1000 0 100 10000 1000 Capacitive Load (pF) Capacitive Load (pF) FIGURE 2-2: Load. Rise Time vs. Capacitive 22 20 Time (ns) Fall Time vs. Capacitive 60 VDD = 18V tFALL 18 FIGURE 2-5: Load. tRISE 16 14 12 10 Propagation Delay (ns) 24 10000 VDD = 12V 55 tD1 50 45 tD2 40 35 -40 -25 -10 5 20 35 50 65 80 95 110 125 4 5 Temperature (°C) FIGURE 2-3: Temperature. Rise and Fall Times vs. © 2008 Microchip Technology Inc. 6 7 8 9 10 11 12 Input Amplitude (V) FIGURE 2-6: Amplitude. Propagation Delay vs. Input DS22062B-page 7 MCP14E3/MCP14E4/MCP14E5 Typical Performance Curves (Continued) Note: Unless otherwise indicated, TA = +25°C with 4.5V ≤ VDD ≤ 18V. 80 120 Propagatin Delay (ns) Propagation Delay (ns) 140 tD1 100 80 tD2 60 40 20 VDD = 12V tD1 70 60 tD2 50 40 4 6 8 10 12 14 16 18 -40 -25 -10 5 Supply Voltage (V) Temperature (°C) Propagation Delay Time vs. FIGURE 2-10: Temperature. 1.4 1.8 1.2 1.6 1.0 Quiescent Current (mA) Quiescent Current (mA) FIGURE 2-7: Supply Voltage. Input = 1 0.8 0.6 Input = 0 0.4 0.2 0.0 Propagation Delay Time vs. VDD = 18V Input = 1 1.4 1.2 1.0 0.8 Input = 0 0.6 0.4 0.2 4 6 8 10 12 14 16 18 -40 -25 -10 5 Supply Voltage (V) FIGURE 2-8: Supply Voltage. 7 TA = 125°C 5 4 3 TA = 25°C 2 Quiescent Current vs. 8 ROUT-LO (Ω) ROUT-HI (Ω) FIGURE 2-11: Temperature. VIN = 0V (MCP14E3) VIN = 5V (MCP14E4) 7 20 35 50 65 80 95 110 125 Temperature (°C) Quiescent Current vs. 8 6 20 35 50 65 80 95 110 125 VIN = 5V (MCP14E3) VIN = 0V (MCP14E4) TA = 125°C 6 5 4 TA = 25°C 3 2 1 1 4 6 8 10 12 14 16 18 Supply Voltage (V) FIGURE 2-9: Output Resistance (Output High) vs. Supply Voltage. DS22062B-page 8 4 6 8 10 12 14 16 18 Supply Voltage (V) FIGURE 2-12: Output Resistance (Output Low) vs. Supply Voltage. © 2008 Microchip Technology Inc. MCP14E3/MCP14E4/MCP14E5 Typical Performance Curves (Continued) Note: Unless otherwise indicated, TA = +25°C with 4.5V ≤ VDD ≤ 18V. 120 VDD = 18V 100 100 kHz 80 400 kHz 200 kHz 60 40 VDD = 18V 50 kHz Supply Current (mA) Supply Current (mA) 120 650 kHz 20 0 100 6,800 pF 80 4,700 pF 60 2,200 pF 40 20 100 pF 0 1000 10000 10 Capacitive Load (pF) FIGURE 2-13: Capacitive Load. Supply Current vs. FIGURE 2-16: Frequency. 70 VDD = 12V 50 kHz 60 100 kHz 50 400 kHz 40 200 kHz 30 650 kHz 20 10 0 100 VDD = 12V 1000 50 4,700 pF 40 30 2,200 pF 20 10 10000 100 pF 10 Supply Current vs. FIGURE 2-17: Frequency. 35 VDD = 6V 50 kHz 30 100 kHz 25 400 kHz 20 200 kHz 15 650 kHz 5 0 100 1000 Supply Current vs. VDD = 6V 10,000 pF 30 6,800 pF 25 20 4,700 pF 15 2,200 pF 10 5 100 pF 0 1000 10000 10 Capacitive Load (pF) FIGURE 2-15: Capacitive Load. 100 Frequency (kHz) Supply Current (mA) Supply Current (mA) 10,000 pF 6,800 pF 0 FIGURE 2-14: Capacitive Load. 10 1000 Supply Current vs. 60 Capacitive Load (pF) 35 100 Frequency (kHz) Supply Current (mA) Supply Current (mA) 70 10,000 pF 100 Supply Current vs. © 2008 Microchip Technology Inc. 100 1000 Frequency (kHz) FIGURE 2-18: Frequency. Supply Current vs. DS22062B-page 9 MCP14E3/MCP14E4/MCP14E5 Typical Performance Curves (Continued) Note: Unless otherwise indicated, TA = +25°C with 4.5V ≤ VDD ≤ 18V. 0.7 VDD = 18V 1.9 1.7 VHI Enable Hysteresis (V) Input Threshold (V) 2.1 VLO 1.5 1.3 1.1 0.9 0.7 VDD = 12V 0.6 0.5 0.4 0.3 0.2 0.1 0.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 Temperature (°C) FIGURE 2-19: Temperature. FIGURE 2-22: Temperature. Input Threshold vs. Crossover Energy (A*sec) Input Threshold (V) Enable Hysteresis vs. 1E-06 1.8 VHI 1.6 VLO 1.4 1.2 1.0 4 6 8 10 12 14 16 1E-07 1E-08 1E-09 18 4 6 Supply Voltage (V) FIGURE 2-20: Voltage. Input Threshold vs. Supply Enable Threshold (V) VDD = 12V 2.9 VEN_H Note: 10 12 14 16 18 The values on this graph represent the loss seen by both drivers in a package during one complete cycle. For a single driver, divide the stated value by 2. For a signal transition of a single driver, divide the state value by 4. FIGURE 2-23: Supply Voltage. 2.3 2.1 8 Supply Voltage (V) 3.1 2.5 20 35 50 65 80 95 110 125 Temperature (°C) 2.0 2.7 5 VEN_L Crossover Energy vs. 1.9 1.7 1.5 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature (°C) FIGURE 2-21: Temperature. DS22062B-page 10 Enable Threshold vs. © 2008 Microchip Technology Inc. MCP14E3/MCP14E4/MCP14E5 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 3-1. TABLE 3-1: PIN FUNCTION TABLE 8-Pin PDIP, SOIC 8-Pin 6x5 DFN Symbol 1 1 ENB_A 2 2 IN A Input A 3 3 GND Ground 4 4 IN B Input B 5 5 OUT B 6 6 VDD 7 7 OUT A 8 8 ENB_B — PAD NC Note: 3.1 Description Output A Enable Output B Supply Input Output A Output B Enable Exposed Metal Pad Duplicate pins must be connected for proper operation. Control Inputs A and B The MOSFET driver inputs are a high-impedance TTL/ CMOS compatible input. The inputs also have hysteresis between the high and low input levels, allowing them to be driven from slow rising and falling signals and to provide noise immunity. 3.2 Outputs A and B Outputs A and B are CMOS push-pull outputs that are capable of sourcing and sinking 4.0A of peak current (VDD = 18V). The low output impedance ensures the gate of the MOSFET will stay in the intended state even during large transients. These outputs also have a reverse latch-up rating of 1.5A. 3.3 Supply Input (VDD) VDD is the bias supply input for the MOSFET driver and has a voltage range of 4.5V to 18V. This input must be decoupled to ground with a local ceramic capacitor. This bypass capacitor provides a localized low-impedance path for the peak currents that are to be provided to the load. 3.4 3.5 Enable A (ENB_A) The ENB_A pin is the enable control for Output A. This enable pin is internally pulled up to VDD for active high operation and can be left floating for standard operation. When the ENB_A pin is pulled below the enable pin Low Level Input Voltage (VEN_L), Output A will be in the off state regardless of the input pin state. 3.6 Enable B (ENB_B) The ENB_B pin is the enable control for Output B. This enable pin is internally pulled up to VDD for active high operation and can be left floating for standard operation. When the ENB_B pin is pulled below the enable pin Low-Level Input Voltage (VEN_L), Output B will be in the off state regardless of the input pin state. 3.7 DFN Exposed Pad The exposed metal pad of the DFN package is not internally connected to any potential. Therefore, this pad can be connected to a ground plane or other copper plane on a printed circuit board to aid in heat removal from the package. Ground (GND) Ground is the device return pin. The ground pin(s) should have a low impedance connection to the bias supply source return. High peak currents will flow out the ground pin(s) when the capacitive load is being discharged. © 2008 Microchip Technology Inc. DS22062B-page 11 MCP14E3/MCP14E4/MCP14E5 4.0 APPLICATION INFORMATION 4.1 General Information VDD = 18V MOSFET drivers are high-speed, high current devices which are intended to source/sink high peak currents to charge/discharge the gate capacitance of external MOSFETs or IGBTs. In high frequency switching power supplies, the PWM controller may not have the drive capability to directly drive the power MOSFET. A MOSFET driver like the MCP14E3/MCP14E4/MCP14E5 family can be used to provide additional source/sink current capability. An additional degree of control has been added to the MCP14E3/MCP14E4/MCP14E5 family. There are separate enable functions for each driver that allow for the immediate termination of the output pulse regardless of the state of the input signal. 4.2 The ability of a MOSFET driver to transition from a fully off state to a fully on state are characterized by the drivers rise time (tR), fall time (tF), and propagation delays (tD1 and tD2). The MCP14E3/MCP14E4/ MCP14E5 family of drivers can typically charge and discharge a 2200 pF load capacitance in 15 ns along with a typical matched propagation delay of 50 ns. Figure 4-1 and Figure 4-2 show the test circuit and timing waveform used to verify the MCP14E3/ MCP14E4/MCP14E5 timing. 0.1 µF Ceramic Output CL = 2200 pF Input MCP14E3 (1/2 MCP14E5) +5V 90% Input 0V 10% 18V tD1 tF tD2 tR 90% 90% Output 0V FIGURE 4-1: Waveform. DS22062B-page 12 10% Output CL = 2200 pF Input MCP14E4 (1/2 MCP14E5) +5V 90% 0V 10% 18V tD1 90% Output 10% 0V FIGURE 4-2: Waveform. 4.3 tR tD2 90% tF 10% Non-Inverting Driver Timing Enable Function The ENB_A and ENB_B enable pins allow for independent control of OUT A and OUT B respectively. They are active high and are internally pulled up to VDD so that the default state is to enable the driver. These pins can be left floating for normal operation. VDD = 18V Input Input 0.1 µF Ceramic Input MOSFET Driver Timing 1 µF 1 µF 10% Inverting Driver Timing When an enable pin voltage is above the enable pin high threshold voltage, VEN_H (2.4V typical), that driver output is enabled and allowed to react to changes in the INPUT pin voltage state. Likewise, when the enable pin voltage falls below the enable pin low threshold voltage, VEN_L (2.0V typical), that driver output is disabled and does not respond the changes in the INPUT pin voltage state. When the driver is disabled, the output goes to a low state. Refer to Table 4-1 for enable pin logic. The threshold voltages of the enable function are compatible with logic levels. Hysteresis is provided to help increase the noise immunity of the enable function, avoiding false triggers of the enable signal during driver switching. For robust designs, it is recommended that the slew rate of the enable pin signal be greater than 1 V/ns. There are propagation delays associated with the driver receiving an enable signal and the output reacting. These propagation delays, tD3 and tD4, are graphically represented in Figure 4-3. © 2008 Microchip Technology Inc. MCP14E3/MCP14E4/MCP14E5 TABLE 4-1: ENABLE PIN LOGIC MCP14E3 ENB_A ENB_B IN A IN B OUT A H H H H H H H L H H L H H H L L L L X X MCP14E4 MCP14E5 OUT B OUT A OUT B OUT A OUT B L L H H L H L H H L L L H L L H H H H H L L H L L L L L L L Placing a ground plane beneath the MCP14E3/ MCP14E4/MCP14E5 will help as a radiated noise shield as well as providing some heat sinking for power dissipated within the device. 5V ENB_x VEN_H 4.6 VEN_L 0V tD3 Power Dissipation The total internal power dissipation in a MOSFET driver is the summation of three separate power dissipation elements. tD4 VDD EQUATION 4-1: 90% OUT x P T = P L + P Q + P CC Where: 10% 4.4 Enable Timing Waveform. Decoupling Capacitors Careful layout and decoupling capacitors are highly recommended when using MOSFET drivers. Large currents are required to charge and discharge capacitive loads quickly. For example, 2.5A are needed to charge a 2200 pF load with 18V in 16 ns. To operate the MOSFET driver over a wide frequency range with low supply impedance, a ceramic and low ESR film capacitor are recommended to be placed in parallel between the driver VDD and GND. A 1.0 µF low ESR film capacitor and a 0.1 µF ceramic capacitor should be used. These capacitors should be placed close to the driver to minimized circuit board parasitics and provide a local source for the required current. 4.5 PCB Layout Considerations = Total power dissipation PL = Load power dissipation PQ = Quiescent power dissipation PCC = Operating power dissipation 0V FIGURE 4-3: PT 4.6.1 CAPACITIVE LOAD DISSIPATION The power dissipation caused by a capacitive load is a direct function of frequency, total capacitive load, and supply voltage. The power lost in the MOSFET driver for a complete charging and discharging cycle of a MOSFET is: EQUATION 4-2: P L = f × C T × V DD 2 Where: f = Switching frequency CT = Total load capacitance VDD = MOSFET driver supply voltage Proper PCB layout is important in a high current, fast switching circuit to provide proper device operation and robustness of design. PCB trace loop area and inductance should be minimized by the use of ground planes or trace under MOSFET gate drive signals, separate analog and power grounds, and local driver decoupling. © 2008 Microchip Technology Inc. DS22062B-page 13 MCP14E3/MCP14E4/MCP14E5 4.6.2 QUIESCENT POWER DISSIPATION The power dissipation associated with the quiescent current draw of the MCP14E3/MCP14E4/MCP14E5 depends upon the state of the input and enable pins. Refer to the DC Characteristic table for the quiescent current draw for specific combinations of input and enable pin states. The quiescent power dissipation is: EQUATION 4-3: P Q = ( I QH × D + I QL × ( 1 – D ) ) × V DD Where: IQH = Quiescent current in the high state D = Duty cycle IQL = Quiescent current in the low state VDD = MOSFET driver supply voltage 4.6.3 OPERATING POWER DISSIPATION The operating power dissipation occurs each time the MOSFET driver output transitions because for a very short period of time both MOSFETs in the output stage are on simultaneously. This cross-conduction current leads to a power dissipation describes as: EQUATION 4-4: P CC = CC × f × V DD Where: CC = Cross-conduction constant (A*sec) f = Switching frequency VDD = MOSFET driver supply voltage DS22062B-page 14 © 2008 Microchip Technology Inc. MCP14E3/MCP14E4/MCP14E5 5.0 PACKAGING INFORMATION 5.1 Package Marking Information (Not to Scale) 8-Lead DFN-S (6x5) XXXXXXX XXXXXXX XXYYWW NNN MCP14E3 e3 E/MF^^ 0814 256 8-Lead PDIP (300 mil) XXXXXXXX XXXXXNNN YYWW Legend: XX...X Y YY WW NNN e3 * Note: Example: MCP14E3 e3 E/P^^256 0814 8-Lead SOIC (150 mil) XXXXXXXX XXXXYYWW NNN Example: Example: MCP14E3E SN^^0814 e3 256 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2008 Microchip Technology Inc. DS22062B-page 15 MCP14E3/MCP14E4/MCP14E5 8-Lead Plastic Dual Flat, No Lead Package (MF) – 6x5 mm Body [DFN-S] PUNCH SINGULATED Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D1 e b N L N K E E2 E1 EXPOSED PAD NOTE 1 2 2 1 1 NOTE 1 D2 TOP VIEW BOTTOM VIEW φ A2 A A1 A3 NOTE 2 Units Dimension Limits Number of Pins MILLIMETERS MIN N NOM MAX 8 Pitch e Overall Height A – 1.27 BSC 0.85 Molded Package Thickness A2 – 0.65 0.80 Standoff A1 0.00 0.01 0.05 Base Thickness A3 0.20 REF Overall Length D 4.92 BSC Molded Package Length D1 Exposed Pad Length D2 1.00 4.67 BSC 3.85 4.00 4.15 Overall Width E 5.99 BSC Molded Package Width E1 Exposed Pad Width E2 2.16 2.31 Contact Width b 0.35 0.40 0.47 Contact Length L 0.50 0.60 0.75 Contact-to-Exposed Pad K 0.20 – – Model Draft Angle Top φ – – 12° 5.74 BSC 2.46 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package may have one or more exposed tie bars at ends. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-113B DS22062B-page 16 © 2008 Microchip Technology Inc. MCP14E3/MCP14E4/MCP14E5 8-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N NOTE 1 E1 1 3 2 D E A2 A L A1 c e eB b1 b Units Dimension Limits Number of Pins INCHES MIN N NOM MAX 8 Pitch e Top to Seating Plane A – – .210 Molded Package Thickness A2 .115 .130 .195 Base to Seating Plane A1 .015 – – Shoulder to Shoulder Width E .290 .310 .325 Molded Package Width E1 .240 .250 .280 Overall Length D .348 .365 .400 Tip to Seating Plane L .115 .130 .150 Lead Thickness c .008 .010 .015 b1 .040 .060 .070 b .014 .018 .022 eB – – Upper Lead Width Lower Lead Width Overall Row Spacing § .100 BSC .430 Notes: 1. Pin 1 visual index feature may vary, but must be located with the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-018B © 2008 Microchip Technology Inc. DS22062B-page 17 MCP14E3/MCP14E4/MCP14E5 8-Lead Plastic Small Outline (SN) – Narrow, 3.90 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D e N E E1 NOTE 1 1 2 3 α h b h A2 A c φ L A1 L1 Units Dimension Limits Number of Pins β MILLIMETERS MIN N NOM MAX 8 Pitch e Overall Height A – 1.27 BSC – Molded Package Thickness A2 1.25 – – Standoff § A1 0.10 – 0.25 Overall Width E Molded Package Width E1 3.90 BSC Overall Length D 4.90 BSC 1.75 6.00 BSC Chamfer (optional) h 0.25 – 0.50 Foot Length L 0.40 – 1.27 Footprint L1 1.04 REF Foot Angle φ 0° – 8° Lead Thickness c 0.17 – 0.25 Lead Width b 0.31 – 0.51 Mold Draft Angle Top α 5° – 15° Mold Draft Angle Bottom β 5° – 15° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-057B DS22062B-page 18 © 2008 Microchip Technology Inc. MCP14E3/MCP14E4/MCP14E5 /HDG3ODVWLF6PDOO2XWOLQH61±1DUURZPP%RG\>62,&@ 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ © 2008 Microchip Technology Inc. DS22062B-page 19 MCP14E3/MCP14E4/MCP14E5 NOTES: DS22062B-page 20 © 2008 Microchip Technology Inc. MCP14E3/MCP14E4/MCP14E5 APPENDIX A: REVISION HISTORY Revision B (April 2008) The following is the list of modifications: 1. Correct examples in Product identification System page. Revision A (September 2007) • Original Release of this Document. © 2008 Microchip Technology Inc. DS22062B-page 21 MCP14E3/MCP14E4/MCP14E5 NOTES: DS22062B-page 22 © 2008 Microchip Technology Inc. MCP14E3/MCP14E4/MCP14E5 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X XX Temperature Range Device: Package MCP14E3: 4.0A Dual MOSFET Driver, Inverting MCP14E3T: 4.0A Dual MOSFET Driver, Inverting Tape and Reel MCP14E4: 4.0A Dual MOSFET Driver, Non-Inverting MCP14E4T: 4.0A Dual MOSFET Driver, Non-Inverting Tape and Reel MCP14E5: 4.0A Dual MOSFET Driver, Complementary MCP14E5T: 4.0A Dual MOSFET Driver, Complementary Tape and Reel Temperature Range: E Package: * MF P SN = -40°C to +125°C = Dual, Flat, No-Lead (6x5 mm Body), 8-lead = Plastic DIP, (300 mil body), 8-lead = Plastic SOIC (150 mil Body), 8-Lead Examples: a) MCP14E3-E/MF: 4.0A Dual Inverting MOSFET Driver, 8LD DFN package. b) MCP14E3-E/P: 4.0A Dual Inverting MOSFET Driver, 8LD PDIP package. c) MCP14E3-E/SN: 4.0A Dual Inverting MOSFET Driver, 8LD SOIC package. a) MCP14E4-E/MF: 4.0A Dual Non-Inverting MOSFET Driver, 8LD DFN package. b) MCP14E4-E/P: 4.0A Dual Non-Inverting MOSFET Driver, 8LD PDIP package. c) MCP14E4T-E/SN: Tape and Reel, 4.0A Dual Non-Inverting MOSFET Driver, 8LD SOIC package. a) MCP14E5T-E/MF: Tape and Reel, 4.0A Dual Complementary MOSFET Driver, 8LD DFN package. b) MCP14E5-E/P: 4.0A Dual Complementary MOSFET Driver, 8LD PDIP package. c) MCP14E5-E/SN: 4.0A Dual Complementary MOSFET Driver, 8LD SOIC package. * All package offerings are Pb Free (Lead Free) © 2008 Microchip Technology Inc. DS22062B-page 23 MCP14E3/MCP14E4/MCP14E5 NOTES: DS22062B-page 24 © 2008 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2008, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. © 2008 Microchip Technology Inc. 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