THS6214 TH S6 214 TH S6 21 4 www.ti.com ....................................................................................................................................................................................................... SBOS431 – MAY 2009 Dual-Port, Differential, VDSL2 Line Driver Amplifiers FEATURES DESCRIPTION 1 • Low Power Consumption: – 21mA/Port (Full Bias Mode) – 16.2mA/Port (Mid Bias Mode) – 11.2mA/Port (Low Bias Mode) – Low-Power Shutdown Mode – IADJ Pin for Variable Bias • Low Noise: – 2.7nV/√Hz Voltage Noise – 17pA/√Hz Inverting Current Noise – 1.2pA/√Hz Noninverting Current Noise • Low MTPR Distortion: – 70dB with +20.5dBm G.993.2—Profile 8b • –93dBc HD3 (1MHz, 100Ω Differential) • High Output Current: > 416mA (25Ω Load) • Wide Output Swing: 43.2VPP (±12V, 100Ω Differential Load) • Wide Bandwidth: 150MHz (GDIFF = 10V/V) • PSRR: 50dB at 1MHz for Good Isolation • Wide Power-Supply Range: 10V to 28V The THS6214 is a dual-port, current-feedback architecture, differential line driver amplifier system ideal for xDSL systems. The device is targeted for use in VDSL2 (very-high-bit-rate digital subscriber line 2) line driver systems that enable greater than +14.5dBm line power, supporting the G.993.2 VDSL2 17a profile. It is also fast enough to support central-office transmissions of +14.5dBm line power up to 30MHz. 23 The unique architecture of the THS6214 uses minimal quiescent current while still achieving very high linearity. Differential distortion, under full bias conditions, is –93dBc at 1MHz and reduces to only –73dBc at 10MHz. Fixed multiple bias settings of the amplifiers allow for enhanced power savings for line lengths where the full performance of the amplifier is not required. To allow for even more flexibility and power savings, an adjustable current pin (IADJ) is available to further lower the bias currents. The wide output swing of 43.2VPP (100Ω differential load) with ±12V power supplies, coupled with over 416mA current drive (25Ω load), allows for wide dynamic headroom, keeping distortion minimal. The THS6214 is available in a QFN-24 or a TSSOP-24 PowerPAD™ package. APPLICATIONS • • Ideal For VDSL2 Systems Backwards-Compatible with ADSL/ADSL2+/ADSL2++ Systems +12V RS RT RF RP RG 100W RP RF RS IADJ RT +12V Figure 1. Typical VDSL2 Line Driver Circuit Using One Port of the THS6214 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments, Inc. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009, Texas Instruments Incorporated THS6214 SBOS431 – MAY 2009 ....................................................................................................................................................................................................... www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) SPECIFIED TEMPERATURE RANGE PACKAGE MARKING PRODUCT PACKAGE-LEAD (2) PACKAGE DESIGNATOR THS6214 QFN-24 RHF –40°C to +85°C 6214 THS6214 TSSOP-24 PWP –40°C to +85°C THS6214 (1) (2) ORDERING NUMBER TRANSPORT MEDIA, QUANTITY THS6214IRHFT Tape and reel, 250 THS6214IRHFR Tape and reel, 3000 THS6214IPWP Tape and reel, 60 THS6214IPWPR Tape and reel, 2000 For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. The PowerPAD™ is electrically isolated from all other pins. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range, unless otherwise noted. THS6214 UNIT Supply voltage, VS– to VS+ 28 V Input voltage, VI ±VS V Differential input voltage, VID ±2 V ±500 mA Output current, IO: Static dc (2) Continuous power dissipation See Dissipation Ratings Table Under any condition (3) Maximum junction temperature, TJ Continuous operation, long-term reliability RHF package only (4) Continuous operation, long-term reliability PWP package only (4) Storage temperature range, TSTG ESD ratings (1) (2) (3) (4) +150 °C +130 °C +140 °C –65 to +150 °C Human body model (HBM) 2000 V Charged device model (CDM) 500 V Machine model (MM) 100 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolute maximum rated conditions for extended periods may degrade device reliability. The THS6214 incorporates a PowerPAD on the underside of the chip. This pad acts as a heatsink and must be connected to a thermally dissipating plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature, which could permanently damage the device. See TI Technical Brief SLMA002 for more information about utilizing the PowerPAD thermally-enhanced package. Under high-frequency ac operation (greater than 10kHz), the short-term output current capability is much greater than the continuous dc output current rating. This short-term output current rating is about 8.5 times the dc capability, or about ±850mA. The absolute maximum junction temperature under any condition is limited by the constraints of the silicon process. The absolute maximum junction temperature for continuous operation is limited by the package constraints. Operation above this temperature may result in reduced reliability and/or lifetime of the device. DISSIPATION RATINGS (1) 2 PACKAGE θJP (°C/W) θJA (°C/W) (1) QFN-24 (RHF) 5 30 HTSSOP-24 (PWP) 7 45 For high power dissipation applications, soldering the PowerPAD to the PCB is required. Failure to do so may result in reduced reliability and/or lifetime of the device. See TI technical brief SLMA002 for more information about using the PowerPAD thermally enhanced package. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THS6214 THS6214 www.ti.com ....................................................................................................................................................................................................... SBOS431 – MAY 2009 PIN CONFIGURATIONS(1)(2) BIAS-2/D1D2 BIAS-1/D1D2 VS- VS+ D1 OUT 24 23 22 21 20 QFN-24 RHF PACKAGE (TOP VIEW) HTSSOP-24 PWP PACKAGE (TOP VIEW) D1 IN+ 1 19 D1 FB D2 IN+ 2 18 D2 FB (3) 3 17 D2 OUT 16 NC GND (1) 5 15 D3 OUT D3 IN+ 6 14 D4 IN+ 7 13 BIAS-1/D1D2 2 23 D1 OUT BIAS-2/D1D2 3 22 D1 FB D1 IN+ 4 21 D2 FB D2 IN+ 5 20 D2 OUT (3) 6 19 NC (1) (4) (4) 7 18 NC D3 FB D3 IN+ 8 17 D3 OUT D4 FB D4 IN+ 9 16 D3 FB BIAS-2/D3D4 10 15 D4 FB BIAS-1/D3D4 11 14 D4 OUT VS- 12 13 VS+ 12 IADJ D4 OUT 11 VS+ 9 10 VS- BIAS-1/D3D4 8 VS+ PowerPAD (4) BIAS-2/D3D4 24 GND 4 NC 1 (4) IADJ PowerPAD VS- (1) The PowerPAD is electrically isolated from all other pins and can be connected to any potential voltage range from VS– to VS+. Typically, the PowerPAD is connected to the GND plane because this plane tends to physically be the largest and is able to dissipate the most amount of heat. (2) The THS6214 defaults to the shutdown (disable) state if no signal is present on the bias pins. (3) The GND pin range is from VS– to (VS+ – 5V). (4) NC = no connection. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THS6214 3 THS6214 SBOS431 – MAY 2009 ....................................................................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS: VS = ±12V At TA = +25°C, GDIFF = +10V/V with RL = 100Ω differential load, RADJ = 0Ω, active impedance circuit configuration, and full bias, unless otherwise noted. Each port is independently tested. Boldface values are 100% tested at +25°C. THS6214IRHF, IPWP PARAMETER CONDITIONS MIN UNIT TEST LEVEL (1) 160 MHz C 150 MHz B TYP MAX AC PERFORMANCE Small-signal bandwidth, –3dB GDIFF = +5V/V , RF = 1.5kΩ, VO = 2VPP GDIFF = +10V/V , RF = 1.5kΩ, VO = 2VPP 120 Over –40°C to +85°C temperature range 100 0.1dB bandwidth flatness GDIFF = +10V/V , RF = 1.24kΩ Large-signal bandwidth GDIFF = +10V/V , RF = 1.24kΩ, VO = 20VPP Slew rate (10% to 90% level) GDIFF = +10V/V, VO = 20V step, differential 3200 TA = –40°C to +85°C 3000 Rise and fall time Harmonic distortion GDIFF = +10V/V, VO = 2VPP MHz B 114 MHz C 120 MHz C 3800 V/µs B 5 V/µs B ns C GDIFF = +10V/V, VO = 2VPP, RL = 100Ω differential 2nd harmonic C Full bias, f = 1MHz –100 -95 dBc -90 dBc B dBc C -85 dBc B -80 dBc B dBc C -70 dBc B -65 dBc B dBc C -65 dBc B -53 dBc B dBc C 3.2 nV/√Hz B 3.5 nV/√Hz B 1.4 pA/√Hz B 1.6 pA/√Hz B 20 pA/√Hz B 24 pA/√Hz B kΩ A kΩ B ±50 mV A TA = –40°C to +85°C ±60 mV B TA = –40°C to +85°C ±155 µV/°C B ±5 mV A ±7 mV B ±3.5 µA A TA = –40°C to +85°C ±5.5 µA B TA = –40°C to +85°C ±30 nA/°C B ±45 µA A TA = –40°C to +85°C ±55 µA B TA = –40°C to +85°C ±154 nA/°C B ±30 µA A ±40 µA B TA = –40°C to +85°C 3rd harmonic Low bias, f = 1Mhz –96 Full bias, f = 1MHz –89 TA = –40°C to +85°C 2nd harmonic Low bias, f = 1MHz –85 Full bias, f = 10MHz –75 TA = –40°C to +85°C 3rd harmonic Low bias, f = 10MHz –72 Full bias, f = 10MHz –73 TA = –40°C to +85°C Differential input voltage noise Low bias, f = 10MHz –58 f = 1MHz, input-referred 2.7 TA = –40°C to +85°C Differential noninverting current noise f = 1MHz 1.2 TA = –40°C to +85°C Differential inverting current noise f = 1MHz 17 TA = –40°C to +85°C B DC PERFORMANCE Open-loop transimpedance gain RL = 100Ω 330 700 300 Input offset voltage Input offset voltage drift Input offset voltage matching ±15 Channels 1 to 2 and 3 to 4 only ±0.5 TA = –40°C to +85°C Noninverting input bias current Noninverting input bias current drift ±1 Inverting input bias current Inverting input bias current drift ±8 Inverting input bias current matching ±8 TA = –40°C to +85°C (1) 4 Test levels: (A) 100% tested at +25°C. Over-temperature limits set by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THS6214 THS6214 www.ti.com ....................................................................................................................................................................................................... SBOS431 – MAY 2009 ELECTRICAL CHARACTERISTICS: VS = ±12V (continued) At TA = +25°C, GDIFF = +10V/V with RL = 100Ω differential load, RADJ = 0Ω, active impedance circuit configuration, and full bias, unless otherwise noted. Each port is independently tested. Boldface values are 100% tested at +25°C. THS6214IRHF, IPWP PARAMETER UNIT TEST LEVEL (1) ±9.5 V A V B 65 dB A CONDITIONS MIN TYP Each input ±9 TA = –40°C to +85°C ±8.6 Each input 53 TA = –40°C to +85°C 49 MAX INPUT CHARACTERISTICS Common-mode input range Common-mode rejection ratio Noninverting input resistance Inverting input resistance dB B 500 || 2 kΩ || pF C 50 Ω C ±10.9 V C ±10.8 V A V B V A V B mA A OUTPUT CHARACTERISTICS (2) Output voltage swing RL = 100Ω, each output Output current (sourcing and sinking) RL = 50Ω, each output ±10.6 TA = –40°C to +85°C ±10.4 RL = 25Ω, each output ±10.2 TA = –40°C to +85°C ±10 RL = 25Ω, based on VOUT tests ±408 TA = –40°C to +85°C ±400 Short-circuit output current ±416 1 mA B A C f = 1MHz, differential 0.2 Ω C f = 1MHz, VOUT = 2VPP, Port 1 to Port 2 –90 dB C Output impedance Crosstalk ±10.4 POWER SUPPLY Operating voltage IS+ Quiescent current ±5 TA = –40°C to +85°C ±5 Per port, full bias (Bias-1 = 0, Bias-2 = 0) 19.5 TA = –40°C to +85°C 17 Per port, mid bias (Bias-1 = 1, Bias-2 = 0) 15 TA = –40°C to +85°C 12.8 Per port, low bias (Bias-1 = 0, Bias-2 = 1) 10 TA = –40°C to +85°C 8.1 Per port, bias off (Bias-1 = 1, Bias-2 = 1) ±12 ±14 V A ±14 V C 21 22.5 mA A 24 mA B 16.2 17.4 mA A 18.6 mA B 12.4 mA A 13.2 mA B 0.8 mA A 1 mA B 21.5 mA A 23 mA B 16.4 mA A 17.6 mA B 11.6 mA A 11.4 mA B 0.3 mA A 0.8 mA B 1 mA C 66 dB A dB B dB A dB B 11.2 0.4 TA = –40°C to +85°C IS– Quiescent current Per port, full bias (Bias-1 = 0, Bias-2 = 0) 18.5 TA = –40°C to +85°C 16 Per port, mid bias (Bias-1 = 1, Bias-2 = 0) 14 TA = –40°C to +85°C 11.8 Per port, low bias (Bias-1 = 0, Bias-2 = 1) 9 TA = –40°C to +85°C 7.1 Per port, bias off (Bias-1 = 1, Bias-2 = 1) 20 15.2 10.2 0.1 TA = –40°C to +85°C Current through GND pin Per port, full bias (Bias-1 = 0, Bias-2 = 0) Power-supply rejection ratio (+PSRR) Power-supply rejection ratio (–PSRR) (2) Differential 54 TA = –40°C to +85°C 52 Differential 52 TA = –40°C to +85°C 50 65 Test circuit is shown in Figure 1. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THS6214 5 THS6214 SBOS431 – MAY 2009 ....................................................................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS: VS = ±12V (continued) At TA = +25°C, GDIFF = +10V/V with RL = 100Ω differential load, RADJ = 0Ω, active impedance circuit configuration, and full bias, unless otherwise noted. Each port is independently tested. Boldface values are 100% tested at +25°C. THS6214IRHF, IPWP PARAMETER CONDITIONS MIN Logic 1, with respect to GND (3), TA = –40°C to +85°C 1.9 TYP UNIT TEST LEVEL (1) V B 0.8 V B 30 µA A 35 µA B 1 µA A 1.2 µA B µs C MAX LOGIC Bias control pin logic threshold (3) Logic 0, with respect to GND , TA = –40°C to +85°C Bias pin quiescent current Bias-1, Bias-2 = 0.5V (logic 0) 20 TA = –40°C to +85°C Bias-1, Bias-2 = 3.3V (logic 1) 0.3 TA = –40°C to +85°C Turn-on time delay (tON) Time for IS to reach 50% of final value Turn-off time delay (tOFF) Time for IS to reach 50% of final value Bias pin input impedance Amplifier output impedance (3) 6 Off bias (Bias-1 = 1, Bias-2 = 1) 1 1 µs C 50 kΩ C 10 || 5 kΩ || pF C The GND pin usable range is from VS– to (VS+ – 5V). Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THS6214 THS6214 www.ti.com ....................................................................................................................................................................................................... SBOS431 – MAY 2009 ELECTRICAL CHARACTERISTICS: VS = ±6V At TA = +25°C, GDIFF = +5V/V with RL = 100Ω differential load, RADJ = 0Ω, active impedance circuit configuration, and full bias, unless otherwise noted. Each port is independently tested. THS6214IRHF, IPWP PARAMETER CONDITIONS MIN UNIT TEST LEVEL (1) 140 MHz C 140 MHz B TYP MAX AC PERFORMANCE GDIFF = +5V/V , RF = 1.5kΩ, VO = 2VPP Small-signal bandwidth, –3dB (VO = 2VPP) 0.1dB bandwidth flatness GDIFF = +10V/V , RF = 1.5kΩ, VO = 2VPP 110 TA = –40°C to +85°C 95 GDIFF = +10V/V , RF = 1.24kΩ Large-signal bandwidth GDIFF = +5V/V , RF = 1.24kΩ, VO = 20VPP Slew rate (10% to 90% level) GDIFF = +10V/V, VO = 20V step, differential 1200 Over –40°C to +85°C temperature range 1000 Rise and fall time Harmonic distortion GDIFF = +10V/V, VO = 2VPP MHz B 100 MHz C 120 MHz C 1600 V/µs B 5 V/µs B ns C GDIFF = +10V/V, VO = 2VPP, f = 1MHz, RL = 100Ω differential 2nd harmonic C Full bias –98 -92 dBc -87 dBc B dBc C -84 dBc B -79 dBc B dBc C -75 dBc B -68 dBc B dBc C -60 dBc B -54 dBc B dBc C 3.0 nV/√Hz B 3.3 nV/√Hz B 1.4 pA/√Hz B 1.6 pA/√Hz B 20 pA/√Hz B 24 pA/√Hz B kΩ A kΩ B ±45 mV A TA = –40°C to +85°C ±55 mV B TA = –40°C to +85°C ±155 µV/°C B ±5 mV A ±7 mV B ±3.5 µA A TA = –40°C to +85°C ±5.5 µA B TA = –40°C to +85°C ±30 nA/°C B ±45 µA A TA = –40°C to +85°C ±55 µA B Inverting input bias current drift TA = –40°C to +85°C ±135 nA/°C B Inverting input bias current matching ±30 µA A TA = –40°C to +85°C ±40 µA B TA = –40°C to +85°C 3rd harmonic Low bias –93 Full bias –93 TA = –40°C to +85°C 2nd harmonic Low bias –89 Full bias –80 TA = –40°C to +85°C 3rd harmonic Low bias –74 Full bias –66 TA = –40°C to +85°C Differential input voltage noise Low bias –55 f = 1MHz, input-referred 2.5 TA = –40°C to +85°C Differential noninverting current noise f = 1MHz 1.2 TA = –40°C to +85°C Differential inverting current noise f = 1MHz 17 TA = –40°C to +85°C B DC PERFORMANCE Open-loop transimpedance gain RL = 100Ω 330 TA = –40°C to +85°C 300 Input offset voltage ±10 Input offset voltage drift Input offset voltage matching 650 Channels 1 to 2 and 3 to 4 only ±0.5 TA = –40°C to +85°C Noninverting input bias current Noninverting input bias current drift Inverting input bias current (1) ±1 ±8 ±8 Test levels: (A) 100% tested at +25°C. Over-temperature limits set by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THS6214 7 THS6214 SBOS431 – MAY 2009 ....................................................................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS: VS = ±6V (continued) At TA = +25°C, GDIFF = +5V/V with RL = 100Ω differential load, RADJ = 0Ω, active impedance circuit configuration, and full bias, unless otherwise noted. Each port is independently tested. THS6214IRHF, IPWP PARAMETER UNIT TEST LEVEL (1) ±3.0 V A V B 62 dB A CONDITIONS MIN TYP Each input ±2.9 TA = –40°C to +85°C ±2.7 Each input 51 TA = –40°C to +85°C 47 MAX INPUT CHARACTERISTICS Common-mode input range Common-mode rejection ratio Noninverting input resistance Inverting input resistance dB B 500 || 2 kΩ || pF C 55 Ω C ±4.9 V C ±4.9 V A V B V A V B mA A OUTPUT CHARACTERISTICS (2) RL = 100Ω, each output Output voltage swing Output current (sourcing and sinking) RL = 50Ω, each output ±4.75 TA = –40°C to +85°C ±4.6 RL = 25Ω, each output ±4.55 TA = –40°C to +85°C ±4.4 RL = 25Ω, based on VOUT tests ±182 TA = –40°C to +85°C ±176 Short-circuit output current ±188 ±1 mA B A C f = 1MHz, differential 0.2 Ω C f = 1MHz, VOUT = 2VPP, Port 1 to Port 2 -90 dB C Output impedance Crosstalk ±4.7 POWER SUPPLY ±5 Operating voltage IS+ Quiescent current TA = –40°C to +85°C ±5 Per port, full bias (Bias-1 = 0, Bias-2 = 0) 13 TA = –40°C to +85°C 10 Per port, mid bias (Bias-1 = 1, Bias-2 = 0) 10.2 TA = –40°C to +85°C 9.3 Per port, low bias (Bias-1 = 0, Bias-2 = 1) 7.4 TA = –40°C to +85°C 6.7 Per port, bias off (Bias-1 = 1, Bias-2 = 1) ±6 ±14 V A ±14 V C 17 21 mA A 22 mA B 13.2 16.2 mA A 16.4 mA B 11.4 mA A 11.6 mA B 0.8 mA A 0.9 mA B 20 mA A 21 mA B 15.2 mA A 15.4 mA B 10.4 mA A 10.6 mA B 0.3 mA A 0.5 mA B 1 mA C 64 dB A dB B dB A dB B 9.4 0.5 TA = –40°C to +85°C IS– Quiescent current Per port, full bias (Bias-1 = 0, Bias-2 = 0) 12 TA = –40°C to +85°C 9 Per port, mid bias (Bias-1 = 1, Bias-2 = 0) 9.2 TA = –40°C to +85°C 8.3 Per port, low bias (Bias-1 = 0, Bias-2 = 1) 6.4 TA = –40°C to +85°C 5.7 Per port, bias off (Bias-1 = 1, Bias-2 = 1) 16 12.2 8.4 0.1 TA = –40°C to +85°C Current through GND pin Per port, full bias (Bias-1 = 0, Bias-2 = 0) Power-supply rejection ratio (+PSRR) Power-supply rejection ratio (–PSRR) (2) 8 Differential 54 TA = –40°C to +85°C 52 Differential 52 TA = –40°C to +85°C 50 63 Test circuit is shown in Figure 1. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THS6214 THS6214 www.ti.com ....................................................................................................................................................................................................... SBOS431 – MAY 2009 ELECTRICAL CHARACTERISTICS: VS = ±6V (continued) At TA = +25°C, GDIFF = +5V/V with RL = 100Ω differential load, RADJ = 0Ω, active impedance circuit configuration, and full bias, unless otherwise noted. Each port is independently tested. THS6214IRHF, IPWP PARAMETER CONDITIONS MIN Logic 1, with respect to GND (3), TA = –40°C to +85°C 1.9 TYP UNIT TEST LEVEL (1) V B 0.8 V B 30 µA A 35 µA B 1 µA A 1.2 µA B µs C MAX LOGIC Bias control pin logic threshold (3) Logic 0, with respect to GND , TA = –40°C to +85°C Bias-1, Bias-2 = 0.5V (logic 0) 20 TA = –40°C to +85°C Bias pin quiescent current Bias-1, Bias-2 = 3.3V (logic 1) 0.3 TA = –40°C to +85°C Turn-on time delay (tON) Time for IS to reach 50% of final value Turn-off time delay (tOFF) Time for IS to reach 50% of final value 1 1 µs C 50 kΩ C 10 || 5 kΩ || pF C Bias pin input impedance Amplifier output impedance (3) Off bias (Bias-1 = 1, Bias-2 = 1) The GND pin usable range is from VS– to (VS+ – 5V). Table 1. Logic Table BIAS-1 BIAS-2 FUNCTION DESCRIPTION 0 0 Full bias mode (100%) Amplifiers on with lowest distortion possible (default state) 1 0 Mid bias mode (75%) Amplifiers on with power savings and a reduction in distortion performance 0 1 Low bias mode (50%) Amplifiers on with enhanced power savings and a reduction of overall performance 1 1 Shutdown mode Amplifiers off and output has high impedance Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THS6214 9 THS6214 SBOS431 – MAY 2009 ....................................................................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS: VS = ±12V, Full Bias At TA = +25°C, GDIFF = +10V/V, GCM = 1V/V, RADJ = 0Ω, RF = 1.24kΩ, and RL = 100Ω, unless otherwise noted. SMALL-SIGNAL FREQUENCY RESPONSE vs BIAS MODE SMALL-SIGNAL FREQUENCY RESPONSE 3 0 -3 -6 GDIFF = 10V/V RF = 1.24kW -9 -12 -15 Full Bias Normalized Gain (dB) 0 Normalized Gain (dB) 3 GDIFF = 5V/V RF = 1.5kW GCM = 1V/V VO = 2VPP RADJ = 0W RL = 100W -3 -6 75% Bias -9 -12 -15 -18 10M 100M GDIFF = 10V/V GCM = 1V/V VO = 2VPP RADJ = 0W RL = 100W 50% Bias -18 10M 400M 100M Frequency (Hz) Frequency (Hz) Figure 2. Figure 3. PULSE RESPONSE 12 0 8 -3 VO = 4VPP -6 VO = 2VPP VO = 20VPP -9 GDIFF = 10V/V GCM = 1V/V RADJ = 0W RL = 100W -12 -15 -18 0 VO = 8VPP Output Voltage (V) 3 1.2 GDIFF = 10V/V GCM = 1V/V RL = 100W 4 0.8 0.4 Small-Signal ±500mVP Right Scale 0 0 -4 -0.4 Large-Signal Pulse Response (±10VP) Left Scale -8 -0.8 -12 120 60 180 240 Output Voltage (V) Normalized Gain (dB) LARGE-SIGNAL FREQUENCY RESPONSE 400M -1.2 300 Time (10ns/div) Frequency (MHz) Figure 4. Figure 5. RECOMMENDED RS vs CAPACITIVE LOAD FREQUENCY RESPONSE vs CAPACITIVE LOAD 100 23 RS Optimized for 100% Bias 22pF 20 470pF Gain (dB) RS (W) 17 10 100pF 14 THS6214 10 100 10 1000 CL VIN 5 1 47pF 11 8 1 39pF RS 1kW VOUT Optional RS THS6214 2 10M 100M Capacitive Load (pF) Frequency (Hz) Figure 6. Figure 7. Submit Documentation Feedback 300M Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THS6214 THS6214 www.ti.com ....................................................................................................................................................................................................... SBOS431 – MAY 2009 TYPICAL CHARACTERISTICS: VS = ±12V, Full Bias (continued) At TA = +25°C, GDIFF = +10V/V, GCM = 1V/V, RADJ = 0Ω, RF = 1.24kΩ, and RL = 100Ω, unless otherwise noted. HARMONIC DISTORTION vs FREQUENCY GDIFF = 10V/V GCM = 1V/V VO = 2VPP RL = 100W -60 -70 -80 HARMONIC DISTORTION vs OUTPUT VOLTAGE -60 Harmonic Distortion (dBc) Harmonic Distortion (dBc) -50 Third Harmonic Second Harmonic -90 -100 GDIFF = 10V/V GCM = 1V/V RL = 100W f = 1MHz -70 -80 Third Harmonic -90 -100 Second Harmonic -110 -120 -110 400k 10M 1M 0.5 40M 1 10 Figure 8. Figure 9. HARMONIC DISTORTION vs SUPPLY VOLTAGE -82 Harmonic Distortion (dBc) HARMONIC DISTORTION vs LOAD RESISTANCE GDIFF = 10V/V GCM = 1V/V VO = 2VPP RL = 100W f = 1MHz -84 -86 -88 Third Harmonic -92 -94 -96 Second Harmonic -70 GDIFF = 10V/V GCM = 1V/V VO = 2VPP f = 1MHz Third Harmonic Harmonic Distortion (dBc) -80 -90 20 Output Voltage (VPP) Frequency (Hz) -80 -90 -100 Second Harmonic -110 -98 -100 -120 4 5 6 7 8 9 10 11 12 50 100 1k Supply Voltage (±VS) Resistance (W) Figure 10. Figure 11. HARMONIC DISTORTION vs NONINVERTING GAIN TWO-TONE, THIRD-ORDER INTERMODULATION INTERCEPT 55 -85 Third Harmonic -95 -100 GDIFF = 10V/V GCM = 1V/V VO = 2VPP RL = 100W f = 1MHz Second Harmonic -105 -110 Intercept Point (dBm) Harmonic Distortion (dBc) 50 -90 45 40 35 30 25 20 15 1 10 30 0 Gain (V/V) 5 10 15 20 25 30 Frequency (MHz) Figure 12. Figure 13. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THS6214 11 THS6214 SBOS431 – MAY 2009 ....................................................................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS: VS = ±12V, Full Bias (continued) At TA = +25°C, GDIFF = +10V/V, GCM = 1V/V, RADJ = 0Ω, RF = 1.24kΩ, and RL = 100Ω, unless otherwise noted. INPUT VOLTAGE AND CURRENT NOISE DENSITY 12 10 8 6 4 2 0 -2 1W Internal -4 Power Dissipation -6 -8 -10 -12 -14 -600 -400 -200 Output Voltage Noise Density (nV/ÖHz) Input Current Noise Density (pA/ÖHz) Output Voltage (V) OUTPUT VOLTAGE AND CURRENT LIMITATIONS 1W Internal Power Dissipation 50W Load Line 100W Load Line 1000 Voltage and current noise contributing to differential noise 100 Inverting Current Noise (17.4pA/ÖHz) Voltage Noise (2.7nV/ÖHz) 10 Noninverting Current Noise (1.2pV/ÖHz) 1 0 200 1k 100 600 400 10k Figure 14. 1M 10M Figure 15. QUIESCENT CURRENT FOR FULL BIAS SETTING vs RADJ PSRR vs FREQUENCY 60 Power-Supply Rejection Ratio (dB) 25 Quiescent Current (±IQ, mA) 100k Frequency (Hz) Output Current (mA) 20 15 +IQ 10 -IQ 5 -PSRR 50 +PSRR 40 30 20 10 0 0 0 1 2 3 4 5 1k 6 10k 100k 1M RADJ (kW) Frequency (Hz) Figure 16. Figure 17. OPEN-LOOP GAIN AND PHASE 10M 100M CLOSED-LOOP OUTPUT IMPEDANCE 140 10 0 100 -90 Phase 80 -135 60 -180 40 -225 20 -270 0 -315 10k 100k 1M 10M 100M 1G Output Impedance (W) -45 Transimpedance Phase (°) Transimpedance Gain (dBW) Gain 120 1 0.1 0.01 0.001 100k Frequency (Hz) 10M 100M Frequency (Hz) Figure 18. 12 1M Figure 19. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THS6214 THS6214 www.ti.com ....................................................................................................................................................................................................... SBOS431 – MAY 2009 TYPICAL CHARACTERISTICS: VS = ±12V, Mid Bias At TA = +25°C, GDIFF = +10V/V, GCM = 1V/V, RADJ = 0Ω, RF = 1.24kΩ, and RL = 100Ω, unless otherwise noted. SMALL-SIGNAL FREQUENCY RESPONSE LARGE-SIGNAL FREQUENCY RESPONSE 3 3 GDIFF = 5V/V RF = 1.5kW 0 Normalized Gain (dB) Normalized Gain (dB) 0 -3 GDIFF = 10V/V RF = 1.24kW -6 -9 -12 -15 GCM = 1V/V VO = 2VPP RL = 100W -3 VO = 20VPP -9 VO = 8VPP -12 -18 100M 400M VO = 2VPP GCM = 1V/V GDIFF = 10V/V RL = 100W -15 -18 10M VO = 4VPP -6 0 20 40 60 80 100 120 140 160 180 200 220 240 260 Frequency (Hz) Frequency (MHz) Figure 20. Figure 21. PULSE RESPONSE QUIESCENT CURRENT FOR MID BIAS SETTING vs RADJ 12 1.2 8 0.8 18 0.4 Small-Signal ±500mVP Right Scale 0 0 -4 -0.4 Large-Signal Pulse Response (±10VP) Left Scale -8 -0.8 -12 Quiescent Current (±IQ, mA) 4 Output Voltage (V) Output Voltage (V) 16 14 12 10 8 +IQ 6 -IQ 4 2 -1.2 0 Time (10ns/div) 0 1 2 3 4 5 6 RADJ (kW) Figure 22. Figure 23. RECOMMENDED RS vs CAPACITIVE LOAD FREQUENCY RESPONSE vs CAPACITIVE LOAD 100 23 RS Optimized for 100% Bias 22pF 20 470pF Gain (dB) RS (W) 17 10 100pF 14 THS6214 100 10 1000 CL VIN 5 1 47pF 11 8 1 39pF RS 1kW VOUT Optional RS THS6214 2 10M 100M Capacitive Load (pF) Frequency (Hz) Figure 24. Figure 25. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THS6214 300M 13 THS6214 SBOS431 – MAY 2009 ....................................................................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS: VS = ±12V, Mid Bias (continued) At TA = +25°C, GDIFF = +10V/V, GCM = 1V/V, RADJ = 0Ω, RF = 1.24kΩ, and RL = 100Ω, unless otherwise noted. HARMONIC DISTORTION vs FREQUENCY GDIFF = 10V/V GCM = 1V/V VO = 2VPP RL = 100W -60 -70 HARMONIC DISTORTION vs OUTPUT VOLTAGE -70 Third Harmonic Second Harmonic -80 GDIFF = 10V/V GCM = 1V/V RL = 100W f = 1MHz -75 Harmonic Distortion (dBc) Harmonic Distortion (dBc) -50 -90 -100 -80 Third Harmonic -85 -90 -95 Second Harmonic -100 -105 -110 -110 400k 10M 1M 0 40M 4 2 6 Figure 26. HARMONIC DISTORTION vs SUPPLY VOLTAGE Second Harmonic -100 Harmonic Distortion (dBc) Harmonic Distortion (dBc) Third Harmonic -60 -105 GDIFF = 10V/V GCM = 1V/V VO = 2VPP f = 1MHz -70 -80 16 Third Harmonic -90 -100 Second Harmonic -110 5 6 7 8 9 10 11 12 10 100 Supply Voltage (±VS) 1k Resistance (W) Figure 28. Figure 29. HARMONIC DISTORTION vs NONINVERTING GAIN TWO-TONE, THIRD-ORDER INTERMODULATION INTERCEPT -85 60 50 -90 Third Harmonic -95 Second Harmonic -100 GDIFF = 10V/V GCM = 1V/V VO = 2VPP RL = 100W f = 1MHz -105 -110 1 10 20 Intercept Point (dBm) Harmonic Distortion (dBc) 14 -120 4 40 30 20 10 0 0 Gain (V/V) 5 10 15 20 25 30 Frequency (MHz) Figure 30. 14 12 HARMONIC DISTORTION vs LOAD RESISTANCE GDIFF = 10V/V GCM = 1V/V VO = 2VPP RL = 100W f = 1MHz -85 -95 10 Figure 27. -80 -90 8 Output Voltage (VPP) Frequency (Hz) Figure 31. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THS6214 THS6214 www.ti.com ....................................................................................................................................................................................................... SBOS431 – MAY 2009 TYPICAL CHARACTERISTICS: VS = ±12V, Low Bias At TA = +25°C, GDIFF = +10V/V, GCM = 1V/V, RADJ = 0Ω, RF = 1.24kΩ, and RL = 100Ω, unless otherwise noted. SMALL-SIGNAL FREQUENCY RESPONSE LARGE-SIGNAL FREQUENCY RESPONSE 3 6 GDIFF = 5V/V RF = 1.5kW 0 0 Normalized Gain (dB) Normalized Gain (dB) 3 -3 -6 GDIFF = 10V/V RF = 1.24kW -9 -12 -15 GCM = 1V/V VO = 2VPP RL = 100W 100M -12 GDIFF = 10V/V GCM = 1V/V RL = 100W 300M 0 20 40 VO = 2VPP 60 80 100 120 140 160 180 200 220 Frequency (MHz) Figure 32. Figure 33. SUPPLY CURRENT FOR LOW BIAS SETTING vs RADJ 0.8 0 -4 -0.4 Large-Signal Pulse Response (±10VP) Left Scale -0.8 -12 Output Voltage (V) 0.4 Small-Signal ±500mVP Right Scale 14 1.2 Quiescent Current (±IQ, mA) GDIFF = 10V/V GCM = 1V/V RL = 100W 8 Output Voltage (V) -9 Frequency (Hz) PULSE RESPONSE -8 VO = 4VPP VO = 8VPP -18 12 0 VO = 20VPP -6 -15 -18 10M 4 -3 12 10 8 6 +IQ 4 -IQ 2 0 -1.2 0 Time (10ns/div) 1 2 3 4 5 6 RADJ (kW) Figure 34. Figure 35. RECOMMENDED RS vs CAPACITIVE LOAD FREQUENCY RESPONSE vs CAPACITIVE LOAD 100 26 RS Optimized for 100% Bias 22pF 23 Gain (dB) RS (W) 20 10 100pF 17 470pF THS6214 14 11 39pF RS 47pF CL VIN 1kW VOUT Optional 8 RS 5 1 1 100 10 1000 THS6214 2 10M 100M Capacitive Load (pF) Frequency (Hz) Figure 36. Figure 37. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THS6214 200M 15 THS6214 SBOS431 – MAY 2009 ....................................................................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS: VS = ±12V, Low Bias (continued) At TA = +25°C, GDIFF = +10V/V, GCM = 1V/V, RADJ = 0Ω, RF = 1.24kΩ, and RL = 100Ω, unless otherwise noted. HARMONIC DISTORTION vs FREQUENCY GDIFF = 10V/V GCM = 1V/V VO = 2VPP RL = 100W -50 -60 HARMONIC DISTORTION vs OUTPUT VOLTAGE -60 Harmonic Distortion (dBc) Harmonic Distortion (dBc) -40 Third Harmonic -70 -80 Second Harmonic -90 -100 GDIFF = 10V/V GCM = 1V/V RL = 100W f = 1MHz -70 -80 Third Harmonic -90 Second Harmonic -100 -110 -120 -110 100k 10M 1M 0 30M 4 2 6 Figure 38. HARMONIC DISTORTION vs SUPPLY VOLTAGE Third Harmonic -90 Second Harmonic GDIFF = 10V/V GCM = 1V/V VO = 2VPP RL = 100W f = 1MHz -100 Harmonic Distortion (dBc) Harmonic Distortion (dBc) -85 -95 12 14 16 HARMONIC DISTORTION vs LOAD RESISTANCE -80 -105 GDIFF = 10V/V GCM = 1V/V VO = 2VPP f = 1MHz -85 Third Harmonic -90 -95 Second Harmonic -100 -105 -110 4 5 6 7 8 9 10 11 12 50 100 1k Supply Voltage (±VS) Resistance (W) Figure 40. Figure 41. HARMONIC DISTORTION vs NONINVERTING GAIN TWO-TONE, THIRD-ORDER INTERMODULATION INTERCEPT -85 55 50 Third Harmonic -90 Intercept Point (dBm) Harmonic Distortion (dBc) 10 Figure 39. -80 -95 Second Harmonic -100 GDIFF = 10V/V GCM = 1V/V VO = 2VPP RL = 100W f = 1MHz -105 -110 45 40 35 30 25 20 15 1 10 20 0 Gain (V/V) 5 10 15 20 25 30 Frequency (MHz) Figure 42. 16 8 Output Voltage (VPP) Frequency (Hz) Figure 43. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THS6214 THS6214 www.ti.com ....................................................................................................................................................................................................... SBOS431 – MAY 2009 TYPICAL CHARACTERISTICS: VS = ±6V, Full Bias At TA = +25°C, GDIFF = +5V/V, GCM = 1V/V, RADJ = 0Ω, RF = 1.82kΩ, and RL = 100Ω, unless otherwise noted. SMALL-SIGNAL FREQUENCY RESPONSE 3 3 Normalized Gain (dB) 0 Normalized Gain (dB) SMALL-SIGNAL FREQUENCY RESPONSE vs BIAS 6 GDIFF = 5V/V RF = 1.82kW -3 GDIFF = 10V/V RF = 1.5kW -6 -9 -12 -15 GCM = 1V/V VO = 2VPP RL = 100W 100M 75% Bias -3 -6 50% Bias -9 -12 -15 -18 10M Full Bias 0 GDIFF = 5V/V GCM = 1V/V VO = 2VPP RL = 100W -18 10M 400M 100M Frequency (Hz) Frequency (Hz) Figure 44. Figure 45. LARGE-SIGNAL FREQUENCY RESPONSE PULSE RESPONSE 7.5 Large-Signal Pulse Response GDIFF = 5V/V (±5VP) Left Scale GCM = 1V/V RL = 100W 6.0 0 VO = 4VPP -6 VO = 16VPP -9 VO = 2VPP -12 GDIFF = 5V/V GCM = 1V/V RL = 100W -15 -18 0 50 VO = 20VPP Output Voltage (V) 4.5 3.0 150 200 250 300 1.6 1.2 0.8 1.5 0.4 Small-Signal Pulse Response (±500mVP) Right Scale 0 -1.5 0 -0.4 -3.0 -0.8 -4.5 -1.2 -6.0 -1.6 -7.5 100 2.0 Output Voltage (V) Normalized Gain (3dB/div) 3 -3 400M -2.0 Time (10ns/div) 350 Frequency (MHz) Figure 46. Figure 47. RECOMMENDED RS vs CAPACITIVE LOAD FREQUENCY RESPONSE vs CAPACITIVE LOAD 17 100 RS Optimized for 100% Bias 14 Gain (dB) RS (W) 470pF 10 11 22pF RS THS6214 100pF 39pF 8 CL VIN 5 1kW VOUT Optional 47pF RS THS6214 1 1 100 10 1000 2 10M 100M Capacitive Load (pF) Frequency (Hz) Figure 48. Figure 49. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THS6214 300M 17 THS6214 SBOS431 – MAY 2009 ....................................................................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS: VS = ±6V, Full Bias (continued) At TA = +25°C, GDIFF = +5V/V, GCM = 1V/V, RADJ = 0Ω, RF = 1.82kΩ, and RL = 100Ω, unless otherwise noted. HARMONIC DISTORTION vs FREQUENCY GDIFF = 5V/V GCM = 1V/V VO = 2VPP RL = 100W -60 -70 HARMONIC DISTORTION vs OUTPUT VOLTAGE -55 GDIFF = 5V/V GCM = 1V/V VO = 2VPP RL = 100W f = 1MHz -60 Harmonic Distortion (dBc) Harmonic Distortion (dBc) -50 Third Harmonic -80 -90 Second Harmonic -100 -65 -70 -75 Third Harmonic -80 -85 Second Harmonic -90 -95 -100 -110 400k -105 10M 1M 40M 0 8 10 Figure 50. Figure 51. HARMONIC DISTORTION vs SUPPLY VOLTAGE -85 Third Harmonic -95 12 14 16 HARMONIC DISTORTION vs LOAD RESISTANCE GDIFF = 5V/V GCM = 1V/V VO = 2VPP RL = 100W f = 1MHz Second Harmonic -100 -75 Harmonic Distortion (dBc) Harmonic Distortion (dBc) 6 Output Voltage (VPP) -80 -90 4 2 Frequency (Hz) GDIFF = 5V/V GCM = 1V/V VO = 2VPP f = 1MHz -80 -85 -90 Third Harmonic -95 Second Harmonic -100 -105 -105 -110 4 5 6 7 8 9 10 11 50 12 100 1k Supply Voltage (±VS) Resistance (W) Figure 52. Figure 53. HARMONIC DISTORTION vs NONINVERTING GAIN TWO-TONE, THIRD-ORDER INTERMODULATION INTERCEPT -80 60 Third Harmonic -90 -95 Second Harmonic -100 GDIFF = 5V/V GCM = 1V/V VO = 2VPP RL = 100W f = 1MHz -105 Intercept Point (dBm) Harmonic Distortion (dBc) 55 -85 50 45 40 35 30 25 20 1 10 20 0 Gain (V/V) 10 15 20 25 30 Frequency (MHz) Figure 54. 18 5 Figure 55. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THS6214 THS6214 www.ti.com ....................................................................................................................................................................................................... SBOS431 – MAY 2009 TYPICAL CHARACTERISTICS: VS = ±6V, Full Bias (continued) At TA = +25°C, GDIFF = +5V/V, GCM = 1V/V, RADJ = 0Ω, RF = 1.82kΩ, and RL = 100Ω, unless otherwise noted. QUIESCENT CURRENT FOR FULL BIAS SETTING vs RADJ 20 Quiescent Current (±IQ, mA) 18 16 14 12 10 8 +IQ 6 -IQ 4 2 0 0 1 2 3 4 5 6 RADJ (kW) Figure 56. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THS6214 19 THS6214 SBOS431 – MAY 2009 ....................................................................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS: VS = ±6V, Mid Bias At TA = +25°C, GDIFF = +5V/V, GCM = 1V/V, RADJ = 0Ω, RF = 1.82kΩ, and RL = 100Ω, unless otherwise noted. SMALL-SIGNAL FREQUENCY RESPONSE 3 GDIFF = 5V/V RF = 1.82kW 0 Normalized Gain (dB) 0 Normalized Gain (dB) LARGE-SIGNAL FREQUENCY RESPONSE 3 -3 GDIFF = 10V/V RF = 1.5kW -6 -9 -12 GCM = 1V/V VO = 2VPP RL = 100W -15 0 150 200 Figure 58. 250 300 QUIESCENT CURRENT FOR MID BIAS SETTING vs RADJ 2.0 16 1.2 0.4 0 -0.4 Quiescent Current (±IQ, mA) 1.6 Output Voltage (V) Output Voltage (V) 100 Figure 57. Small-Signal Pulse Response (±500mVP) Right Scale 0 50 VO = 20VPP Frequency (MHz) 0.8 -1.5 GDIFF = 5V/V GCM = 1V/V RL = 100W Frequency (Hz) 3.0 1.5 VO = 2VPP -12 300M PULSE RESPONSE 4.5 VO = 16VPP -9 -18 100M Large-Signal Pulse Response GDIFF = 5V/V (±5VP) Left Scale GCM = 1V/V RL = 100W 6.0 VO = 4VPP -6 -15 -18 10M 7.5 -3 14 12 10 8 +IQ 6 -3.0 -0.8 -4.5 -1.2 -6.0 -1.6 2 -7.5 -2.0 0 -IQ 4 Time (10ns/div) 0 1 2 3 4 5 6 RADJ (kW) Figure 59. Figure 60. RECOMMENDED RS vs CAPACITIVE LOAD FREQUENCY RESPONSE vs CAPACITIVE LOAD 17 100 22pF RS Optimized for 100% Bias 14 470pF 39pF Gain (dB) RS (W) RS 10 11 8 THS6214 CL VIN 1kW VOUT Optional 100pF RS 5 THS6214 47pF 1 1 20 100 10 1000 2 10M 100M Capacitive Load (pF) Frequency (Hz) Figure 61. Figure 62. Submit Documentation Feedback 200M Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THS6214 THS6214 www.ti.com ....................................................................................................................................................................................................... SBOS431 – MAY 2009 TYPICAL CHARACTERISTICS: VS = ±6V, Mid Bias (continued) At TA = +25°C, GDIFF = +5V/V, GCM = 1V/V, RADJ = 0Ω, RF = 1.82kΩ, and RL = 100Ω, unless otherwise noted. HARMONIC DISTORTION vs FREQUENCY GDIFF = 5V/V GCM = 1V/V VO = 2VPP RL = 100W -50 -60 HARMONIC DISTORTION vs OUTPUT VOLTAGE -60 Third Harmonic -70 -80 -90 Second Harmonic -100 -70 Third Harmonic -75 -80 -85 Second Harmonic -90 -95 -110 400k -100 10M 1M 40M 0 4 2 6 10 Output Voltage (VPP) Figure 63. Figure 64. HARMONIC DISTORTION vs SUPPLY VOLTAGE Third Harmonic -90 Second Harmonic -95 -80 Harmonic Distortion (dBc) -85 12 14 16 HARMONIC DISTORTION vs LOAD RESISTANCE GDIFF = 5V/V GCM = 1V/V VO = 2VPP RL = 100W f = 1MHz -100 GDIFF = 5V/V GCM = 1V/V VO = 2VPP f = 1MHz -85 -90 Third Harmonic -95 Second Harmonic -100 -105 -110 4 5 6 7 8 9 10 11 50 12 100 1k Supply Voltage (±VS) Resistance (W) Figure 65. Figure 66. HARMONIC DISTORTION vs NONINVERTING GAIN TWO-TONE, THIRD-ORDER INTERMODULATION INTERCEPT -86 60 55 -88 Third Harmonic -90 -92 -94 -96 Second Harmonic GDIFF = 5V/V GCM = 1V/V VO = 2VPP RL = 100W f = 1MHz -98 Intercept Point (dBm) Harmonic Distortion (dBc) 8 Frequency (Hz) -80 Harmonic Distortion (dBc) GDIFF = 5V/V GCM = 1V/V RL = 100W f = 1MHz -65 Harmonic Distortion (dBc) Harmonic Distortion (dBc) -40 50 45 40 35 30 25 20 1 10 20 0 Gain (V/V) 5 10 15 20 25 30 Frequency (MHz) Figure 67. Figure 68. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THS6214 21 THS6214 SBOS431 – MAY 2009 ....................................................................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS: VS = ±6V, Low Bias At TA = +25°C, GDIFF = +5V/V, GCM = 1V/V, RADJ = 0Ω, RF = 1.82kΩ, and RL = 100Ω, unless otherwise noted. SMALL-SIGNAL FREQUENCY RESPONSE LARGE-SIGNAL FREQUENCY RESPONSE 6 6 GDIFF = 5V/V RF = 1.82kW 3 0 Normalized Gain (dB) Normalized Gain (dB) 3 -3 GDIFF = 10V/V RF = 1.5kW -6 -9 -12 GCM = 1V/V VO = 2VPP RL = 100W -15 0 20 40 60 80 100 120 140 160 180 200 220 240 260 Figure 70. QUIESCENT CURRENT FOR LOW BIAS SETTING vs RADJ 2.0 0 -0.4 -3.0 -0.8 -4.5 -1.2 -6.0 -1.6 Quiescent Current (±IQ, mA) 1.2 0.4 -7.5 12 1.6 Output Voltage (V) Output Voltage (V) GDIFF = 5V/V GCM = 1V/V RL = 100W Frequency (MHz) Small-Signal Pulse Response (±500mVP) Right Scale 0 VO = 2VPP VO = 20VPP -12 Figure 69. 0.8 -1.5 VO = 4VPP Frequency (Hz) 3.0 1.5 -9 300M PULSE RESPONSE 4.5 VO = 16VPP -6 -18 100M Large-Signal Pulse Response GDIFF = 5V/V (±5VP) Left Scale GCM = 1V/V RL = 100W 6.0 -3 -15 -18 10M 7.5 0 -2.0 10 8 6 +IQ 4 -IQ 2 0 Time (10ns/div) 0 1 2 3 4 5 6 RADJ (kW) Figure 71. Figure 72. RECOMMENDED RS vs CAPACITIVE LOAD FREQUENCY RESPONSE vs CAPACITIVE LOAD 20 100 RS Optimized for 100% Bias 17 100pF Gain (dB) RS (W) 14 10 22pF 470pF RS THS6214 11 39pF 8 CL VIN 1kW VOUT Optional 47pF RS 5 THS6214 1 1 22 100 10 1000 2 10M 100M Capacitive Load (pF) Frequency (Hz) Figure 73. Figure 74. Submit Documentation Feedback 200M Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THS6214 THS6214 www.ti.com ....................................................................................................................................................................................................... SBOS431 – MAY 2009 TYPICAL CHARACTERISTICS: VS = ±6V, Low Bias (continued) At TA = +25°C, GDIFF = +5V/V, GCM = 1V/V, RADJ = 0Ω, RF = 1.82kΩ, and RL = 100Ω, unless otherwise noted. HARMONIC DISTORTION vs FREQUENCY HARMONIC DISTORTION vs OUTPUT VOLTAGE -60 GDIFF = 5V/V GCM = 1V/V VO = 2VPP RL = 100W -50 -60 Harmonic Distortion (dBc) Harmonic Distortion (dBc) -40 -70 Third Harmonic -80 Second Harmonic -90 -100 100k -70 Third Harmonic -80 Second Harmonic -90 -100 1M 10M 100M 0 4 2 6 8 10 Frequency (Hz) Output Voltage (VPP) Figure 75. Figure 76. HARMONIC DISTORTION vs SUPPLY VOLTAGE 12 14 16 HARMONIC DISTORTION vs LOAD RESISTANCE -80 -80 -85 Third Harmonic -90 Second Harmonic -95 GDIFF = 5V/V GCM = 1V/V VO = 2VPP RL = 100W f = 1MHz -100 4 5 6 7 8 9 10 11 Harmonic Distortion (dBc) Harmonic Distortion (dBc) GDIFF = 5V/V GCM = 1V/V RL = 100W f = 1MHz -85 Second Harmonic -90 -95 -100 GDIFF = 5V/V GCM = 1V/V VO = 2VPP f = 1MHz -105 -110 12 50 Third Harmonic 100 1k Resistance (W) Supply Voltage (±VS) Figure 77. Figure 78. HARMONIC DISTORTION vs NONINVERTING GAIN TWO-TONE, THIRD-ORDER INTERMODULATION INTERCEPT 60 -80 -85 Third Harmonic -90 -95 Second Harmonic GDIFF = 5V/V GCM = 1V/V VO = 2VPP RL = 100W f = 1MHz -100 Intercept Point (dBm) Harmonic Distortion (dBc) 55 50 45 40 35 30 25 20 1 10 20 0 Gain (V/V) 5 10 15 20 25 30 Frequency (MHz) Figure 79. Figure 80. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THS6214 23 THS6214 SBOS431 – MAY 2009 ....................................................................................................................................................................................................... www.ti.com APPLICATION INFORMATION WIDEBAND CURRENT-FEEDBACK OPERATION The THS6214 provides the exceptional ac performance of a wideband current-feedback op amp with a highly linear, high-power output stage. Requiring only 21mA/port quiescent current, the THS6214 swings to within 1.9V of either supply rail on a 100Ω load and delivers in excess of 416mA at room temperature. This low-output headroom requirement, along with supply voltage independent biasing, provides remarkable ±6V supply operation. The THS6214 delivers greater than 140MHz bandwidth driving a 2VPP output into 100Ω on a ±6V supply. Previous boosted output stage amplifiers typically suffer from very poor crossover distortion as the output current goes through zero. The THS6214 achieves a comparable power gain with much better linearity. The primary advantage of a current-feedback op amp over a voltage-feedback op amp is that ac performance (bandwidth and distortion) is relatively independent of signal gain. Figure 81 shows the dc-coupled, gain of +10V/V, dual power-supply circuit configuration used as the basis of the ±12V Electrical and Typical Characteristics. For test purposes, the input impedance is set to 50Ω with a resistor to ground and the output impedance is set to 50Ω with a series output resistor. Voltage swings reported in the Electrical Characteristics are taken directly at the input and output pins, whereas load powers (dBm) are defined at a matched 50Ω load. For the circuit of Figure 81, the total effective load is 100Ω || 1.24kΩ || 1.24kΩ = 86.1Ω. +12V 1/2 THS6214 RF 1.24kW VIN RG 274W RF 1.24kW This approach allows the user to set a source termination impedance at the input that is independent of the signal gain. For instance, simple differential filters may be included in the signal path right up to the noninverting inputs with no interaction with the gain setting. The differential signal gain for the circuit of Figure 81 is: RF AD = 1 + 2 ´ RG (1) Where AD = differential gain. Figure 81 shows a value of 274Ω for the AD = +10V/V design. Because the THS6214 is a current feedback (CFB) amplifier, its bandwidth is primarily controlled with the feedback resistor value; the differential gain, however, may be adjusted with considerable freedom using just the RG resistor. In fact, RG may be reduced by a reactive network that provides a very isolated shaping to the differential frequency response. Various combinations of single-supply or ac-coupled gain can also be delivered using the basic circuit of Figure 81. Common-mode bias voltages on the two noninverting inputs pass on to the output with a gain of +1V/V because an equal dc voltage at each inverting node creates no current through RG. This circuit does show a common-mode gain of +1V/V from input to output. The source connection should either remove this common-mode signal if undesired (using an input transformer can provide this function), or the common-mode voltage at the inputs can be used to set the output common-mode bias. If the low common-mode rejection of this circuit is a problem, the output interface can also be used to reject that common-mode. For instance, most modern differential input analog-to-digital converters (ADCs) reject common-mode signals very well, while a line driver application through a transformer also attenuates the common-mode signal through to the line. VOUT RL 1/2 THS6214 GDIFF = 1 + -12V 2 ´ RF RG = VOUT VIN Figure 81. Noninverting Differential I/O Amplifier 24 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THS6214 THS6214 www.ti.com ....................................................................................................................................................................................................... SBOS431 – MAY 2009 DUAL-SUPPLY VDSL DOWNSTREAM Figure 82 shows an example of a dual-supply VDSL downstream driver. Both channels of the THS6214 are configured as a differential gain stage to provide signal drive to the primary winding of the transformer (in Figure 82, a step-up transformer with a turns ratio of 1:1.1). The main advantage of this configuration is the cancellation of all even harmonic-distortion products. Another important advantage for VDSL is that each amplifier must only swing half of the total output required driving the load. LINE DRIVER HEADROOM MODEL +12V The first step in a transformer-coupled, twisted-pair driver design is to compute the peak-to-peak output voltage from the target specifications. This calculation is done using the following equations: VRMS2 PL = 10 ´ log (1mW) ´ RL (4) 20W 1/4 THS6214 RF 2.2kW 0.1mF AFE 2VPP Max Assumed RG 1.4kW 2kW 0.1mF IP = 159mA RS 10W 1:1.1 RP 2.9kW 2kW ZLINE RP 2.9kW RF 2.2kW The two back-termination resistors (RS = 10Ω each) added at each terminal of the transformer make the impedance of the modem match the impedance of the phone line, and also provide a means of detecting the received signal for the receiver. The value of these resistors (RM) is a function of the line impedance and the transformer turns ratio (n), given by the following equation: ZLINE RM = 2n2 (3) with: • • • RL 100W RS 10W PL = power at the load VRMS = voltage at the load RL = load impedance These values produce the following: 20W 1/4 THS6214 IP = 159mA VRMS = -12V (1mW) ´ RL ´ 10 PL 10 (5) VP = CrestFactor ´ VRMS = CF ´ VRMS Figure 82. Dual-Supply VDSL Downstream Driver The analog front-end (AFE) signal is ac-coupled to the driver, and the noninverting input of each amplifier is biased to the mid-supply voltage (ground in this case). In addition to providing the proper biasing to the amplifier, this approach also provides a high-pass filtering with a corner frequency, set here at 5kHz. Because the signal bandwidth starts at 26kHz, this high-pass filter does not generate any problem and has the advantage of filtering out unwanted lower frequencies. The input signal is amplified with a gain set by the following equation: 2 ´ RF GD = 1 + RG (2) With RF = 2.2kΩ and RG = 1.4kΩ, the gain for this differential amplifier is RP = 2.9kΩ. This gain boosts the AFE signal, assumed to be a maximum of 2VPP, to a maximum of 3VPP. (6) with: • • VP = peak voltage at the load CF = Crest Factor VLPP = 2 ´ CF ´ VRMS (7) with VLPP = peak-to-peak voltage at the load. Consolidating Equation 4 through Equation 7 allows us to express the required peak-to-peak voltage at the load as a function of the crest factor, the load impedance, and the power at the load. Thus: VLPP = 2 ´ CF ´ (1mW) ´ RL ´ 10 PL 10 (8) VLPP is usually computed for a nominal line impedance and may be taken as a fixed design target. The next step in the design is to compute the individual amplifier output voltage and currents as a function of peak-to-peak voltage on the line and transformer turns ratio. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THS6214 25 THS6214 SBOS431 – MAY 2009 ....................................................................................................................................................................................................... www.ti.com As this turns ratio changes, the minimum allowed supply voltage changes along with it. The peak current in the amplifier output is given by: 2 ´ VLPP 1 1 ±IP = ´ ´ n 2 4RM (9) V1, V2, R1, and R2 are given in Table 2 for ±12V operation. Table 2. Line Driver Headroom Model Values ±12V with VPP as defined in Equation 8, and RM as defined in Equation 3 and shown in Figure 83. RM VPP = 2VLPP n VLPP n RL VLPP V1 R1 V2 R2 1V 0.6Ω 1V 1.2Ω When using a synthetic output impedance circuit (see Figure 82), a significant drop is noticed in bandwidth from the specification that appears in the Electrical Characteristics tables. This apparent drop in bandwidth for the differential signal is a result of the apparent increase in the feedback transimpedance as seen for each amplifier. This feedback transimpedance equation is given below. RM 1+2´ ZFB = RF ´ RS 1+2´ Figure 83. Driver Peak Output Voltage With the previous information available, it is now possible to select a supply voltage and the turns ratio desired for the transformer, as well as calculate the headroom for the THS6214. RS + + RS RP RL RS RP RL RF - RP (12) To increase 0.1dB flatness to the frequency of interest, adding a serial RC in parallel with the gain resistor may be needed, as shown in Figure 85. RS 1/4 THS6214 The model, shown in Figure 84, can be described with the following set of equations: 1. As the available output swing: VPP = VCC - (V1 + V2) - IP ´ (R1 + R2) (10) RF RP RM 2. Or as the required supply voltage: VCC = VPP + (V1 + V2) + IP ´ (R1 + R2) ZLINE (11) VIN The minimum supply voltage for power and load requirements is given by Equation 11. RG RP 100W CM RF +VCC 1/4 THS6214 RS R1 V1 Figure 85. +0.1dB Flatness Compensation Circuit VOUT IP V2 R2 Figure 84. Line Driver Headroom Model 26 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THS6214 THS6214 www.ti.com ....................................................................................................................................................................................................... SBOS431 – MAY 2009 TOTAL DRIVER POWER FOR xDSL APPLICATIONS The total internal power dissipation for the THS6214 in an xDSL line driver application is the sum of the quiescent power and the output stage power. The THS6214 holds a relatively constant quiescent current versus supply voltage—giving a power contribution that is simply the quiescent current times the supply voltage used (the supply voltage is greater than the solution given in Equation 11). The total output stage power can be computed with reference to Figure 86. +VCC IAVG = IP CF RT Figure 86. Output Stage Power Model The two output stages used to drive the load of Figure 83 can be seen as an H-Bridge in Figure 86. The average current drawn from the supply into this H-Bridge and load is the peak current in the load given by Equation 9 divided by the crest factor (CF) for the xDSL modulation. This total power from the supply is then reduced by the power in RT, leaving the power dissipated internal to the drivers in the four output stage transistors. That power is simply the target line power used in Equation 4 plus the power lost in the matching elements (RM). In the following examples, a perfect match is targeted giving the same power in the matching elements as in the load. The output stage power is then set by Equation 13. IP POUT = ´ VCC - 2PL CF (13) The total amplifier power is then: IP PTOT = IQ ´ VCC + ´ VCC - 2PL CF (14) For the ADSL CO driver design of Figure 82, the peak current is 159mA for a signal that requires a crest factor of 5.6 with a target line power of 20.5dBm into a 100Ω load (115mW). With a typical quiescent current of 21mA and a nominal supply voltage of ±12V, the total internal power dissipation for the solution of Figure 82 is: PTOT = 21mA (24V) + 159mA (24V) - 2(115mW) = 955mW 5.6 (15) OUTPUT CURRENT AND VOLTAGE The THS6214 provides output voltage and current capabilities that are unsurpassed in a low-cost, dual monolithic op amp. Under no-load conditions at +25°C, the output voltage typically swings closer than 1.1V to either supply rail; tested at +25°C, the swing limit is within 1.4V of either rail into a 100Ω differential load. Into a 25Ω load (the minimum tested load), the amplifier delivers more than ±408mA continuous and greater than ±1A peak output current. The specifications described above, though familiar in the industry, consider voltage and current limits separately. In many applications, it is the voltage times current (or V-I product) that is more relevant to circuit operation. Refer to the Output Voltage and Current Limitations plot (Figure 14) in the Typical Characteristics. The X- and Y-axes of this graph show the zero-voltage output current limit and the zero-current output voltage limit, respectively. The four quadrants give a more detailed view of the THS6214 output drive capabilities, noting that the graph is bounded by a safe operating area of 1W maximum internal power dissipation (in this case, for one channel only). Superimposing resistor load lines onto the plot shows that the THS6214 can drive ±10.9V into 100Ω or ±10.5V into 50Ω without exceeding the output capabilities or the 1W dissipation limit. A 100Ω load line (the standard test circuit load) shows the full ±12V output swing capability, as shown in the Electrical Characteristics tables. The minimum specified output voltage and current over temperature are set by worst-case simulations at the cold temperature extreme. Only at cold startup do the output current and voltage decrease to the numbers shown in the Electrical Characteristics tables. As the output transistors deliver power, the junction temperature increases, decreasing the VBEs (increasing the available output voltage swing), and increasing the current gains (increasing the available output current). In steady-state operation, the available output voltage and current are always greater than that shown in the over-temperature specifications, because the output stage junction temperatures are higher than the minimum specified operating ambient temperature. To maintain maximum output stage linearity, no output short-circuit protection is provided. This absence of short-circuit protection is normally not a problem because most applications include a series-matching resistor at the output that limits the internal power dissipation if the output side of this Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THS6214 27 THS6214 SBOS431 – MAY 2009 ....................................................................................................................................................................................................... www.ti.com resistor is shorted to ground. However, shorting the output pin directly to the adjacent positive power-supply pin (24-pin package), in most cases, destroys the amplifier. If additional short-circuit protection is required, a small series resistor may be included in the supply lines. Under heavy output loads, this additional resistor reduces the available output voltage swing. A 5Ω series resistor in each power-supply lead limits the internal power dissipation to less than 1W for an output short-circuit, while decreasing the available output voltage swing only 0.5V for up to 100mA desired load currents. Always place the 0.1µF power-supply decoupling capacitors after these supply current limiting resistors, directly on the supply pins. DRIVING CAPACITIVE LOADS One of the most demanding and yet very common load conditions for an op amp is capacitive loading. Often, the capacitive load is the input of an ADC—including additional external capacitance that may be recommended to improve the ADC linearity. A high-speed, high open-loop gain amplifier such as the THS6214 can be very susceptible to decreased stability and closed-loop response peaking when a capacitive load is placed directly on the output pin. When the amplifier open-loop output resistance is considered, this capacitive load introduces an additional pole in the signal path that can decrease the phase margin. Several external solutions to this problem have been suggested. When the primary considerations are frequency response flatness, pulse response fidelity, and/or distortion, the simplest and most effective solution is to isolate the capacitive load from the feedback loop by inserting a series isolation resistor between the amplifier output and the capacitive load. This series resistor does not eliminate the pole from the loop response, but shifts it and adds a zero at a higher frequency. The additional zero acts to cancel the phase lag from the capacitive load pole, thus increasing the phase margin and improving stability. The Typical Characteristics show the recommended RS vs Capacitive Load (see Figure 6, Figure 24, Figure 36, Figure 48, Figure 61, and Figure 73) and the resulting frequency response at the load. Parasitic 28 capacitive loads greater than 2pF can begin to degrade device performance. Long printed-circuit board (PCB) traces, unmatched cables, and connections to multiple devices can easily cause this value to be exceeded. Always consider this effect carefully, and add the recommended series resistor as close as possible to the THS6214 output pin (see the Board Layout Guidelines section). DISTORTION PERFORMANCE The THS6214 provides good distortion performance into a 100Ω load on ±12V supplies. Relative to alternative solutions, the amplifier provides exceptional performance into lighter loads and/or operation on a dual ±6V supply. Generally, until the fundamental signal reaches very high frequency or power levels, the second harmonic dominates the distortion with a negligible third-harmonic component. Focusing then on the second harmonic, increasing the load impedance improves distortion directly. Remember that the total load includes the feedback network—in the noninverting configuration (see Figure 81), this value is the sum of RF + RG, whereas in the inverting configuration it is just RF. Also, providing an additional supply decoupling capacitor (0.01µF) between the supply pins (for bipolar operation) improves the second-order distortion slightly (from 3dB to 6dB). In most op amps, increasing the output voltage swing directly increases harmonic distortion. The Typical Characteristics show the second harmonic increasing at a little less than the expected 2x rate, whereas the third harmonic increases at a little less than the expected 3x rate. Where the test power doubles, the difference between it and the second harmonic decreases less than the expected 6dB, whereas the difference between it and the third harmonic decreases by less than the expected 12dB. This difference also shows up in the two-tone, third-order intermodulation spurious (IM3) response curves. The third-order spurious levels are extremely low at low-output power levels. The output stage continues to hold them low even as the fundamental power reaches very high levels. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THS6214 THS6214 www.ti.com ....................................................................................................................................................................................................... SBOS431 – MAY 2009 DIFFERENTIAL NOISE PERFORMANCE The THS6214 is designed to be used as a differential driver in xDSL applications. Therefore, it is important to analyze the noise in such a configuration. Figure 87 shows the op amp noise model for the differential configuration. GD 2 +2 4kTRF GD EN In order to minimize the output noise as a result of the noninverting input bias current noise, it is recommended to keep the noninverting source impedance as low as possible. RF 4kTRF RG DC ACCURACY AND OFFSET CONTROL 2 EO 4kTRG RF 4kTRF IN EN IN ERS 4kTRS Figure 87. Differential Op Amp Noise Analysis Model As a reminder, the differential gain is expressed as: 2 ´ RF GD = 1 + RG (16) The output noise can be expressed as shown below: 2 iIRF 2 Evaluating these equations for the THS6214 ADSL circuit and component values of Figure 82 gives a total output spot noise voltage of 38.9nV/√Hz and a total equivalent input spot noise voltage of 7nV/√Hz. 4kTRS EO = 2 2 ´ eN + (iN ´ RS) + 4kTRS + 2 (18) IN RS EO = IN RS ERS Dividing this expression by the differential noise gain (GD = (1 + 2RF/RG)) gives the equivalent input referred spot noise voltage at the noninverting input, as shown in Equation 18. 2 2 2 ´ GD2 ´ eN + (iN ´ RS) + 4kTRS + 2(iIRF) + 2(4kTRFGD) (17) A current-feedback op amp such as the THS6214 provides exceptional bandwidth in high gains, giving fast pulse settling but only moderate dc accuracy. The Electrical Characteristics show an input offset voltage comparable to high-speed, voltage-feedback amplifiers; however, the two input bias currents are somewhat higher and are unmatched. While bias current cancellation techniques are very effective with most voltage-feedback op amps, they do not generally reduce the output dc offset for wideband current-feedback op amps. Because the two input bias currents are unrelated in both magnitude and polarity, matching the input source impedance to reduce error contribution to the output is ineffective. Evaluating the configuration of Figure 81, using a worst-case condition at +25°C input offset voltage and the two input bias currents, gives a worst-case output offset range equal to: VOFF = ±(NG × VOS(MAX)) + (IBN × RS/2 × NG) ±(IBI × RF) where NG = noninverting signal gain = ±(10 × 5mV) ±(1.24kΩ × 45µA) + (3.5µA × 25Ω × 10) = ±50mV + 0.875mV ± 55.8mV VOFF = –104.92mV to +106.67mV Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THS6214 29 THS6214 SBOS431 – MAY 2009 ....................................................................................................................................................................................................... www.ti.com BOARD LAYOUT GUIDELINES Achieving optimum performance with a high-frequency amplifier such as the THS6214 requires careful attention to board layout parasitic and external component types. Recommendations that optimize performance include: a) Minimize parasitic capacitance to any ac ground for all of the signal I/O pins. Parasitic capacitance on the output and inverting input pins can cause instability; on the noninverting input, it can react with the source impedance to cause unintentional band limiting. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes should be unbroken elsewhere on the board. b) Minimize the distance (less than 0.25in, or 6,35mm) from the power-supply pins to high-frequency 0.1µF decoupling capacitors. At the device pins, the ground and power plane layout should not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The power-supply connections should always be decoupled with these capacitors. An optional supply decoupling capacitor across the two power supplies (for bipolar operation) improves second-harmonic distortion performance. Larger (2.2µF to 6.8µF) decoupling capacitors, effective at lower frequencies, should also be used on the main supply pins. These capacitors can be placed somewhat farther from the device and may be shared among several devices in the same area of the PCB. c) Careful selection and placement of external components preserve the high-frequency performance of the THS6214. Resistors should be a very low reactance type. Surface-mount resistors work best and allow a tighter overall layout. Metal film and carbon composition, axially-leaded resistors can also provide good high-frequency performance. Again, keep leads and PCB trace length as short as possible. Never use wire-wound type resistors in a high-frequency application. Although the output pin and inverting input pin are the most sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as close as possible to the output pin. Other network components, such as noninverting input termination resistors, should also be placed close to the package. Where double-side component mounting is allowed, place the feedback resistor directly under the package on the other side of the board between the output and inverting input pins. The frequency response is primarily determined by the feedback resistor value as described previously. Increasing the value reduces the bandwidth, whereas decreasing it leads to a more 30 peaked frequency response. The 1.24kΩ feedback resistor used in the Typical Characteristics at a gain of +10V/V on ±12V supplies is a good starting point for design. Note that a 1.5kΩ feedback resistor, rather than a direct short, is recommended for a unity-gain follower application. A current-feedback op amp requires a feedback resistor to control stability even in the unity-gain follower configuration. d) Connections to other wideband devices on the board may be made with short direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50mils to 100mils [.050in to .100in, or 1,27mm to 2,54mm]) should be used, preferably with ground and power planes opened up around them. Estimate the total capacitive load and set RS from the plot of Recommended RS vs Capacitive Load (see Figure 6, Figure 24, Figure 36, Figure 48, Figure 61, and Figure 73). Low parasitic capacitive loads (less than 5pF) may not need an isolation resistor because the THS6214 is nominally compensated to operate with a 2pF parasitic load. If a long trace is required, and the 6dB signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement a matched-impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50Ω environment is not necessary on board; in fact, a higher impedance environment improves distortion (see the distortion versus load plots). With a characteristic board trace impedance defined based on board material and trace dimensions, a matching series resistor into the trace from the output of the THS6214 is used, as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance is the parallel combination of the shunt resistor and the input impedance of the destination device. This total effective impedance should be set to match the trace impedance. The high output voltage and current capability of the THS6214 allows multiple destination devices to be handled as separate transmission lines, each with their own series and shunt terminations. If the 6dB attenuation of a doubly-terminated transmission line is unacceptable, a long trace can be series-terminated at the source end only. Treat the trace as a capacitive load in this case and set the series resistor value as shown in the plot of RS vs Capacitive Load. However, this configuration does not preserve signal integrity as well as a doubly-terminated line. If the input impedance of the destination device is low, there is some signal attenuation as a result of the voltage divider formed by the series output into the terminating impedance. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THS6214 THS6214 www.ti.com ....................................................................................................................................................................................................... SBOS431 – MAY 2009 e) Socketing a high-speed part such as the THS6214 is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network, which can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering the THS6214 directly onto the board. f) Use the –VS plane to conduct heat out of the QFN-24 and TSSOP-24 PowerPAD packages. These packages attach the die directly to an exposed thermal pad on the bottom, which should be soldered to the board. This pad must be connected electrically to the same voltage plane as the most negative supply applied to the THS6214 (in Figure 82, this supply is –12V). Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THS6214 31 PACKAGE OPTION ADDENDUM www.ti.com 29-Jun-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty THS6214IPWP ACTIVE HTSSOP PWP 24 THS6214IPWPR ACTIVE HTSSOP PWP THS6214IRHFR ACTIVE QFN THS6214IRHFT ACTIVE QFN 60 Lead/Ball Finish MSL Peak Temp (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR RHF 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR RHF 24 250 CU NIPDAU Level-2-260C-1 YEAR Green (RoHS & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 25-Jun-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) THS6214IPWPR HTSSOP PWP 24 2000 330.0 THS6214IRHFR QFN RHF 24 3000 THS6214IRHFT QFN RHF 24 250 16.4 6.95 8.3 1.6 8.0 16.0 Q1 330.0 12.4 4.3 5.3 1.3 8.0 12.0 Q1 180.0 12.4 4.3 5.3 1.3 8.0 12.0 Q1 Pack Materials-Page 1 W Pin1 (mm) Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 25-Jun-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) THS6214IPWPR HTSSOP PWP 24 2000 346.0 346.0 33.0 THS6214IRHFR QFN RHF 24 3000 346.0 346.0 29.0 THS6214IRHFT QFN RHF 24 250 190.5 212.7 31.8 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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