DG540/541/542 Vishay Siliconix Wideband/Video “T” Switches Wide Bandwidth: 500 MHz Low Crosstalk: –85 dB High Off-Isolation: –80 dB @ 5 MHz “T” Switch Configuration TTL and CMOS Logic Compatible Fast Switching—tON: 45 ns Low rDS(on): 30 Flat Frequency Response High Color Fidelity Low Insertion Loss Improved System Performance Reduced Board Space Reduced Power Consumption Improved Data Throughput RF and Video Switching RGB Switching Local and Wide Area Networks Video Routing Fast Data Acquisition ATE Radar/FLR Systems Video Multiplexing To achieve TTL compatibility, low channel capacitances and fast switching times, the DG540 family is built on the Vishay Siliconix proprietary D/CMOS process. Each switch conducts equally well in both directions when on. The DG540/541/542 are high performance monolithic wideband/video switches designed for switching RF, video and digital signals. By utilizing a “T” switch configuration on each channel, these devices achieve exceptionally low crosstalk and high off-isolation. The crosstalk and off-isolation of the DG540 are further improved by the introduction of extra GND pins between signal pins. DG540 DG540 Dual-In-Line 18 GND S1 4 17 S2 V– 5 16 V+ GND 6 15 GND S4 7 14 S3 GND 8 13 GND D4 9 12 D3 IN4 10 11 IN3 2 1 20 19 D2 3 IN 2 GND 3 S1 4 18 GND V– 5 17 S2 Logic Switch GND 6 16 V+ 0 OFF S4 7 15 GND 1 ON GND 8 14 S3 9 10 11 12 13 Logic “0” 0.8 V Logic “1” 1 2V GND D2 IN 1 19 D3 2 IN3 D1 GND IN2 D4 20 IN4 1 D1 PLCC IN1 Top View Top View Document Number: 70055 S-00399—Rev. G, 13-Sep-99 www.vishay.com FaxBack 408-970-5600 4-1 DG540/541/542 Vishay Siliconix FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION DG541 DG542 Dual-In-Line and SOIC Dual-In-Line and SOIC IN1 1 16 IN2 IN1 1 16 IN2 D1 2 15 D2 D1 2 15 D2 S1 3 14 S2 GND 3 14 GND V– 4 13 V+ S1 4 13 S2 GND 5 12 GND V– 5 12 V+ S4 6 11 S3 S4 6 11 S3 D4 7 10 D3 GND 7 10 GND IN4 8 9 IN3 D4 8 9 D3 Top View Top View TRUTH TABLE - DG541 TRUTH TABLE - DG542 Logic Switch Logic SW1, SW2 SW3, SW4 0 OFF 0 OFF ON ON 1 ON OFF 1 Logic “0” 0.8 V Logic “1” 2 V Logic “0” 0.8 V Logic “1” 2 V ORDERING INFORMATION Temp Range Package Part Number DG540 –40 to 85_C –55 to 125_C 20-Pin Plastic DIP DG540DJ 20-Pin PLCC DG540DN 20-Pin Sidebraze DG540AP DG540AP/883 DG541 –40 to 85_C 16-Pin Plastic DIP DG541DJ 16-Pin Narrow SOIC DG541DY DG541AP –55 to 125_C 16-Pin Sidebraze DG541AP/883, 5962-9076401MEA DG542 –40 to 85_C –55 to 125_C www.vishay.com S FaxBack 408-970-5600 4-2 16-Pin Plastic DIP DG542DJ 16-Pin Narrow SOIC DG542DY 16-Pin Sidebraze DG542AP DG542AP/883, 5962-91555201MEA Document Number: 70055 S-00399—Rev. G, 13-Sep-99 DG540/541/542 Vishay Siliconix V+ to V– . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 21 V V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 21 V V– to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –19 V to +0.3 V Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V–) –0.3 V to (V+) +0.3 V or 20 mA, whichever occurs first VS, VD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V–) –0.3 V to (V–) +14 V or 20 mA, whichever occurs first Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Current, S or D (Pulsed 1 ms, 10% duty cycle max) . . . . . . . . . . . . . . 40 mA Storage Temperature (AP Suffix) . . . . . . . . . . . . . . . . . . –65 to 150_C (DJ, DN, DY Suffixes) . . . . . . . . –65 to 125_C Power Dissipation (Package)a 16-Pin Plastic DIPb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-Pin Plastic DIPc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-Pin Narrow Body SOICd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-Pin PLCCd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-, 20-Pin Sidebraze DIPe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 mW 800 mW 640 mW 800 mW 900 mW Notes: a. All leads welded or soldered to PC Board. b. Derate 6.5 mW/_C above 25_C c. Derate 7 mW/_C above 25_C d. Derate 10 mW/_C above 75_C e. Derate 12 mW/_C above 75_C V+ GND VREF S IN – + D V– FIGURE 1. Document Number: 70055 S-00399—Rev. G, 13-Sep-99 www.vishay.com S FaxBack 408-970-5600 4-3 DG540/541/542 Vishay Siliconix Test Conditions Unless Specified Parameter Symbol V+ = 15 V, V– = –3 V VINH = 2 V, VINL = 0.8 Vf Tempb VANALOG V– = –5 V, V+ = 12 V Full Typc A Suffix D Suffixes –55 to 125_C –40 to 85_C Mind Maxd Mind Maxd Unit Analog Switch Analog Signal Range Drain-Source On-Resistance rDS(on) IS = –10 mA,, VD = 0 V DrDS(on) rDS(on) Match –5 5 –5 5 Room Full 30 60 100 60 75 Room 2 6 6 Source Off Leakage Current IS(off) VS = 0 V, VD = 10 V Room Full –0.05 –10 –500 10 500 –10 –100 10 100 Drain Off Leakage Current ID(off) VS = 10 V, VD = 0 V Room Full –0.05 –10 –500 10 500 –10 –100 10 100 Channel On Leakage Current ID(on) VS = VD = 0 V Room Full –0.05 –10 –1000 10 1000 –10 –100 10 100 V W nA A Digital Control Input Voltage High VINH Full Input Voltage Low VINL Full 2 2 V 0.8 IIN VIN = GND or V+ Room Full 0.05 On State Input Capacitancee CS(on) VS = VD = 0 V Room 14 20 20 Off State Input Capacitancee CS(off) VS = 0 V Room 2 4 4 CD(off) VD = 0 V Room 2 4 4 BW RL = 50 W , See Figure 5 Room 500 DG540 DG541 Room Full 45 70 130 70 130 DG542 Room Full 55 100 160 100 160 DG540 DG541 Room Full 20 50 85 50 85 DG542 Room Full 25 60 85 60 85 Room –25 DG540 Room –80 DG541 Room –60 DG542 Room –75 Room –85 Room Full 3.5 Room Full –3.2 Input Current –1 –20 0.8 1 20 –1 –20 1 20 mA Dynamic Characteristics Off State Output Capacitancee Bandwidth Turn On Time tON RL = 1 kW CL = 35 p pF 50% to t 90% See Figure 2 Turn Off Time Charge Injection Off Isolation I l i All Hostile Crosstalk OIRR XTALK(AH) CL = 1000 pF, VS = 0 V See Figure 3 RIN = 75 W RL = 75 W f = 5 MHz See Figure 4 RIN = 10 W , RL = 75 W f = 5 MHz, See Figure 6 MHz ns tOFF Q pF F pC dB Power Supplies Positive Supply Current I+ Negative Supply Current I– 6 9 6 9 All Channels On or Off mA –6 –9 –6 –9 Notes: a. Refer to PROCESS OPTION FLOWCHART. b. Room = 25_C, Full = as determined by the operating temperature suffix. c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. e. Guaranteed by design, not subject to production test. f. VIN = input voltage to perform proper function. www.vishay.com S FaxBack 408-970-5600 4-4 Document Number: 70055 S-00399—Rev. G, 13-Sep-99 DG540/541/542 Vishay Siliconix _ Supply Curent vs. Temperature 6 ID(off), IS(off) vs. Temperature 100 nA 5 10 nA 4 I+ I S(off), I D(off)– Leakage 3 I (mA) 2 1 IGND 0 –1 –2 I– –3 1 nA 100 pA 10 pA 1 pA –4 0.1 pA –5 –55 –35 –15 5 25 45 65 Temperature (_C) 85 105 125 –55 rDS(on) vs. Drain Voltage 25 50 75 Temperature (_C) V+ Constant 120 125_C 100 80 25_C 60 –55_C 40 20 42 40 40 38 38 V– = –5 V 36 36 V+ = 12 V 34 34 32 32 V– = –3 V V+ = 15 V 30 30 20 20 –1 1 3 5 7 9 11 –5 VD – Drain Voltage (V) V– = –1 V 18 18 0 –3 –4 –3 –2 –1 0 10 11 12 13 14 15 16 V– – Negative Supply (V) On Capacitance V+ – Positive Supply (V) Off Isolation 22 –110 20 –100 RL = 75 –90 18 –80 ISO (dB) 16 C (pF) 125 V+ = 10 V r DS(on)– Drain-Source On-Resistance ( ) V+ = 15 V V– = –3 V 140 100 V– Constant 42 160 r DS(on)– Drain-Source On-Resistance ( ) 0 –25 14 DG540 –70 DG542 –60 –50 12 DG541 –40 10 –30 8 –20 –10 6 0 2 4 6 8 10 VD – Drain Voltage (V) Document Number: 70055 S-00399—Rev. G, 13-Sep-99 12 14 1 10 100 f – Frequency (MHz) www.vishay.com S FaxBack 408-970-5600 4-5 DG540/541/542 Vishay Siliconix _ Off Isolation vs. Frequency and Load Resistance (DG540) All Hostile Crosstalk –100 –110 –90 –100 RL = 75 –80 –80 1 k X TALK (dB) OIRR (dB) –70 –60 DG540 –90 180 10 k –50 –40 DG542 –70 –60 DG541 –50 –30 –40 –20 –30 –10 –20 –10 0 1 10 40 10 1 100 100 f – Frequency (MHz) f – Frequency (MHz) Charge Injection vs. VS Switching Times vs. Temperature (DG540/541) 90 80 30 70 20 60 Time (ns) Q (pC) 10 0 tON 50 40 –10 30 –20 tOFF 20 CL = 1000 pF –30 10 0 –40 –3 –2 –1 0 1 2 3 4 5 6 7 8 –55 –25 0 25 VS – Source Voltage (V) 50 75 100 125 Temperature (_C) Switching and Break-Before-Make Time vs. Temperature (DG542) Operating Supply Voltage Range 20 90 80 18 V+ – Positive Supply (V) tON 70 Time (ns) 60 tBBM 50 40 tOFF 30 20 16 Operating Voltage Area 14 12 10 0 10 –55 –25 0 25 50 Temperature (_C) www.vishay.com S FaxBack 408-970-5600 4-6 75 100 125 0 –1 –2 –3 –4 –5 –6 V– – Negative Supply (V) Document Number: 70055 S-00399—Rev. G, 13-Sep-99 DG540/541/542 Vishay Siliconix +15 V 3V tr <20 ns tf <20 ns 3V V+ D S VO IN CL 35 pF RL 1 kW V– GND Logic Input Switch Input 50% VS 90% Switch Output 0 –3 V tON tOFF CL (includes fixture and stray capacitance) RL VO = VS RL + rDS(on) FIGURE 2. Switching Time DVO +15 V Rg V+ VO D S VO IN Vg CL 1000 pF 3V INX V– GND ON OFF ON DVO = measured voltage error due to charge injection The charge injection in coulombs is DQ = CL x DVO –3 V FIGURE 3. Charge Injection +15 V +15 V C C V+ S VS VO D Rg = 75 W 0 V, 2.4 V RL 75 W IN GND V– –3 V Off Isolation = 20 log C V+ S VS VO D Rg = 50 W 0 V, 2.4 V RL 50 W IN GND V– C –3 V VS VO C = RF Bypass FIGURE 4. Off Isolation Document Number: 70055 S-00399—Rev. G, 13-Sep-99 FIGURE 5. Bandwidth www.vishay.com FaxBack 408-970-5600 4-7 DG540/541/542 Vishay Siliconix C +15 V V+ S1 10 W 2.4 V D1 VO RL 75 W INX S2 D2 S3 D3 S4 D4 GND V– RL RL RL C –15 V VOUT XTALK(AH) 20 log10 V IN FIGURE 6. All Hostile Crosstalk Device Description The DG540/541/542 family of wideband switches offers true bidirectional switching of high frequency analog or digital signals with minimum signal crosstalk, low insertion loss, and negligible non-linearity distortion and group delay. Built on the Siliconix D/CMOS process, these “T” switches provide excellent off-isolation with a bandwidth of around 500 MHz (350 MHz for DG541). Silicon-gate D/CMOS processing also yields fast switching speeds. An on-chip regulator circuit maintains TTL input compatibility over the whole operating supply voltage range, easing control logic interfacing. Circuit layout is facilitated by the interchangeability of source and drain terminals. Frequency Response A single switch on-channel exhibits both resistance [rDS(on)] and capacitance [CS(on)]. This RC combination has an www.vishay.com FaxBack 408-970-5600 4-8 attenuation effect on the analog signal – which is frequency dependent (like an RC low-pass filter). The –3-dB bandwidth of the DG540 is typically 500 MHz (into 50 W). This measured figure of 500 MHz illustrates that the switch channel can not be represented by a two stage RC combination. The on capacitance of the channel is distributed along the on-resistance, and hence becomes a more complex multi stage network of R’s and C’s making up the total rDS(on) and CS(on). See Application Note AN502 for more details. Off-Isolation and Crosstalk Off-isolation and crosstalk are affected by the load resistance and parasitic inter-electrode capacitances. Higher off-isolation is achieved with lower values of RL. However, low values of RL increase insertion loss requiring gain adjustments down the line. Stray capacitances, even a fraction of 1 pF, can cause a large crosstalk increase. Good layout and ground shielding techniques can considerably improve your ac circuit performance. Document Number: 70055 S-00399—Rev. G, 13-Sep-99 DG540/541/542 Vishay Siliconix Suitable decoupling capacitors are 1- to 10-mF tantalum bead, plus 10- to 100-nF ceramic. Power Supplies A useful feature of the DG54X family is its power supply flexibility. It can be operated from a single positive supply (V+) if required (V– connected to ground). +15 V Note that the analog signal must not exceed V– by more than –0.3 V to prevent forward biasing the substrate p-n junction. The use of a V– supply has a number of advantages: 1. 2. 3. + C1 It allows flexibility in analog signal handling, i.e., with V– = –5 V and V+ = 12 V; up to 5-V ac signals can be controlled. The value of on capacitance [CS(on)] may be reduced. A property known as ‘the body-effect’ on the DMOS switch devices causes various parametric effects to occur. One of these effects is the reduction in CS(on) for an increasing V body–source. Note, however, that to increase V– normally requires V+ to be reduced (since V+ to V– = 21 V max.). Reduction in V+ causes an increase in rDS(on), hence a compromise has to be achieved. It is also useful to note that optimum video linearity performance (e.g., differential phase and gain) occurs when V– is around –3 V. C2 V+ S1 D1 S2 D2 DG540 S3 D3 S4 D4 GNDs V– C1 = 10 mF Tantalum C2 = 0.1 mF Ceramic V– eliminates the need to bias the analog signal using potential dividers and large coupling capacitors. C1 C2 + –3 V FIGURE 7. Supply Decoupling Decoupling It is an established RF design practice to incorporate sufficient bypass capacitors in the circuit to decouple the power supplies to all active devices in the circuit. The dynamic performance of the DG54X is adversely affected by poor decoupling of power supply pins. Also, of even more significance, since the substrate of the device is connected to the negative supply, adequate decoupling of this pin is essential. Board Layout PCB layout rules for good high frequency performance must be observed to achieve the performance boasted by the DG540. Some tips for minimizing stray effects are: 1. Use extensive ground planes on double sided PCB, separating adjacent signal paths. Multilayer PCB is even better. Decoupling capacitors should be incorporated on all power supply pins (V+, V–). (See Figure 7.) 2. 2. They should be mounted as close as possible to the device pins. Keep signal paths as short as practically possible, with all channel paths of near equal length. 3. 3. Capacitors should have good high frequency characteristics – tantalum bead and/or monolithic ceramic types are adequate. Careful arrangement of ground connections is also very important. Star connected system grounds eliminate signal current flowing through ground path parasitic resistance from coupling between channels. Rules: 1. Document Number: 70055 S-00399—Rev. G, 13-Sep-99 www.vishay.com FaxBack 408-970-5600 4-9 DG540/541/542 Vishay Siliconix Figure 8 shows a 4-channel video multiplexer using a DG540. +15 V V+ CH1 CH2 Si582 75 75 + CH3 A=2 75 CH4 75 – DG540 V– 75 DIS 250 250 –3 V TTL Channel Select FIGURE 8. 4 by 1 Video Multiplexing Using the DG540 Figure 9 shows an RGB selector switch using two DG542s. +15 V V+ R1 75 Red Out R2 75 G1 75 Green Out G2 75 DG542 V– –3 V Si584 +15 V V+ B1 75 Blue Out B2 75 Sync 1 75 Sync Out Sync 2 75 DG542 RGB Source Select V– –3 V FIGURE 9. RGB Selector Using Two DG542s www.vishay.com FaxBack 408-970-5600 4-10 Document Number: 70055 S-00399—Rev. G, 13-Sep-99 Legal Disclaimer Notice Vishay Notice Specifications of the products displayed herein are subject to change without notice. Vishay Intertechnology, Inc., or anyone on its behalf, assumes no responsibility or liability for any errors or inaccuracies. Information contained herein is intended to provide a product description only. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Vishay's terms and conditions of sale for such products, Vishay assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of Vishay products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right. The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications. Customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Vishay for any damages resulting from such improper use or sale. Document Number: 91000 Revision: 08-Apr-05 www.vishay.com 1