HYNIX GMS81024

8-BIT SINGLE CHIP MICROCOMPUTERS
GMS810 SERIES
USER`S MANUAL
• GMS81004
• GMS81008
• GMS81016
• GMS81024
• GMS81032
Revision 3.0
Published by
MCU Application Team in HYUNDAI ELCETRONICS Co., Ltd.
¨Ï HYUNDAI ELECTRONICS Co., Ltd. 1998 All Right Reserved.
Additional information of this manual may be served by HYUNDAI ELECTIONICS Offices in Korea or
Distributors and Representative listed at address directory.
HYUNDAI ELECTIONICS reserves the right to make changes to any Information here in at any time
without notice.
The information, diagrams, and other data in this manual are correct and reliable; however, HYUNDAI
ELECTIONICS Co., Ltd. is in no way responsible for any violations of patents or other rights of the
third party generated by the use of this manual.
Table of Contents
Table of Contents
Chapter 1
Overview
1.1 Features & Pin Assignments . . . . . . . . . . . . . . . . . . . . .
1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Package Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Pin Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 Port Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.6 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . .
1-1
1-2
1-3
1-5
1-6
1-10
Chapter 2
Function Description
2.1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 TCALL Vector Area . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 Zero-Page Peripheral Registers . . . . . . . . . . . . . . . . . . .
2-1
2-6
2-7
2-8
Chapter 3
I/O PORT
3.1 Port R0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Port R1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Port R2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-1
3-2
3-2
Chapter 4
Peripheral Hardware
4.1 Clock Generating Circuit . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-1
4-10
Table of Contents
Chapter 5
Interrupt
5.1 Interrupt Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2 Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . .
5.3 Interrupt Accept Mode . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4 Interrupt Processing Sequence . . . . . . . . . . . . . . . . . . . .
5.5 Software Interrupt . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6 Multiple Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7 Key Scan Input Processing . . . . . . . . . . . . . . . . . . . . . . .
5-1
5-3
5-4
5-7
5-8
5-9
5-11
Chapter 6
Standby Function
6.1 Stop Mode
............................ .....
6.2 Standby Mode Release . . . . . . . . . . . . . . . . . . . . . . . . .
6.3 Release Operation of Standby Mode . . . . . . . . . . . . . . .
6-1
6-3
6-5
Chapter 7
Reset Function
7.1 External RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2 Power On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3 Low Voltage Detection Mode . . . . . . . . . . . . . . . . . . . . .
Appendix
Instruction Set Table
Programmer`s guide
Mask option list
7-1
7-1
7-4
OVERVIEW
1
FUNCTION DESCRIPTION
2
I/O PORT
3
PERIPHERAL HARDWARE
4
INTERRUPT
5
STANDBY FUNCTION
6
RESET FUNCTION
7
APPENDIX A.
8
APPENDIX B.
9
Chapter 1. Overview
CHAPTER 1. OVERVIEW
The GMS810 Series is the high speed and Low voltage operating 8-bit single chip
microcomputers. This MCU contains G8MC core, ROM, RAM, input/output ports and five
multi-function timer/counters.
1.1 FEATURES & PIN ASSIGNMENTS (TOP VIEW)
¡á
¡á
¡á
¡á
¡á
¡á
¡á
¡á
¡á
¡á
¡á
¡á
ROM size . . . . . . . . . . . . . 4,096 Bytes ( GMS81004 ) , 8,192 Bytes (GMS81008 )
. . . . . . . . . . . . . 16,384 Bytes ( GMS81016 ) ,24,576 Bytes(GMS81024 )
. . . . . . . . . . . . . 32,768 Bytes ( GMS81032 )
RAM size . . . . . . . . . . . . .
448 Bytes
Instruction Execution Time . . 1us @Xin=4MHz
Timer
¡Ü
Timer/Counter . . . . . . 8Bit * 2ch , 16Bit * 1ch
¡Ü
Basic Interval Time . . . 8Bit * 1ch
¡Ü
Watch Dog Timer . . . . 6Bit * 1ch
Power On Reset
Power Saving Operation Modes
¡Ü
STOP
8 Interrupt Sources
¡Ü
Nested Interrupt Control is Available
Operating Voltage
¡Ü
2.0~4.0V @2MHz
¡Ü
2.2~4.0V @4MHz
Low Voltage Detection Circuit
Watch dog Timer Auto Start ( During 1Second after Power on Reset )
Package
¡Ü
20SOP/20PDIP/24SOP/24Skinny DIP/28SOP/28Skinny DIP
¡Ü
44PLCC
I/O Port
input
output
I/O
20pin
3
2
13
24pin
3
2
17
28pin
3
2
21
1- 1
44pin
3
2
24
Chapter 1. Overview
PIN ASSIGNMENT
R13
1
28
R14
R13
1
24
R14
R12
2
27
R15
R12
2
23
R15
R11
3
26
R16
R11
3
22
R16
R11
1
20
R16
R10
4
25
R17
R10
4
21
R17
R10
2
19
R17
VDD
5
24
REMOUT
VDD
5
20
REMOUT
VDD
3
18
REMOUT
XOUT
6
23
RESET
XOUT
6
XOUT
4
17
RESET
XIN
7
22
TEST
XIN
7
16
TEST
R00
8
21
R07
R00
R01
9
20
R06
R02
10
19
R03
11
R20
19
RESET
18
TEST
XIN
5
8
17
R07
R00
6
15
R07
R01
9
16
R06
R01
7
14
R06
R05
R02
10
15
R05
R02
8
13
R05
18
R04
R03
11
14
R04
R03
9
12
R04
12
17
VSS
R20
12
13
VSS
R20
10
11
VSS
R21
13
16
R24
R22
14
15
R23
24PIN
NC
REMOUT
RESET
R27
VSS
NC
TEST
R07
R06
R05
NC
39
38
37
36
35
34
33
32
31
30
29
24PIN
20PIN
NC
40
28
NC
R17
41
27
R04
R16
42
26
VSS
R15
43
25
R24
R14
44
24
R23
23
NC
2
22
R22
R12
3
21
R21
R11
4
20
R20
R10
5
19
R03
NC
6
18
NC
11
12
13
14
15
16
17
NC
R25
R26
R01
R02
NC
10
XIN
R00
9
XOUT
44PLCC
VDD
R13
8
1
7
NC
NC
28PIN
1- 2
Chapter 1. Overview
1.2 Block Diagram
WATCHDOG
G8MC
TIMER
CORE
R0
R00~R07
REMOUT
R17/T0
R16/T1
R15/T2
R14/EC
PORT
RAM
TIMER
(448byte)
R12/INT2
INTERRUPT
`
R1
R10~R17
R11/INT1
PORT
ROM
R00~R07
R10~R17
Key scan
INT.
generation
Block
(16K byte)
R2
R20~R27
TEST
RESET
Xin
CLOCK
GEN. /
SYSTEM
CONTROL
PORT
PRESCALER
/
B.I.T
Xout
Vdd
Vss
1- 3
Chapter 1. Overview
1.3 Package Dimension
1.3.1 20SOP Pin Dimension(dimensions in inch)
1.3.2 20PDIP Pin Dimension (dimensions in inch)
1- 4
Chapter 1. Overview
1.3.3 24SOP Pin Dimension (dimensions in inch)
1.3.4 24skinnyDIP Pin Dimension (dimensions in inch)
1- 5
Chapter 1. Overview
1.3.5 28SOP Pin Dimension (dimensions in inch)
1.3.6 28skinnyDIP Pin Dimension (dimensions in inch)
1- 6
Chapter 1. Overview
1.3.7 44PLCC Pin Dimension (dimensions in mm)
1- 7
Chapter 1. Overview
1.4 Pin Function
PIN NAME
INPUT
INPUT/
OUTPUT 20Pin 24Pin 28Pin 44Pin
R00
I/O
6
8
8
11
R01
I/O
7
9
9
15
R02
I/O
8
10
10
16
R03
I/O
9
11
11
19
R04
I/O
12
14
18
27
R05
I/O
13
15
19
30
R06
I/O
14
16
20
31
R07
I/O
15
17
21
32
R10
I/O
2
4
4
5
R11/INT1
I/O
1
3
3
4
R12/INT2
I/O
-
2
2
3
Function
@ RESET @ STOP
- Each bit of the port can be
individually configured as an
input or an output by user
software
- Push-pull output
- CMOS input with pull-up resistor
(option)
- Can be programmable as Key
Scan Input
- Pull-ups are automatically
disabled at output mode
INPUT
State
of before
STOP
- CMOS input with pull-up resistor
(option)
- Push-pull output
- Can be programmable as Key
Scan Input or Open drain output
- Direct Driving of LED(N-TR)
- Pull-ups are disabled at output
mode
INPUT
State
of before
STOP
INPUT
State
of before
STOP
R13
I/O
-
1
1
2
R14/EC
I/O
-
24
28
44
R15/T2
I/O
-
23
27
43
R16/T1
I/O
20
22
26
42
R17/T0
I/O
19
21
25
41
R20
I/O
10
12
12
20
R21
I/O
-
-
13
21
R22
I/O
-
-
14
22
R23
I/O
-
-
15
24
R24
I/O
-
-
16
25
R25
I/O
-
-
-
13
R26
I/O
-
-
-
14
R27
I/O
-
-
-
36
XIN
I
5
7
7
10
XOUT
O
4
6
6
9
- Oscillator Input
- Oscillator Output
REMOUT
O
18
20
24
38
- High Current Output
RESET
I
17
19
23
37
- Includes pull-up resistor
TEST
I
16
18
22
33
- Includes pull-up resistor
VDD
P
3
5
5
8
- Positive power supply
VSS
P
11
13
17
26
VSS
P
-
-
-
35
- CMOS input with pull-up resistor
(option)
- Push-pull output
- Direct Driving of LED(N-TR)
- Pull-ups are disabled at output
mode
- Ground
1- 8
Low
High
`L` output `L` Output
state
`L` level
of before
STOP
Chapter 1. Overview
1.5 Port Structure
1.5.1 R0 PORT
PIN
CIRCUIT TYPE
@ RESET
VDD
pull-up
option
Data Reg
R00
R01
R02
R03
R04
R05
R06
R07
VDD
PAD
Direction Reg
Data Bus
¡è
Rd
VSS
MUX
Data Bus
¡è
Rd
1- 9
Hi - Z
OR
High-Input
(with pullup)
Chapter 1. Overview
1.5.2 R1 PORT
PIN
CIRCUIT TYPE
open drain
selection
@ RESET
VDD
VDD
pull-up
option
Data Reg
PAD
R10
R11/INT1
R12/INT2
R13
R14/EC
Data Bus
VSS
MUX
Rd
T0 R11...INT1
T0 R12...INT2
T0 R14...EC
open drain
selection
from R15...T2
from R16...T1
from R17...T0
Data Reg
R15 / T2
R16 / T1
R17 / T0
Hi - Z
OR
High-Input
(with pullup)
Direction Reg
VDD
VDD
pull-up
option
MUX
PAD
Direction Reg
Data Bus
VSS
MUX
Rd
1 - 10
Hi - Z
OR
High-Input
(with pullup)
Chapter 1. Overview
1.5.3 R2 PORT
PIN
CIRCUIT TYPE
@ RESET
VDD
R20
R21
R22
R23
R24
R25
R26
R27
VDD
pull-up
option
Data Reg
PAD
Direction Reg
Data Bus
¡è
Rd
Hi - Z
OR
High-Input
(with pullup)
VSS
MUX
REMOUT PORT
PIN
CIRCUIT TYPE
@ RESET
VDD
REMOUT
PAD
internal signal
VSS
1 - 11
Low level
Chapter 1. Overview
1.5.4 Miscellaneous Ports
PIN
CIRCUIT TYPE
@ RESET
Xout
Xin
Xin
Xout
oscillation
from STOP circuit
VSS
VDD
pull-up resistor
VSS
RESET
Low level
PAD
from POWER on RESET circuit
VSS
VDD
pull-up resistor
VSS
TEST
PAD
1 - 12
High level
Chapter 1. Overview
1.6 Electrical Characteristics
1.6.1 Absolute Maximum Ratings (Ta = 25¡É )
PARAMETER
SYMBOL
Supply Voltage
VDD
RATINGS
UNIT
-0.3 ~ +7.0
V
Input Voltage
VI
-0.3 ~ VDD + 0.3
V
Output Voltage
VO
-0.3 ~ VDD + 0.3
V
Operating Temperature
Topr
Storage Temperature
Tstg
1.6.2
Recommended
Power
Dissipation Operating Ranges
PD
0 ~ 70
¡É
-65 ~ 150
¡É
700
mW
1.6.2 Recommended Operating Ranges
PARAMETER
SYMBOL
CONDITION
MIN.
TYP.
MAX.
UNIT
VDD1
fXin = 1MHz
fXin = 2MHz
2.0
4.0
V
VDD2
fXin = 4MHz
2.2
4.0
V
4.0
MHz
70
¡É
Supply Voltage
Oscillation Frequency
fXin
1.0
Operating Temperature
Topr
0
1 - 13
2.0
Chapter 1. Overview
1.6.3 DC Characteristics (VDD = 2.0~4.0, Vss = 0V, Ta = 0¡É ~ 70¡É )
Parameter
Symbol
Specification
Condition
min
high level
input voltage
VIH1
R11, R12, R14, RESETB
0.8VDD
VIH2
R0, R1(Except R11,R12,R14 ) , R2
low level
input voltage
VIL1
R11, R12, R14, RESETB
VIL2
R0, R1(Except R11,R12,R14 ) , R2
typ
max
Unit
VDD
V
0.7VDD
VDD
V
0
0.2VDD
V
0
0.3VDD
V
high level input
leakage current
IIH
R0,R1,R2,RESETB
VIH=VDD
1
uA
low level input
leakage current
IIL
R0,R1,R2,RESETB
(without pull-up)
VIL=0V
-1
uA
VOH1
R0
IOH=-0.5mA
VDD-0.4
V
VOH2
R1(ExceptR17),R2
IOH=-1mA
VDD-0.4
V
VOH3
R17
IOH=-8mA
VDD-0.9
V
VOH5
OSC
IOH=-200uA
VDD-0.9
V
VOL1
R0
IOL=1mA
0.4
V
VOL2
R1, R2
IOL=5mA
0.8
V
VOL5
OSC
IOL=200uA
0.8
V
IOHL
R0, R1, R2
VOH=VDD
1
uA
IOLL
R0, R1, R2
VOL=0V
-1
uA
IOH
REMOUT
VOH=2V
-30
-12
-5
mA
IOL
REMOUT
VOL=1V
0.5
-
3
mA
IP1
RESETB
VDD=3V
15
30
60
uA
IP2
R0, R1, R2
VDD=3V
10
20
40
uA
high level
output voltage
low level
output voltage
high level output
leakage current
low level output
leakage current
high level output
current
low level output
current
input pull-up
current
fXIN=4MHz
POWER
SUPPLY
CURRENT
IDD
fXIN=2MHz
ISTOP
RAM retention
supply voltage
operating
current
stop
mode
current
oscillator
stop
VRET
VDD=4V
4
10
mA
VDD=2.2V
2.4
6
mA
VDD=4V
2.4
6
mA
VDD=2V
1.2
3
mA
3
10
uA
2
8
uA
VDD=4V
VDD=2V
----0.7
1 - 14
V
Chapter 1. Overview
¡Ü GMS810 Series REMOUT port IOH Characteristics graph
0.0
-5.0
VDD=2V
-10.0
IOH(mA)
-15.0
VDD=3V
-20.0
-25.0
-30.0
VDD=4V
-35.0
0
1
2
3
4
VOH(V)
¡Ü GMS810 Series REMOUT port IOL Characteristics graph
8.00
7.00
VDD=4V
6.00
IOL(mA)
5.00
4.00
VDD=3V
3.00
2.00
1.00
VDD=2V
0.00
0
1
2
3
VOL(V)
1 - 15
4
Chapter 1. Overview
1.6.4 AC Characteristics (VDD = 2.0~4.0, Vss = 0V, Ta = 0¡É ~ 70¡É )
Specification
No
Parameter
Symbol
Pin
typ
max
250
500
1000
ns
1000 2000
ns
1
External clock input cycle time
tcp
2
System clock cycle time
tsys
3
External clock pulse width High
tcpH
Xin
40
ns
4
External clock pulse width Low
tcpL
Xin
40
ns
5
External clock rising time
trcp
Xin
40
ns
6
External clock falling time
tfcp
Xin
40
ns
7
interrupt pulse width High
tIH
INT1~INT2
2
tsys
8
Interrupt pulse width Low
tIL
INT1~INT2
2
tsys
9
Reset input pulse width low
tRSTL
RESET
8
tsys
tECH
EC
2
tsys
tECL
EC
2
tsys
trEC
EC
40
ns
tfEC
EC
40
ns
10
11
12
13
Event counter
width high
Event counter
width low
Event counter
rising time
Event counter
falling time
input pulse
input pulse
input pulse
input pulse
Xin
Unit
min
500
* Refer to Fig 1-1
1 - 16
Chapter 1. Overview
tCPH
tCP
tCPL
Vcc-0.5V
Xin
0.5V
trCP
tfCP
tIH
tIL
0.8Vcc
INT1
INT2
0.2Vcc
tRSTL
RESET
0.2Vcc
tECH
EC
tECL
0.8Vcc
0.8Vcc
0.2Vcc
trEC
tfEC
* FIG-1 : Clock, INT, RESET. EC input timing
1 - 17
OVERVIEW
1
FUNCTION DESCRIPTION
2
I/O PORT
3
PERIPHERAL HARDWARE
4
INTERRUPT
5
STANDBY FUNCTION
6
RESET FUNCTION
7
APPENDIX A.
8
APPENDIX B.
9
Chapter 2. Function Description
CHAPTER 2. FUNCTION DESCRIPTION
2.1 REGISTERS
15
7
0
PCH
PCL
Program Counter
7
0
A
15
A-Register
¡é
7
0
YA (16bit Accumulator)
7
0
X
X-Register
7
0
Y
Y-Register
7
0
Stack Pointer ¡Ø1
SP
7
0
PSW
Program Status Word
¡é
N
V
G
B
H
I
Z
C
Carry Flag
Zero Flag
Interrupt Enable Flag
Half Carry Flag
Break Flag
G Flag
Overflow Flag
Negative Flag
¡Ø1 Stack Address
15
7
PCH
0
PCL
¡é
Fixed as 01XXh (=RAM 1page)
¡é
SP
2- 1
Chapter 2. Function Description
2.1.1 A register
- 8bit Accumulator.
- In the case of 16-bit operation, compose the lower 8-bit of A, upper 8bit in Y (16-bit
Accumulator)
- In the case of multiplication instruction, execute as a multiplier register. After
multiplication operation, the lower 8-bit of the result enters. (Y*A ¡æ YA)
- In the case of division instruction, execute as the lower 8-bit of dividend. After
division operation, quotient enters.
2.1.2 X register
- General-purpose 8-bit register
- In the case of index addressing mode within direct page(RAM area), execute as
index register.
- In the case of division instruction, execute as register.
2.1.3 Y register
- General-purpose 8-bit register
- In the case of index addressing mode, execute as index register
- In the case of 16-bit operation instruction, execute as the upper 8-bit of YA (16-bit
accumulator).
- In the case of multiplication instruction, execute as a multiplicand register. After
multiplication operation, the upper 8-bit of the result enters.
- In the case of division instruction, execute as the upper 8-bit of dividend. After
division operation, remains enters.
- Can be used as loop counter of conditional branch command. (e.g.DBNE Y, rel)
2.1.4 Stack Pointer
- In the cases of subroutine call, Interrupt and PUSH, POP, RETI, RET instruction,
stack data on RAM or in the case of returning, assign the storage location having
stacked data.
- Stack area is constrained within 1-page (00H-FFH). The SP is post-decremented
when a subroutine call or a push instruction is executed, or when an interrupt is
accepted; and the SP is pre-incremented when a return or a pop instruction is
executed.
- SP should be initialized as follows
ex) LDX #0FEH
: 0FEH ¡æ X reg.
TXSP
: X reg. ¡æ SP
- The behaviors of stack pointer according to each instruction are the following.
2- 2
Chapter 2. Function Description
2.1.4.1 Interrupt
M(SP) ¡ç (PCH)
M(SP) ¡ç (PCL)
M(SP) ¡ç (PSW)
SP ¡ç SP - 1
SP ¡ç SP - 1
SP ¡ç SP - 1
SP ¡ç SP + 1
SP ¡ç SP + 1
SP ¡ç SP + 1
(PSW) ¡ç M(SP)
(PCL) ¡ç M(SP)
(PCH) ¡ç M(SP)
2.1.4.2 RETI( Return from interrupt )
2.1.4.3 Subroutine call
M(SP) ¡ç (PCH)
M(SP) ¡ç (PCL)
SP ¡ç SP - 1
SP ¡ç SP - 1
2.1.4.4 RET(Return from subroutine)
SP ¡ç SP + 1
SP ¡ç SP + 1
(PCL) ¡ç M(SP)
(PCH) ¡ç M(SP)
2- 3
Chapter 2. Function Description
2.1.4.5 PUSH A(X, Y, PSW)
M(SP) ¡ç A
SP ¡ç SP - 1
2.1.4.6 POP A(X, Y, PSW)
SP ¡ç SP + 1
A ¡ç M(SP)
2.1.5 PC (Program Counter)
- Program counter is a 16-bit counter consisted of 8-bit register PCH and PCL.
- Addressing space is 64K bytes.
2.1.6 PSW (Program Status Word)
- PSW is an 8-bit register.
- Consisted of the flags showing the post state of operation and the flags determining
the CPU operation, initialized as 00H in reset state.
2.1.7 Flag register.
2.1.7.1 Carry flag (C)
-
After operation, set when there is a carry from bit7 of ALU or there is not a borrow.
Set by SETC and clear by CLRC.
Executable as 1-bit accumulator.
Branch condition flag of BCS, BCC.
2.1.7.2 Zero flag (Z)
- After operation also including 16-bit operatiion, set if the result is ¡È0¡È
- Branch condition flag of BEQ, BNE.
2.1.7.3 Interrupt enable flag (I)
- Master enable flag of interrupt except for RST (reset).
- Set and cleared by EI, DI
2- 4
Chapter 2. Function Description
2.1.7.4 Half carry flag (H)
- After operation, set when there is a carry from bit3 of ALU or there is not a borrow
from bit4 of ALU.
- Can not be set by any instruction.
- Cleared by CLRV instruction like V flag.
2.1.7.5 Break flag (B)
- Set by BRK (S/W interrupt) instruction to distinguish BRK and TCALL instruction
having the same vector address.
2.1.7.6 G flag (G)
- Set and cleared by SETG, CLRG instruction.
- Assign direct page (0-page, 1-page).
- Addressable directly to RAM 1-page by SETG. and to RAM 0-page by CLRG.
2.1.7.7 Overflow flag (V)
- After operation, set when overflow or underflow occurs.
- In the case of BIT instruction, bit6 memory location is transferred to V-flag.
- Cleared by CLRV instruction, but not set by any instruction.
- Branch condition flag of BVS, BVC.
2.1.7.8 Negative flag (N)
- Set whenever the result of a data transfer or operation is negative (bit7 is set to
¡È1¡È).
- In the case of BIT instruction, bit7 of memory location is transferred to N-flag
- N-flag is not affected by CLR or SET instruction.
- Branch condition flag of BPL, BMI.
2- 5
Chapter 2. Function Description
2.2 MEMORY MAP
0000h
RAM
(192 BYTES)
0-PAGE
00BFh
DIRECT PAGE
PERIPHERAL REGISTERS
0100h
RAM (STACK)
(256 BYTES)
1-PAGE
0200h
NON-USE
GMS81032
8000h
ROM
(32,768 BYTES)
GMS81024
A000h
ROM
(24,576 BYTES)
GMS81016
C000h
PROGRAM ROM
ROM
(16,384 BYTES)
GMS81008
E000h
ROM
(8,192 BYTES)
GMS81004
F000h
ROM
(4,096 BYTES)
FF00h
PCALL AREA
FFC0h
TCALL VECTOR AREA
FFE0h
INTERRUPT VECTOR AREA
FFFFh
2- 6
U-PAGE
Chapter 2. Function Description
2.3 TCALL VECTOR AREA
FFC0h
FFC1h
FFC2h
FFC3h
FFC4h
FFC5h
FFC6h
FFC7h
FFC8h
FFC9h
FFCAh
FFCBh
FFCCh
FFCDh
FFCEh
FFCFh
FFD0h
FFD1h
FFD2h
FFD3h
FFD4h
FFD5h
FFD6h
FFD7h
FFD8h
FFD9h
FFDAh
FFDBh
FFDCh
FFDDh
FFDEh
FFDFh
* This
TCALL 15
TCALL 14
TCALL 13
TCALL 12
TCALL 11
TCALL 10
TCALL 9
TCALL 8
TCALL 7
TCALL 6
TCALL 5
TCALL 4
TCALL 3
TCALL 2
TCALL 1
TCALL 0
(L)
(H)
(L)
(H)
(L)
(H)
(L)
(H)
(L)
(H)
(L)
(H)
(L)
(H)
(L)
(H)
(L)
(H)
(L)
(H)
(L)
(H)
(L)
(H)
(L)
(H)
(L)
(H)
(L)
(H)
(L)
(H)
*
vector area is used in BRK command and TCALL0 command.
2- 7
Chapter 2. Function Description
2.4 ZERO-PAGE PERIPHERAL REGISTERS
RESET VALUE
ADDRESS
FUNCTION REGISTERS
R/W
SYMBOL
7 6 5 4 3 2 1 0
00C0H
PORT R0 DATA REG.
00C1H
PORT R0 DATA DIRECTION REG.
00C2H
PORT R1 DATA REG.
00C3H
PORT R1 DATA DIRECTION REG.
00C4H
PORT R2 DATA REG.
00C5H
PORT R2 DATA DIRECTION REG.
00C6H
Reserved
R/W
R0
W
R0DD
Undefined
00
R/W
R1
Undefined
W
R1DD
00
R/W
R2
Undefined
W
R2DD
00
CLOCK CONTROL REG.
W
CKCTLR
BASIC INTERVAL REG.
R
BITR
00C8H
WATCH DOG TIMER REG.
W
WDTR
00C9H
PORT R1 MODE REG.
W
PMR1
00CAH
INT. MODE REG.
R/W
IMOD
00CBH
EXT. INT. EDGE SELECTION
W
IEDS
00CCH
INT. ENABLE REG. HIGH
R/W
IENL
-
0
0
00CDH
INT. REQUEST FLAG REG. LOW
R/W
IRQL
-
0
0
00CEH
INT. ENABLE REG. HIGH
R/W
IENH
0
0
00CFH
INT. REQUEST FLAG REG. HIGH
R/W
IRQH
0
0
00D0H
TIMER 0 (16bit) MODE REG.
R/W
TM0
00
00D1H
TIMER 1 (8bit) MODE REG.
R/W
TM1
00
00D2H
TIMER 2 (8bit) MODE REG.
R/W
TM2
00
00D3H
TIMER 0 HIGH-MSB DATA REG.
W
T0HMD
Undefined
00D4H
TIMER 0 HIGH-LSB DATA REG.
W
T0HLD
Undefined
TIMER0 LOW-MSB DATA REG.
W
T0LMD
Undefined
TIMER0 LOW-MSB COUNT REG.
R
TIMER0 LOW-LSB DATA REG.
W
TIMER0 LOW-LSB COUNT REG.
R
TIMER 1 HIGH DATA REG.
W
T1HD
Undefined
TIMER1 LOW DATA REG.
W
T1LD
Undefined
TIMER1 LOW COUNT REG.
R
TIMER2 DATA REG.
W
TIMER2 COUNT REG.
R
00C7H
00D5H
00D6H
00D7H
00D8H
00D9H
00DAH
TIMER 0/ TIMER1 MODE REG.
00DBH
Reserved
00DCH
00DDH
00DEH
-
-
1
1
0
1
1
1
1
1
1
1
0
0
0
0
-
-
-
-
-
-
-
-
-
-
0
-
0
0
0
-
0
-
0
0
0
-
Undefined
-
0
0
0
00
-
-
0
0
00
Undefined
T0LLD
Undefined
Undefined
Undefined
T2DR
Undefined
Undefined
R/W
TM01
00
STANDBY MODE RELEASE REG0
W
SMRR0
00
STANDBY MODE RELEASE REG1
W
SMRR1
00
PORT R1 OPEN DRAIN ASSIGN REG.
W
R1ODC
00
- ; Not used
* Caution : Write only register can not be accessed by bit manipulation instruction.
: Do not access the Reserved registers .
2- 8
OVERVIEW
1
FUNCTION DESCRIPTION
2
I/O PORT
3
PERIPHERAL HARDWARE
4
INTERRUPT
5
STANDBY FUNCTION
6
RESET FUNCTION
7
APPENDIX A.
8
APPENDIX B.
9
Chapter 3. I/O PORT
CHAPTER 3. I/O PORTS
The GMS810series has 21 I/O ports which are PORT0(8 I/O), PORT1 (8 I/O) and
PORT2 (8 I/O). Each port contains data direction register which controls I/O and data
register which stores port data.
3.1 PORT R0
3.1.1 PORT R0 Registers
REGISTER
R0 I/O Data Direction Register
SYMBOL
R/W
RESET VALUE
ADDRESS
R0DD
W
00H
00C1H
R0
R/W
Undefined
00C0H
R0 Data Register
Table 3.1 Port R0 Registers
3.1.2 I/O Data Direction Register (R0DD)
bit
R0DD
initial value
R/W
7
6
5
4
3
2
1
0
R0DD7
R0DD6
R0DD5
R0DD4
R0DD3
R0DD2
R0DD1
R0DD0
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
<00C1H>
R0 I/O Data Direction Register(R0DD) is 8-bit register, and can assign input state or
output state to each bit. If R0DD is ¡È1¡È, port R0 is in the output state, and if ¡È0¡È, it is
in the input state. R0DD is write-only register. Since R0DD is initialized as ¡È00H¡È in
reset state, the whole port R0 becomes input state.
3.1.1 Data Register(R0)
bit
7
6
5
4
3
2
1
0
R0
R07
R06
R05
R04
R03
R02
R01
R00
initial value
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
<00C0H>
PORT0 data register (R0) is 8-bit register to store data of port R0.
When setted as the output state by R0DD, and data is written in R0, data is outputted
into R0 pin. When set as the input state, input state of pin is read.
The initial value of R0 is unknown in reset state.
3 -1
Chapter 3. I/O PORT
3.2 PORT R1
PIN NAME
PORT SELECTION
R10
R11/INT1
R12/INT2
R13
R14/EC
R15/T2
R16/T1
R17/T0
FUNCTION SELECTION
R10(I/O)
R11(I/O)
R12(I/O)
R13(I/O)
R14(I/O)
R15(I/O)
R16(I/O)
R17(I/O)
INT1 (INPUT)
INT2 (INPUT)
EC (INPUT)
T2 (OUTPUT)
T1 (OUTPUT)
T0 (OUTPUT)
Fig 3.1 Pin Function of port R1
3.2.1 PORT R1 Register
REGISTER
SYMBOL
R/W
RESET VALUE
ADDRESS
R1 I/O Data Direction Register
R1DD
W
00H
00C3H
R1
R/W
Undefined
00C2H
R1 Port Mode Register
PMR1
W
00H
00C9H
R1 Port Open drain Assign
Register
R10DC
W
00H
00CEH
R1 Data Register
Table 3.1 Port R1 Registers
3.2.2 I/O Data Direction Register (R1DD)
bit
R1DD
initial value
R/W
7
6
5
4
3
2
1
0
R1DD7
R1DD6
R1DD5
R1DD4
R1DD3
R1DD2
R1DD1
R1DD0
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
<00C3H>
R1 Data Direction Register(R1DD) is 8-bit register, and can assign input state or output
state to each bit. If R1DD is ¡È1¡È, port R1 is in the output state, and if ¡È0¡È, it is in the
input state. R1DD is write-only register. Since R1DD is initialized as ¡È00H¡È in reset
state, the whole port R1 becomes input state.
3 -2
Chapter 3. I/O PORT
3.2.3 Data Register(R1)
R1 Data Register(R1) is 8-bit register to store data of port R1. When set as the output
state by R1DD, and data is written in R1, data is output into R1 pin.
The initial value of R1 is unknown in reset state.
bit
7
6
5
4
3
2
1
0
R1
R17
R16
R15
R14
R13
R12
R11
R10
initial value
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
<00C2H>
3.2.4 Port R1 Open drain Assign Register (R1ODC)
bit
R1ODC
initial value
R/W
7
6
5
4
3
2
1
0
R17OD
R16OD
R15OD
R14OD
R13OD
R12OD
R11OD
R10OD
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
<00DEH>
Port R1 Open Drain Assign Register(R1ODC) is 8bit register, and can assign R1 port as
open drain output port each bit, if corresponding port is selected as output. If R1ODC is
selected as ¡È1¡È, port R1 is open drain output, and if selected as¡È0¡È, it is push-pull
output. R1ODC is write-only register and initialized as ¡È00H¡È in reset state.
3 -3
Chapter 3. I/O PORT
3.2.5 Port R1 Mode Register (PMR1)
bit
PMR1
initial value
R/W
7
6
5
4
3
2
1
0
T0S
T1S
T2S
ECS
-
INT2S
INT1S
-
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
<00C9H>
R1 Port Mode Register(PMR1) is 8-bit register, and can assign the selection mode for
each bit. When set as¡È0¡È, corresponding bit of PMR1 acts as port R1 selection mode,
and when set as¡È1¡È, it becomes function selection mode.
BIT NAME
T0S
T1S
T2S
ECS
-
INT2S
INT1S
PMR1
Selection Mode
Remarks
0
R17 Sel(I/O)
-
1
T0 Sel (Output)
Output Port of Timer0
0
R16 Sel (I/O)
-
1
T1 Sel (Output)
Output Port of Timer1
0
R15 Sel (I/O)
-
1
T2 Sel (Output)
Output Port of Timer2
0
R14 Sel (I/O)
-
1
EC Sel (Input)
Input Port of Timer0 Event Input
0
R12 sel (I/O)
-
1
INT2 Sel (Input)
Input Port of Timer0 Input capture
0
R11 Sel (I/O)
-
1
INT1 Sel (Input)
-
0
1
-
Table 3.3 Selection Mode of PMR1
PMR1 is write-only register and initialized as ¡È 00H¡È in reset state. Therefore,
becomes Port selection mode. Port R1 can be I/O port by manipulating each R1DD bit,
if corresponding PMR1 bit is selected as ¡È0¡È.
3 -4
Chapter 3. I/O PORT
3.3 PORT R2
3.3.1 PORT R2 Registers
REGISTERS
SYMBOL
R/W
RESET VALUE
ADDRESS
R2 I/O Data Direction Register
R2DD
W
00H
00C5H
R2
R/W
Undefined
00C4H
R2 Data Register
Table 3.3 Port R2 Registers
3.3.2 I/O Data Direction Register (R2DD)
bit
R2DD
initial value
R/W
7
6
5
4
3
2
1
0
R2DD7
R2DD6
R2DD5
R2DD4
R2DD3
R2DD2
R2DD1
R2DD0
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
<00C5H>
R2 Data Direction Register(R2DD) is 8-bit register, and can assign input state or output
state or output state to each bit. If R2DD is ¡È1¡È, port R2 is in the output state, and if
¡È0¡È, it is in the input state.
R2DD is write-only register. Since R2DD is initialized as ¡È00H¡È in reset state, the
whole port R2 becomes input state.
3.3.3 Data Register (R2)
bit
7
6
5
4
3
2
1
0
R2
R27
R26
R25
R24
R23
R22
R21
R20
initial value
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
<00C4H>
R2 Data Register(R2) is 8-bit register to store data of port R2.
When setted as the output state by R2DD, and data is written in R2, data is output into
R2 pin. When setted as input state, input state of pin is read.
The initial value of R2 is unknown in reset state.
3 -5
OVERVIEW
1
FUNCTION DESCRIPTION
2
I/O PORT
3
PERIPHERAL HARDWARE
4
INTERRUPT
5
STANDBY FUNCTION
6
RESET FUNCTION
7
APPENDIX A.
8
APPENDIX B.
9
Chapter 4. Peripheral Hardware
CHAPTER 4. PERIPHERAL HARDWARE
4.1 CLOCK GENERATING CIRCUIT
Clock generating circuit consists of Clock Pulse Generator(C.P.G), Prescaler, Basic
Interval Timer(B.I.T) and Watch Dog Timer.
The clock applied to the Xin pin divided by two is used as the internal system clock.
fex
fcpu
OSC
Circuit
Internal System Clock
C.P.G
PRESCALER
IFBIT
PS1
ENPCK
0
7
0
5
8
WDTCL
B.I.T (8)
MUX
WDT (6)
9
BTCL
IFWDT
COMPARATOR
3
WDTON
Peripheral
6
5
6
0
CKCTLR
0
1
2
3
4
WDTR
5
Internal Data Bus
Fig. 4.1 Block diagram of clock generating circuit
4 -1
6
To Reset
Circuit
Chapter 4. Peripheral Hardware
4.1.1 Oscillation Circuit
Oscillation circuit is designed to be used either with a ceramic resonator or crystal
oscillator. Fig. 4.2-(a) shows circuit diagrams using a crystal (or ceramic) oscillator.
As shown in the diagram, oscillation circuits can be constructed by connecting a
oscillator between Xout and Xin. Clock from oscillation circuit makes CPU clock via
clock pulse generator, and then enters prescaler to make peripheral hardware clock.
alternately, the oscillator may be driven from an external source as shown is Fig. 4.2.(b). In the Standby(STOP) mode, oscillatiion stop, Xout state goes to ¡ÈHIGH¡È, Xin
state goes to ¡ÈLOW¡È, and built-in feed back resistor is disabled.
(a) External Crystal (Ceramic) oscillator circuit
Cout
Xout
Xin
Cin
(b) External clock input circuit
Xout
Xin
External clock
Fig. 4.2 Oscillator configurations
*. Recommendable resonator
Frequency
Resonator Maker
CQ
4.0MHz
Part Name
Load Capacitor
Operating Voltage
ZTA4.00MG
Cin=Cout=30pF
2.2 ~ 4.0V
KYOCERA
KBR- 4.0MKC
Cin=Cout=open
2.2 ~ 4.0V
KYOCERA
KBR- 4.0MSB
Cin=Cout=33pF
2.2 ~ 4.0V
TDK
FCR4.0MC5
Cin=Cout=open
2.2 ~ 4.0V
TDK
FCR4.0M5
Cin=Cout=33pF
2.2 ~ 4.0V
TDK
CCR4.0MC3
Cin=Cout=open
2.2 ~ 4.0V
¡Ø MC type is building in load capacitior.CCR type is chip type.
4 -2
Chapter 4. Peripheral Hardware
4.1.2 Prescaler
Prescaler consists of 12-bit binary counter. The clock supplied from oscillation circuit is
input to prescaler (fex). The divided output from each bit of prescaler is provided to
peripheral hardware.
4.1.3 Peripheral hardware clock control
Clock to peripheral hardware can be stopped by bit4 (ENPCK) of CKCTLR Register.
ENPCK is set to ¡È1¡È in reset state.
PS1
fex
PS2
PS3
PS4
PS5
PS6
PS7
PS8
PS9
PS10
PS11
PS12
ENPCK
B.I.T
PS0
fcpu
PS1
PS2
PS3
PS4
PS5
PS6
PS7
PS8
PS9
PS10 PS11
PS12
Peripheral
fex(MHz)
PS0
PS1
PS2
PS3
PS4
PS5
PS6
PS7
PS8
PS9
PS10
PS11
PS12
Freq
4M
2M
1M
500K
250K
125K
62.5K
31.25K
15.63K
7.183K
3.906K
1.953K
0.976K
Period(s)
250n
500n
1u
2u
4u
8u
16u
32u
64u
128u
256u
512u 1024u
Freq
2M
1M
500k
250K
125K
62.5K
31.25K
15.63K
7.183K
3.906K
1.953K
0.976K
Period(s)
500n
1u
2u
4u
8u
16u
32u
64u
128u
256u
512u 1024u 2048u
4
0.488K
2
Fig. 4.3 Block diagram of Prescaler
4 -3
Chapter 4. Peripheral Hardware
Clock Control Register
7
CKCTLR
0
-
-
WDTON
ENPCK
BTCL
BTS2
ENPCK
Peripheral Clock
0
Stopped
1
Provided
BTS1
BTS0
W <00C7H>
4.1.4 Basic Interval Timer (B.I.T)
- 8bit binary counter
- Use the bit output of prescaler as input to secure the oscillation stabilization time
after power-on
- Secures the oscillation stabilization time in standby mode (stop mode) release
- Contents of B.I.T can be read
- Provides the clock for watch dog timer.
DATA BUS
-
-
WTON
ENPCK
BTCL
BTS2
BTS1
BTS0
CKCTLR
PS3
PS4
PS5
BITR
PS6
MUX
BIT0
BIT1
BIT2
BIT3
BIT4
BIT5
BIT6
BIT7
PS7
DATA BUS
PS8
PS9
PS10
Fig. 4.4 Block diagram of Basic Interval Timer
4 -4
IFBIT
Chapter 4. Peripheral Hardware
4.1.4.1 Control of B.I.T
If bit3(BTCL) of CKCTLR is set to ¡È1¡È, B.I.T is cleared, and then, after one machine
cycle, BTCL becomes ¡È0¡È, and B.I.T starts counting. BTCL is set to ¡È0¡È in reset
state.
Clock Control Register
7
CKCTLR
0
-
-
WDTON
ENPCK
BTCL
BTS2
BTS1
BTCL
B.I.T Operation
0
free-run
1
Automatically cleared, after one cycle
BTS0
W <00C7H>
4.1.4.2 Input Clock Selection of Basic Interval Timer
The input clock of B.I.T can be selected from the prescaler within a range of 2us to
256us by clock input selection bits(BTS2~BTS0). (at fex = 4MHz).
In reset state, or power on reset, BTS2=1, BTS1=1, BTS0=1 to secure the longest
oscillation stabilization time.
B.I.T can generate the wide range of basic interval time interrupt request(IFBIT) by
selecting prescaler output.
Interrupt interval can be selected to 8 kinds of interval time as shown in Table. 4.1.
4 -5
Chapter 4. Peripheral Hardware
7
CKCTLR
0
-
-
WDTON
ENPCK
BTCL
BTS2
BTS1
BTS0
BTS2
BTS1
BTS0
B.I.T. Input clock
Standby release time
0
0
0
PS3 (2us)
512 us
0
0
1
PS4 (4us)
1,024 us
0
1
0
PS5 (8us)
2,048 us
0
1
1
PS6 (16us)
4,096 us
1
0
0
PS7 (32us)
8,192 us
1
0
1
PS8 (64us)
16,384 us
1
1
0
PS9 (128us)
32,768 us
1
1
1
PS10 (256us)
65,536 us
W <00C7H>
Table 4.1 Standby release time according to BTS
4.1.4.3 Reading Basic Interval Timer
By reading of the Basic Interval Timer Register(BITR), we can read counter value of
B.I.T. Because B.I.T can be cleared or read, the spending time up to maximum 65.5ms
can be available. B.I.T is read-only register. If B.I.T register is written, then CKCTLR
register with same address is written.
Basic Interval Timer Register
7
BITR
BIT7
0
BIT6
BIT5
BIT4
BIT3
4 -6
BIT2
BIT1
BIT0
R <00C7H>
Chapter 4. Peripheral Hardware
4.1.5 Watch Dog Timer
Watch Dog Timer(WDT) consists of 6-bit binary counter, 6-bit comparator, and Watch
Dog Timer Register (WDTR).
0
5
CLR
WDT0
IFBIT
WDT1
WDT2
WDT3
WDT4
WDTON
WDT5
To Reset circuit
6BIT COMPARATOR
IF WDT
0
6
WDTR0
WDTR
WDTR1
WDTR2
WDTR3
WDTR4
WDTR5
WDTCL
W <00C8H>
Internal Data Bus
Fig. 4.5 Block diagram of Watch Dog Timer
4.1.5.1 Control of WDT
Watch Dog Timer can be used 6-bit general Timer or specific Watch dog timer by setting
bit5(WDTON) of Clock Control Register(CKCTLR).
Clock Control Register
7
CKCTLR
0
-
-
WDTON
ENPCK
BTCL
BTS2
BTS1
WDTON
Watch Dog Timer Function Control
0
6-bit Timer
1
Watch Dog Timer
4 -7
BTS0
W <00C7H>
Chapter 4. Peripheral Hardware
By assigning bit6(WDTCL) of WDTR, 6-bit counter can be cleared
Watch Dog Timer Register
7
WDTR
0
-
WDTCL
WDTR5
WDTR4
WDTR3
WDTR2
WDTR1
WDTR0
W <00C8H>
Determine Interval of IFWDT
Interval of IFWDT = Value of WDTR ¡¿ Interval of IFBIT
WDTCL
Watch Dog Timer Operation
0
Free-run
1
Automatically cleared, after one machine cycle
(Caution) : after WDTCL = 1, timer maximum error is one cycle of IFBIT.
4.1.5.2 WDT Interrupt Interval
WDT Interrupt(IFWDT) interval is determined by the interrupt IFBIT interval of Basic
Interval Timer and the value of WDT Register.
Interval of IFWDT = (IFBIT interval) * (WDTR value)
Interval of IFWDT : 512us ¡¿ 1 = 512us (MIN>)
: 65,536us ¡¿ 63 = 4,128,768us (MAX>)
As IFBIT (Basic Interval Timer Interrupt Request) is used for input clock of WDT, Input
clock cycle is possible from 512us to 65,536us by BTS. (at fex = 4MHz)
*At Hardware reset time ,WDT starts automatically.Therefore, the user must select
the CKCTLR,WDTR before WDT overflow.
( Reset WDTR value = 0Fh,15
interval of WDT = 65,536 ¡¿ 15 = 983040 uS (about 1second ) )
4 -8
Chapter 4. Peripheral Hardware
7
CKCTLR
0
-
-
WDTON
ENPCK
BTCL
BTS2
BTS1
BTS2
BTS1
BTS0
Input clock of WDT
Max. Interval of WDT
output (*note1)
0
0
0
512 us
32,756 us
0
0
1
1,024 us
64,512 us
0
1
0
2,048 us
129,024 us
0
1
1
4,096 us
258,048 us
1
0
0
8,192 us
516,096 us
1
0
1
16,384 us
1,032,192 us
1
1
0
32,768 us
2,064,384 us
1
1
1
65,536 us
4,128,768 us
*note1) When WDTR Register value is 63(3FH)
Caution : Do not use ¡È0¡È for WDTR Register value.
Device come into the reset state by WDT
4 -9
BTS0
W <00C7H>
Chapter 4. Peripheral Hardware
4.2 TIMER
4.2.1 Timer operation mode
Timer consists of 16bit binary counter Timer0(T0), 8bit binary Timer1(T1), Timer2(T2),
Timer Data Register, Timer Mode Register (TM01, TM0, TM1, TM2) and control circuit.
Timer Data Register Consists of Timer0 High-MSB Data Register(T0HMD), Timer0 HighLSB Data Register(T0HLD), Timer0 Low-MSB Data Register(T0LMD), Timer0 Low-LSB
Data Register(T0LLD), Timer1 High Data Register(T1HD), Timer1 Low Data
Register(T1LD), Timer2 Data Register(T2DR).
Any of the PS0~PS5, PS11 and external event input EC can be selected as clock source
for T0. Any of the PS0~PS3, PS7~PS10 can be selected as clock T1. Any of the
PS5~PS12 can be selected as clock source for T2.
Timer0
Timer1
Timer2
-
16-bit Interval Timer
16-bit Event Counter
- Single/Modulo-N Mode
16-bit Input Capture
- Timer Output Initial Value Setting
16-bit rectangular-wave output
- Timer0~Timer1 combination Logic Output
- One Interrupt Generating Every 2nd Counter Overflow
- 8-bit Interval Timer
-8-bit rectangular-wave output
- 8-bit Interval Timer
-8-bit rectangular-wave output
- Modulo-N Mode
*Relevant Port Mode Register (PMR1 : 00C9H) value should be assigned for event counter,
rectangular-wave output and input capture mode.
4 - 10
Chapter 4. Peripheral Hardware
EC/R14
INT2/R12
(Capture
Signal)
Polarity
Selection
TIMER0 (16 BIT)
16
EDGE
Selection
16
8
8
T0HMD
8
T0HLD
8
T0LMD
T0LLD
Tout LOGIC
T1 HD
T0 OUT/R17
REMOUT
T1 LD
8
8
TIMER1 (8 BIT)
T1 OUT/R16
T2DR
TIMER2 (8 BIT)
Fig. 4.6 Timer/Counter Block diagram
4 - 11
T2 OUT/R15
Chapter 4. Peripheral Hardware
4.2.2 Function of Timer & Counter
fex = 4MHz
16bit Timer (T0)
Resolution (CK)
8bit Timer (T1)
MAX.Count
Resolution (CK)
MAX.Count
8bit Timer (T2)
Resolution (CK)
MAX.Count
PS0
( 0.25us)
16,384us
PS0
(0,.25us)
64us
PS5
(
8us)
2.048us
PS1
( 0. 5us)
32,768us
PS1
( 0,5us)
128us
PS6
(
16us)
4,096us
PS2
(
1us)
65,536us
PS2
(
1us)
256us
PS7
(
32us)
8,192us
PS3
(
2us)
131,072us
PS3
(
2us)
512us
PS8
(
64us)
16,384us
PS4
(
4us)
262,144us
PS7
(
32us)
8,192us
PS9
( 128us)
32,768us
PS5
(
8us)
524,288us
PS8
(
64us)
16,384us
PS10 ( 256us)
65,536us
33,554,432us
PS9
( 128us)
32,768us
PS11 ( 512us)
131,072us
65,536us
PS12 (1,024us)
262,144us
PS11 (512us)
EC
-
PS10 (256us)
4 - 12
Chapter 4. Peripheral Hardware
Internal Data Bus
<00D5H>
R/W
<00D6H>
<00D0H>
TM0
7
6
5
4
3
2
1
0
TIMER0 H
COUNT
REG
<00D3H> <00D4H>
TIMER0
HM
DATA
REG
TIMER0 L
COUNT
REG
TIMER0
HL
DATA
REG
<00D5H>
TIMER0
LM
DATA
REG
<00D6H>
TIMER0
LL
DATA
REG
DATA READ
SINGLE/
MODULO-N
SELECTION
16
16
MUX
16
PS0
PS1
CK
PS2
PS3
Int.
Gen.
MUX
T0 COUNTER
(16 BIT)
PS4
PS5
PS11
D
EC
E
M
U
X
IFT0
Clear
L
A
INT2
EDGE
SELECTION
Y
T0INT
OUTPUT GEN.
Fig. 4.7 Block Diagram of Timer0
4 - 13
T0 OUT
Chapter 4. Peripheral Hardware
Timer0 mode Register
7
TM0
CAP0
0
T0ST
T0CN
T0MOD
T0IFS
T0SL2
T0SL1
T0SL0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
T0IFS
0
1
T0MOD
0
1
T0CN
0
1
T0ST
0
1
T0SL1
Input Clock Sel.
PS0
PS1
PS2
PS3
PS4
PS5
PS11
EC
(250ns)
(500ns)
( 1us)
( 2us)
( 4us)
( 8us)
(512us)
T0SL0
Notes
*
Event
Counter
Timer0 Interrupt Sel.
Interrupt Every Counter Overflow
Interrupt Every 2nd Counter Overflow
Timer0 Single / Modulo-N Sel.
Modulo-N
Single Mode
Timer0 Counter Continuation / Pause Control
Count Pause
Count Continuation
Timer0 Start/Stop control
Timer0 Stop
Timer0 Start after Clear
CAP0
0
1
T0SL2
Timer0 Interrupt Sel.
Timer/Counter
Input Capture*
*PS1 : not supporting input capture.
4 - 14
R/W <00D0H>
Chapter 4. Peripheral Hardware
Internal Data Bus
<00D7H>
<00D8H>
<00D8H>
<00D1H>
TM1
7
6
5
4
3
2
1
0
R/W
TIMER1
H
DATA
REG
TIMER1
COUNT REG
X
TIMER1
L
DATA
REG
SINGLE/
MODULO-N
SELECTION
OUTPUT GEN.
PS0
PS1
CK
PS2
PS3
Int.
T1 COUNTER
(8 BIT)
MUX
PS7
Gen.
PS8
PS9
IFT1
PS10
T1INT
OUTPUT GEN.
Fig. 4.8 Block Diagram of Timer1
4 - 15
T1OUT
Chapter 4. Peripheral Hardware
Timer1 mode Register
7
TM1
T1ST
0
T1CN
T1MOD
T1IFS
-
T1SL2
T1SL1
T1SL0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
T1IFS
0
1
T1MOD
0
1
T1CN
0
1
T1ST
0
1
T1SL2
T1SL1
T1SL0
Input Clock Sel.
PS0
PS1
PS2
PS3
PS7
PS8
PS9
PS10
(250ns)
(500ns)
( 1us)
( 2us)
( 32us)
( 64us)
(128us)
(256us)
Timer1 Interrupt Sel.
Interrupt Every Counter Overflow
Interrupt Every 2nd Counter Overflow
Timer1 Single / Modulo-N Sel.
Modulo-N
Single Mode
Timer1 Countern Continuation / Pause Control
Count Pause
Count Continuation
Timer1 Start/Stop control
Timer1 Stop
Timer1 Start after Clear
4 - 16
R/W <00D1H>
Chapter 4. Peripheral Hardware
Timer0/Timer1 mode Register
7
TM01
TOUTS
0
TOUTB
-
T0OUTP
T0UT1
T0UT0
TOUT LOGIC
0
0
1
1
0
1
0
1
AND of T0 OUTPUT and T1 OUTPUT
NAND of T0 OUTPUT and T1 OUTPUT
OR of T0 OUTPUT and T1 OUTPUT
NOR of T0 OUTPUT and T1 OUTPUT
T1INIT
0
1
T0INIT
0
1
T0OUTP
0
1
TOUTB
0
1
TOUTS
0
1
T0INIT
T1INIT
TOUT1
TPIT0
Timer1 Output Initial Value
Timer1 Output Low
Timer1 Output HIgh
Timer0 Output Initial Value
Timer0 Output Low
Timer0 Output High
T0OUTPolarity Selection
T0OUT Polarity Equal to TOUT Logic Input Signal
T0OUT Polarity Reverse to TOUT Logic Input Signal
REMOUT Port Bit Control
REMOUT Output Low
REMOUT Output High
REMOUT Port Output Selection
(TOUT Logic or TOUTB)
Bit(TOUTB) Output Through REMOUT
TOUT Logic Output Through REMOUT
4 - 17
R/W <00DAH>
Chapter 4. Peripheral Hardware
Internal Data Bus
<00D9H>
<00D9H>
<00D2H>
TM2
7
6
5
4
3
2
1
0
R/W
TIMER2
COUNT REG
TIMER2
DATA REG
PS5
PS6
CK
PS7
PS8
IFT2
T2 COUNTER
(8 BIT)
MUX
PS9
PS10
PS11
PS12
OUTPUT GEN.
Fig. 4.9 Block Diagram of Timer2
4 - 18
T2 OUT
Chapter 4. Peripheral Hardware
Timer2 mode Register
7
TM2
-
0
-
-
T2ST
T2CN
T2SL2
T2SL1
T2SL0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
T2cn
0
1
T2ST
0
1
T2SL2
T2SL1
T2SL0
Input Clock Sel.
PS5
PS6
PS7
PS8
PS9
PS10
PS11
PS12
(
8us)
( 16us)
( 32us)
( 64us)
( 128us)
( 256us)
( 512us)
(1,024us)
Timer2 Counter Continuation / Pause Control
Count Pause
Count Continuation
Timer2 Start / Stop Control
Timer2 Stop
Timer2 Start after Clear
4 - 19
R/W <00D2H>
Chapter 4. Peripheral Hardware
PORT mode Register1
7
PMR1
0
T0S
T1S
T2S
PMR1
ECS
-
INT2S
PORT Sel.
0
R17 (I/O)
1
T0 (Output)
0
R16 (I/O)
1
T1 (Output)
0
R15 (I/O)
1
T2 (Output)
0
R14 (I/O)
1
EC (Input)
INT1S
-
W <00C9H>
Remarks
-
T0S
Output Port of Timer0
-
T1S
Output Port of Timer1
-
T2S
Output Port of Timer2
-
ECS
Input Port of Timer0 Event
-
-
-
-
-
-
0
R12 (I/O)
-
1
INT2 (Input)
0
R11 (I/O)
-
1
INT1 (Input)
-
INT2S
Input Port of Timer0 Input Capture
INT1S
-
-
-
-
-
-
-
External Interrupt Signal Edge Selectin Register
7
IEDS
0
-
-
IED2H
IED2L
IED1H
IED*H
IED*L
0
0
1
1
0
1
0
1
IED1L
-
-
INT*
-FallingEdge Selection
Rising Edge Selection
Both Edge Selection
4 - 20
W <00CBH>
Chapter 4. Peripheral Hardware
4.2.3 Timer0, Timer1
TIMER0 and TIMER1 have an up-counter. When value of the up-counter
reaches the content of Timer Data Register(TDR), the up-counter is cleared to
¡È00H¡È, and interrupt(IFT0, IFT1) is occured at the next clock
Fig. 4. 10 Operatiion of Timer0
Concurrence
Concurrence
Concurrence
T0 Data
Registers
Value
T0 Value
0
CLEAR
CLEAR
INTERRUPT
INTERRUPT
CLEAR
INTERRUPT
IFT0
Interval period
For Timer0, the internal clock(PS) and the external clock(EC) can be selected as
counter clock. But Timer1 and Timer2 use only internal clock. As internal clock.
Timer0 can be used as internal-timer which period is determined by Timer Data
Register(TDR). Chosen as external clock, Timer0 executes as event-counter.
The counter execution of Timer0 and Timer1 is controlled by T0CN, T0ST,
CAP0, T1CN, T1ST, of Timer Mode Register TM0 and TM1. T0CN, T1CN are
used to stop and start Timer0 and Timer1 without clearing the counter. T0ST,
T1ST is used to clear the counter. For clearing and starting the counter, T0ST
or T1ST should be temporarily set to ¡È0¡È and then set to ¡È1¡È. T0CN,
T1CN, T0ST and T1ST should be set ¡È1¡È, when Timer counting-up.
Controlling of CAP0 enables Timer0 as input capture. By programming of CAP0
to ¡È1¡È, the period of signal from INT2 can be measured and then, event
counter value for INT2 can be read.
4 - 21
Chapter 4. Peripheral Hardware
T0 Data
Register
Value
Concurrence
Concurrence
CLEAR
CLEAR
T0 Value
0
INTERRUPT
INTERRUPT
IFT0
0
T0ST
1
Clear & Start
0
T0CN
1
Counter
Stop
Count
Clear
& Count
Stop
Count Clear & Start
continue
Fig. 4. 11. Start/Stop operation of Timer0
T3
T2
T1
T0
INT0
Fig. 4. 12. Input capture operation of Timer0
4 - 22
Chapter 4. Peripheral Hardware
During counting-up, value of counter can be read. Timer execution is stopped by the
reset signal (RESET = ¡ÈL¡È)
(Note) in the process of reading 16-bit Timer Data, first read the upper 8-bit data. Then
read the lower 8-bit data, and read the upper 8-bit data again. If the earlier read upper
8-bit data are matched with the later read upper 8-bit data, read 16-bit data are correct.
If not, caution should be taken in the selection of upper 8-bit data.
Example)
1) Upper
2) Lower
3) Upper
8-bit
8-bit
8-bit
Read
Read
Read
0A
FF
0B
0A
01
0B
¡é ¡é
0AFF 0B01
4.2.3.1 Single/Modulo-N Mode
Timer0 (Timer1) can select initial (T0INIT, T1INIT of TM0, TM1) output level of Timer
Output port. If initial level is ¡ÈL¡È, Low-Data Register value of Timer Data Register is
transferred to comparator and T0OUT(T1OUT) is to be ¡ÈLow¡È, if initial level is
¡ÈHigh¡È, High -Data Register is transferred and to be ¡ÈHigh¡È. Single Mode can be
set by Mode Select bit(T0MOD, T1MOD) of Timer Mode Register (TM0, TM1) to ¡È1¡È
When used as Single Mode, Timer counts up and compares with value of Data Register.
If the result is same, Time Out interrupt occurs and level of Timer Output port toggle,
then counter stops as reset state. When used as Modulo-N Mode, T0MOD(T1MOD)
should be set ¡È0¡È. Counter counts up until the value of Data Register and occurs
Time-out interrupt. The level of Timer Output port toggle and repeats process of
counting the value which is selected in Data Register. During Modulo-N Mode, If
interrupt select bit(T0IFS, T1IFS) of Mode Register is ¡È0¡È, Interrupt occurs on every
Time-out. If it is ¡È1¡È, Interrupt occurs every second time-out.
(*note. Timer Output is toggled whenever time out happen)
4 - 23
Chapter 4. Peripheral Hardware
8bit / 16bit
counting
Timer Enable initial.
value toggle.
Timer-output toggle.
interrupt occurs.
count stop.
< Single Mode >
8bit / 16bit
counting
Timer Enable initial.
value toggle.
Timer-Output Toggle.
Int occurs(IFS = 1) Each 2nd time out.
Int occurs(IFS = 0) When Time out.
< Modulo-N Mode >
Fig. 4. 13 Operation Diagram for Single/Modulo-N Mode
4 - 24
Chapter 4. Peripheral Hardware
4.2.4 Timer2
Timer2 operates as a up-counter. The content of T2DR are compared with the
contents of up-counter. If a match is found. Timer2 interrupt (IFT2) is generated
and the up-counter is cleared to ¡È00H¡È. Therefore, Timer2 executes as a
interval timer. Interrupt period is determined by the count source clock for the
Timer2 and content of T2DR.
When T2ST is set to 1, count value of Timer 2 is cleared and starts countingcup. For clearing and starting the Timer2. T2ST have to set to ¡È1¡È after set to
¡È0¡È. In order to write a value directly into the T2DR, T2ST should be set to
¡È0¡È. Count value of Timer2 can be read at any time.
Concurrence
Concurrence
Concurrence
T2 Data
Registers
Value
T2 Value
0
CLEAR
CLEAR
INTERRUPT
INTERRUPT
CLEAR
INTERRUPT
IFT0
Interval period
Fig. 4. 14 Operation of Timer2
4 - 25
Chapter 4. Peripheral Hardware
Concurrence
Concurrence
CLEAR
CLEAR
T2 Data
Register
Value
T2 Value
0
INTERRUPT
INTERRUPT
IFT2
T2ST
count stop by 0
count start clear by 1
Counter
Count up
Count Stop
Count
continue
Fig. 4. 15. Start/Stop of Timer2
4 - 26
Count up after clear
OVERVIEW
1
FUNCTION DESCRIPTION
2
I/O PORT
3
PERIPHERAL HARDWARE
4
INTERRUPT
5
STANDBY FUNCTION
6
RESET FUNCTION
7
APPENDIX A.
8
APPENDIX B.
9
Chapter 5. Interrupt
CHAPTER 5. INTERRUPT
The GMS810 Series contains 8 interrupt sources; 3 externals and 5 internals. Nested
interrupt services with priority control is also possible. Software interrupt is nonmaskable interrupt, the others are all maskable interrupts.
- 8 interrupt source (2Ext, 3Timer, BIT, WDT and Key Scan)
- 8 interrupt vector
- Nested interrupt control is possible
- Programmable interrupt mode
¡Ü
Hardware accept mode
¡Ü
Software selection accept mode
- Read and write of interrupt request flag are possible.
- In interrupt accept, request flag is automatically cleared.
Interrupt hardware consists of Interrupt Mode Register(MOD), Interrupt Enable Register
High (IENH), Interrupt Enable Register Low(IENL), Interrupt Request Register
High(IRQH), Interrupt Request Register Low(IRQL) and priority circuit. Interrupt function
block diagram is shown in Fig. 5.1
5.1 INTERRUPT SOURCE
Each interrupt vector is independent and has its own priority. Software interrupt(BRK) is
also available. Interrupt source classification is shown in Table 5.1
5 -1
Chapter 5. Interrupt
Internal Data Bus
0
7
-
-
-
-
-
-
IENL
KSCN
KSCNR
INT1
INT1R
INT2
INT2R
IFT0
T0R
IFT1
T1R
IFT2
T2R
IFWDT
IFBIT
0
7
-
0
7
-
IENH
-
-
IMOD
PRIORITY
CONTROL
INT.
VECTOR
ADDR.
WDTR
BITR
BRK
Standby Mode Release
IRQ
Fig. 5.1 Interrupt Source
Mask
Priority
Non-maskable
-
RST (RESET PIN)
FFFF
FFFE
0
KSCNR (Key Scan)
FFFB
FFFA
1
INT1R(External Interrupt 1)
FFF9
FFF8
2
INT2R(External Interrupt 2)
FFF7
FFF6
3
T0R (Timer0)
FFF3
FFF2
4
T1R (Timer1)
FFF1
FFF0
5
T2R (Timer2)
FFEF
FFEE
6
WDTR (Watch Dog Timer)
FFE9
FFE8
7
BITR (Basic Interval Timer)
FFE7
FFE6
-
BRK Instruction
FFDF
FFDE
Hardware
Interrupt
Interrupt Source
INT Vector H INT Vector L
Maskable
Software
Interrupt
-
Table 5.1 Interrupt Source
5 -2
Chapter 5. Interrupt
5.2 INTERRUPT CONTROL REGISTER
I flag of PSW is a interrupt mask enable flag. When I flag = ¡È0¡È, all interrupts become
disable. When I flag = ¡È1¡È, interrupts can be selectively enabled and disabled by
contents of corresponding Interrupt Enable Register.
When interrupt is occured, interrupt request flag is set, and Interrupt request is detected
at the edge of interrupt signal. The accepted interrupt request flag is automatically
cleared during interrupt cycle process. The interrupt request flag maintains ¡È1¡È until
the interrupt is accepted or is cleared in program.
In reset state, interrupt request flag register(IRQH, IRQL) is cleared to ¡È0¡È. It is
possible to read the state of interrupt register and to mainpulate the contents of register
and to generate interrupt. (Refer to software interrupt).
Interrupt Enable Register Low
7
IENL
-
WDTR
KSCNE
INT1E
-
WDTR
KSCNR
-
-
INT2E
-
T0E
T1E
BITE
-
-
-
INT1R
INT2R
-
T0R
5 -3
T1R
-
R/W <00CCH>
0
T2E
-
R/W <00CEH>
0
-
Interrupt Request Register High
7
IRQH
-
Interrupt Request Register Low
7
IRQL
-
Interrupt Enable Register High
7
IENH
BITE
0
-
R/W <00CDH>
0
T2R
-
R/W <00CFH>
Chapter 5. Interrupt
5.3 INTERRUPT ACCEPT MODE
The interrupt priority order is determined by bit(IM1, IM0) of IMOD register.
Interrupt Mode Register
7
IMOD
0
-
-
IM1
IM0
IP3
IP2
IP1
IP0
R/W <00CAH>
Assigning by interrupt accept mode bit
IM1
IM0
Priority
0
0
Fixed by H/W
0
1
Changeable by IP 3-0
1
*
Interrupt is inhibited
5.3.1 Selection of interrupt by IP3 - IP0
The condition allow for accepting interrupt is set state of the interrupt mask enable flag
and the interrupt enable bit must be ¡È1¡È.
IP3
IP2
IP1
IP0
Selection interrupt
0
0
0
1
KSCNR (Key Scan)
0
0
1
0
INT1R (External interrupt 1)
0
0
1
1
INT2R (External interrupt 2)
0
1
0
0
Reserved
0
1
0
1
T0R (Timer 0)
0
1
1
0
T1R (Timer 1)
0
1
1
1
T2R (Timer 2)
1
0
0
0
Reserved
1
0
0
1
Reserved
1
0
1
0
WDTR (Watch Dog Timer)
1
0
1
1
BITR (Basic Interval Timer)
1
1
0
0
Reserved
Table 5.2 Interrupt Selection by IP3 - IP0
*In Reset state, these IP3 - IP0 registers become all ¡È0¡È.
5 -4
Chapter 5. Interrupt
5.3.2 Interrupt Timing
CLOCK
A command before interrupt
interrupt process step
SYNC
Interrupt Request Sampling
Fig. 5.2 Interrupt Enable Accept Timing
Interrupt Request
sampling time
Maximum 12 machine cycle (When execute DIV instruction)
Minimum 0 machine cycle
Interrupt preprocess step is 8 machine cycle
Maximum 1 + 12 + 8 = 21 machine cycle
Interrupt overhead
Minimum 1 + 0 + 8 = 9 machine cycle
5.3.3 The valid timing after executing Interrupt control instructions
I flag is valid just after executing of EI/DI on the contrary.
Interrupt Enable register is valid one instruction after controlling interrupt Enable
Register.
5 -5
Chapter 5. Interrupt
5.4 INTERRUPT PROCESSING SEQUENCE
When an interrupt is accepted, the on-going process is stopped and the interrupt service
routine is executed. After the interrupt service routine is completed it is necessary to
restore everything to the state before the interrupt occured.
As soon as an interrupt is accepted, the content of the program counter and PSW are
saved in the stack area.
At the same time, the content of the vector address corresponding to the accepted
interrupt, which is in the interrupt vector table, enters into the program counter and
interrupt service is executed. In order to execute the interrupt service routine, it is
necessary to write the jump addresses in the vector table (FFEOH-FFFFH)
corresponding to each interrupt
Interrupt Processing Step
1) Store upper byte of Program Counter, SP ¡ç SP
2) Store lower byte of Program Counter, SP ¡ç SP - 1
3) Store Program Status Word, SP ¡ç SP - 2
4) After resetting of I-flag, clear accepted Interrupt
Request Flag.(Set B-flag for BRK Instruction)
5) Call Interrupt service routine
5 -6
Chapter 5. Interrupt
Clock
ISR*1
Interrupt Process Step
SYNC
R/W
INTERNAL
ADDR. BUS
INTERNAL
DATA BUS
PC
OP
CODE
SP
OP
CODE
SP-1
PCH
SP-2
PCL
LVA*2
¡ÈL¡È
VECTOR
PSW
HVA*3
NEW PC
¡ÈH¡È
VECTOR
INTERNAL
READ
INTERNAL
WRITE
Fig. 5. 3 Interrupt Procesing Step Timing
*1 ISR : Interrupt Service Routine
*2 LVA : Low Vector Address
*3 HVA : High Vector Address
5.1 SOFTWARE INTERRUPT
5.5.1 Interrupt by Break(BRK) Instruction
Software interrupt is available just by writing ¡ÈBreak(BRK)¡È instruction.
The values of PC and PSW is stacked by BRK instruction and then B flag of PSW is set
and I flag is reset.
Flag change by BRK execution
N
V
G
B
H
set
N
V
G
1
I
Z
C
PSW
Z
C
PSW
reset
H
0
(Right after BRK execution)
5 -7
Chapter 5. Interrupt
Interrupt vector of BRK instruction is shared by vector of Table Call(TCALL0). When
both instruction of BRK and TCALL0 are used, as shown in Fig. 5.4 each processing
routine is judged by contents of B flag.
There is no instruction to reset directly B flag.
B flag
0
1
BRK or
TCALL0
BRK INTERRUPT ROUTINE
TCALL0 ROUTINE
RETI
RET
Fig. 5.4 Execution of BRK or TCALL0
5.6 MULTIPLE INTERRUPT
If there is an interrupt, Interrupt Mask Enable Flag is automatically cleared before
entering the Interrupt Service Routine. After then, no interrupt is accepted. If EI
instruction is executed, interrupt mask enable bit becomes ¡È1¡È, and each enable bit
can accept interrupt request. When two or more interrupts are generated
simultaneously, the highest priority interrupt set by Interrupt Mode Register is accepted.
5 -8
Chapter 5. Interrupt
5.7 Key Scan Input Processing
Key Scan Interrupt is generated by detecting low Input from each Input pin (R0, R1) or
standby(SLEEP, STOP) release signal. Key Scan ports are all 16bit which are
controlled by Stand-by Mode Release Register (SMRR0, SMRR1). Key Input is
considered as Interrupt, therefore, KSCNE bit of IEHN should be set for correct interrupt
executing, SLEEP mode and STOP mode, the rest of executing is the same as that of
external Interrupt. Each SMRR Register bit is allowed for each port(for Bit=0, no Key
Input, for Bit=1, Key Input available). At reset, SMRR becomes ¡È00H¡È. So, there is
no Key Input source.
7
0
SMRR0
W <00DCH>
R00
R01
.
.
R0 port
Selection Logic
R07
7
0
SMRR1
R10
R11
.
.
Internal
Key Scan
Interrupt
W <00DDH>
R1 port
Selection Logic
R17
<Key Scan Block>
5 -9
Chapter 5. Interrupt
SMRR0 Mode Register
7
SMRR0
KR07
0
KR06
KR05
KR04
KR03
KR02
KR01
5 - 10
KR00
W <00DCH>
KR00
Key Input Selection
0
1
no select
select
KR01
Key Input Selection
0
1
no select
select
KR02
Key Input Selection
0
1
no select
select
KR03
Key Input Selection
0
1
no select
select
KR04
Key Input Selection
0
1
no select
select
KR05
Key Input Selection
0
1
no select
select
KR06
Key Input Selection
0
1
no select
select
KR07
Key Input Selection
0
1
no select
select
Chapter 5. Interrupt
SMRR1 Mode Register
7
SMRR1
KR17
0
KR16
KR15
KR14
KR13
KR12
KR11
5 - 11
KR10
W <00DDH>
KR10
Key Input Selection
0
1
no select
select
KR11
Key Input Selection
0
1
no select
select
KR12
Key Input Selection
0
1
no select
select
KR13
Key Input Selection
0
1
no select
select
KR14
Key Input Selection
0
1
no select
select
KR15
Key Input Selection
0
1
no select
select
KR16
Key Input Selection
0
1
no select
select
KR17
Key Input Selection
0
1
no select
select
OVERVIEW
1
FUNCTION DESCRIPTION
2
I/O PORT
3
PERIPHERAL HARDWARE
4
INTERRUPT
5
STANDBY FUNCTION
6
RESET FUNCTION
7
APPENDIX A.
8
APPENDIX B.
9
Chapter6. Standby Function
CHAPTER 6. STANDBY FUNCTION
To save power consumption, there is STOP modes. In this modes, the execution of
program stops.
6.1 STOP MODE
STOP mode can be entered by STOP instruction during program. In STOP mode,
oscillator is stopped to make all clocks stop, which leads to less power consumption. All
registers and RAM data are preserved. ¡ÈNOP¡È instruction should be follows STOP
instruction for rising precharge time of Data Bus line.
ex) STOP : STOP instructiion excution
NOP : NOP instruction
6 -1
Chapter6. Standby Function
OSC.
Clock Pulse GEN
Circuit
CLR
CPU Clock
MUX
Basic Interval Timer
CLR
Prescaler
CLR
STOP
S
Q
R
S
Q
R
Control
Signal
Overflow Detection
Release Signal From Interrupt Circuit
RESET
Fig. 6.1 Block Diagram of Standby Circuit
Prescaler
ENPCK
PS10
Selector
Basic Interval Timer
Peripheral
Fig. 6.2 ENPCK and Basic Interval Timer Clock
6 -2
B.I.T 7
Chapter6. Standby Function
6.2 STANDBY MODE RELEASE
6.2.1 STOP Mode Release
Release of STANDBY mode is executed by RESET input and Interrupt signal. Register
value is defined when Reset. When there is a release signal of STOP mode (Interrupt,
RESET input), the instruction execution starts after stabilization oscillation time is set by
value of BTS2~BTS0 and set ENPCK to 1.
Table 6.1. Standby Mode Register
Release Signal
STOP
RESET
0
KSCN (Key input)
0
INT1 - INT2
0
Table 6.2 Standby Mode Release
Release Factor
Release Method
RESET Pin
By RESET Pin = Low level, Standby mode is release and system is initialized
KSCN
(Key input)
Standby mode is released by Low input of selected pin by Key Scan Input
(SMRR0, SMRR1)
In case of interrupt Mask Enable flag = 0, program executes just after standby
instruction, if flag = 1, enters each interrupt service routine.
INT 1 pin
INT 2 pin
When external interrupt (INT1, INT2) enable flag is ¡È1¡È, standby mode is
released at the rising edge of each terminal.
When Standby mode is released at interrupt. Mask Enable flag = 0, program
executes from the next instruction of standby instruction.
When 1, enters each interrupt service routine.
6 -3
Chapter6. Standby Function
<STOP MODE>
CLCOK
STOP Mode
Stable
OSC. time
Release By Interrupt
Program Setting Time by CKCTLR
Refer to Table 4-1
RESET
Longer than stable OSC. Time
Fig. 6.3 Release Timing of Standby Mode
6.3 RELEASE OPERATION OF STANDBY MODE
After Standby mode is released, the operation begins according to content of
related interrupt register just before Standby mode start(Fig. 6.3)
6.3.1 In Case of Interrupt Enable Flag(I) of PSW = 0
Release by only interrupt which interrupt enable flag = 1, and starts to execute from next
to Standby instruction (STOP).
6 -4
Chapter6. Standby Function
6.3.2 In Case of Interrupt Enable Flag(I) of PSW = 1
Released by only interrupt which each interrupt enable flag = 1, and jump to the relevant
interrupt service routine.
Note) When STOP instruction is used, B.I.T should guarantee the stabilization oscillation
time. Thus, just before entering STOP mode, clock of bit10(PS10) of Prescaler is
selected or peripheral hardware clock control bit(ENPCK) to 1, Therefore the clock
necessary for stabilization oscillation time should be input into B.I.T. otherwise, Standby
mode is released by reset signal. In case of interrupt request flag and interrupt enable
flag are both ¡È1¡È, Standby mode is not entered.
Fig. 6.5 Standby Mode Release Flow
STOP Command
Standby Mode
Interrupt Request GEN.
0
IE Flag
1
Standby Mode Release
0
PSW
IE Flag
1
Standby Next Command
Execution
Interrupt Service Routine
6 -5
Chapter6. Standby Function
Internal circuit
STOP Mode
Oscillator
Stop
Internal CPU clock
Stop
Register
Retained
RAM
Retained
I/O port
Retained
Prescaler
Stop
Basic Interval Timer
Stop
Watch Dog Timer
Stop
Timer
Stop
Address Bus, Data Bus
Retained
Table 6.3 Operation State in Standby Mode
6 -6
OVERVIEW
1
FUNCTION DESCRIPTION
2
I/O PORT
3
PERIPHERAL HARDWARE
4
INTERRUPT
5
STANDBY FUNCTION
6
RESET FUNCTION
7
APPENDIX A.
8
APPENDIX B.
9
Chapter7. Reset Function
CHAPTER 7. RESET FUNCTION
7.1 EXTERNAL RESET
The RESET pin should be held at low for at least 2machine cycles with the power supply
voltage within the operating voltage range and must be connected 0.1uF capacitor
for stable system initialization.
The RESET pin contains a Schmitt trigger with an internal pull-up resistor.
RESET
0.1uF capacitor
Fig 7.0 RESET Pin connection.
7.2 POWER ON RESET
Power On Reset circuit automatically detects the rise of power voltage (the rising time
should be within 50ms) the power voltage reaches a certain level, RESET terminal is
maintained at ¡ÈL¡È Level until a crystal ceramic oscillator oscillates stably. After power
applies and starting of oscillation, this reset state is maintained for about oscillation cycle of
219 (about 65.5ms : at 4MHz).
The execution of built-in Power On Reset circuit is as follows :
(1) Latch the pulse from Power On Detection Pulse Generator circuit, and reset
Prescaler, B.I.T and B.I.T Overflow detection circuit.
(2) Once B.I.T Overflow detection circuit is reset. Then, Prescaler starts to count.
(3) Prescaler output is inputted into B.I.T and PS10 of Prescaler output is automatically
selected. If overflow of B.I.T is detected, Overflow detection circuit is set.
(4) Reset circuit generates maximum period of reset pulse from Prescaler and B.I.T.
7 -1
Chapter7. Reset Function
VDD
Internal IC
Internal Reset
RESET
0.1uF
Power On DET
Pulse GEN.
VSS
XTAL
CLR
OSC.
PS10
Prescaler
CLR
MSB
CLR
Basic Interval
Basic Interval
Tiemr
Tiemr
Fig. 7.1 Block Diagram of Power On Reset Circuit
Notice ; When Power On Reset, oscillator stabilization time doesn`t include OSC. Start time.
VDD
PRESCALER COUNT START
OSC. START TIMING
Fig. 7.2 Oscillator stabilization diagram
7 -2
Chapter7. Reset Function
RESET
INTERNAL
RESET
ADDR. BUS
SP
SP-1
INTERNAL
DATA BUS
SP-2
FFFE FFFF
FE
LSB
MSB
VECTOR VECTOR
Fig. 7.3 Reset Timing by Diagram
7 -3
NEW PC
Chapter7. Reset Function
7.3 Low Voltage Detection Mode
7.3.1 Low voltage detection condition
An on board voltage comparator checks that VDD is at the required level to ensure
correct operation of the device. If VDD is below a certain level, Low voltage detector
forces the device into low voltage detection mode.
7.3.2 Low Voltage Detection Mode
There is no power consumption except stop current, stop mode release function is
disabled. All I/O port is configured as input mode and Data memory is retained until
voltage through external capacitor is worn out. In this mode, all port can be selected with
Pull-up resistor by Mask option. If there is no information on the Mask option sheet ,the
default pull up option (all port connect to pull-up resistor ) is selected.
7.3.3 Release of Low Voltage Detection Mode
Reset signal result from new battery(normally 3V) wakes the low voltage detection mode
and come into normal reset state. It depends on user whether to execute RAM clear
routine or not.
Low Voltage (V)
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0¡É
10¡É
20¡É
30¡É
40¡É
50¡É
60¡É
Temperature(¡É)
Fig 7.5 Low Voltage vs Temperature
7 -4
70¡É
Chapter7. Reset Function
* SRAM BACK-UP after Low Voltage Detection.
3.0V
about hours depend on Vcc-Gnd Capacitor
MCU OPR.
Voltage
Low Voltage Detection
point
Power On Reset
( SRAM retention)
1.8V(TYP)
( 20¡É)
Power On Reset
( SRAM unstable )
0.7V(VRET)
* SRAM Data Backup
0V
User
Removes
Batteries
* The operation after Low voltage detection
Interrupt
: disable
Stop release : disable
All I/O port : input Mode
Remout port : Low Level
OSC
: STOP
All I/O port pull-up ON (Mask Option )
SRAM Data retention
User
Replace
Batteries
* S/W flow chart example after Reset using SRAM Back-up
RESET
Stack Pointer initialize
Check the SRAM value
(RAM Pattern, Check sum..)
SRAM DATA IS VALID?
N
Y
Use saved SRAM
value
7 -5
Clear All Ram area
OVERVIEW
1
FUNCTION DESCRIPTION
2
I/O PORT
3
PERIPHERAL HARDWARE
4
INTERRUPT
5
STANDBY FUNCTION
6
RESET FUNCTION
7
APPENDIX A.
8
APPENDIX B.
9
Appendix A. Instruction Set Table
APPENDIX A. INSTRUCTION SET TABLE
No.
MNEMONIC
OP CODE Words
Exec.
Cycle
Flag
MVG HIZC
OPERATION
1
2
3
4
5
6
7
8
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
#imm
dp
dp+X
!abs
!abs+Y
[dp+X]
[dp]+Y
{X}
04
05
06
07
15
16
17
14
2
2
2
3
3
2
2
1
2
3
4
4
5
6
6
3
A = A + op + C
¡È
¡È
¡È
¡È
¡È
¡È
¡È
N
N
N
N
N
N
N
N
V
V
V
V
V
V
V
V
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
H
H
H
H
H
H
H
H
.
.
.
.
.
.
.
.
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C
C
C
C
C
C
9
10
11
12
13
14
15
16
AND
AND
AND
AND
AND
AND
AND
AND
#imm
dp
dp+X
!abs
!abs+Y
[dp+X]
[dp]+Y
{X}
84
85
86
87
95
96
97
94
2
2
2
3
3
2
2
1
2
3
4
4
5
6
6
3
A = A & op
¡È
¡È
¡È
¡È
¡È
¡È
¡È
N
N
N
N
N
N
N
N
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
Z
Z
Z
Z
Z
Z
Z
Z
.
.
.
.
.
.
.
.
17
18
19
20
ASL
ASL
ASL
ASL
A
dp
dp+X
!abs
08
09
19
18
1
2
2
3
2
4
5
5
op = op << 1
¡È
¡È
¡È
N
N
N
N
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
Z
Z
Z
Z
C
C
C
C
21
22
BBC
BBC
A.bit, rel
dp.bit, rel
y2
y3
2
3
4/6
5/7
if (bit = 0)
then branch
. . . . . . . .
. . . . . . . .
23
24
BBS
BBS
A.bit, rel
dp.bit, rel
x2
x3
2
3
4/6
5/7
if (bit = 1)
then branch
. . . . . . . .
. . . . . . . .
25
26
27
BCC
BCS
BEQ
rel
rel
rel
50
D0
F0
2
2
2
2/4
2/4
2/4
if (C=0) branch
if (C=1) branch
if (Z=1) branch
. . . . . . . .
. . . . . . . .
. . . . . . . .
28
29
BIT
BIT
dp
!abs
0C
1C
2
3
4
5
Z = A & op
¡È
NN. . . . Z .
NN. . . . Z .
30
31
32
33
BMI
BNE
BPL
BRA
rel
rel
rel
rel
90
70
10
2F
2
2
2
2
2/4
2/4
2/4
4
if (N=1) branch
if (Z=0) branch
if (N=0) branch
Branch
.
.
.
.
34
BRK
0F
1
8
S/W interrupt
. . . 1 . 0 . .
35
36
BVC
BVS
rel
rel
30
B0
2
2
2/4
2/4
if (V=0) branch
if (V=1) branch
. . . . . . . .
. . . . . . . .
37
38
CLR1
CLRA1
dp.bit
A.bit
y1
2B
2
2
4
2
op.bit = 0
¡È
. . . . . . . .
. . . . . . . .
39
40
41
CLRC
CLRG
CLRV
20
40
80
1
1
1
2
2
2
C=0
G=0
V=0
. . . . . . . 0
. . 0 . . . . .
. 0 . . 0 . . .
A -1
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
Appendix A. Instruction Set Table
No.
MNEMONIC
OP CODE Words
Exec.
Cycle
Flag
MVG HIZC
OPERATION
42
43
44
45
46
47
48
CMP
CMP
CMP
CMP
CMP
CMP
CMP
#imm
dp
dp+X
!abs
!abs+Y
[dp+X]
[dp]+Y
44
45
46
47
55
56
57
2
2
2
3
3
2
2
2
3
4
4
5
6
6
49
CMP
{X}
54
1
3
50
COM
dp
2C
2
4
dp = dp
N. . . . . Z .
51
52
53
CMPX
CMPX
CMPX
#imm
dp
!abs
5E
6C
7C
2
2
3
2
3
4
Compare X, op
¡È
¡È
N. . . . . Z C
N. . . . . Z C
N. . . . . Z C
54
55
56
CMPY
CMPY
CMPY
#imm
dp
!abs
7E
8C
9C
2
2
3
2
3
4
Compare Y, op
¡È
¡È
¡È
N. . . . . Z C
N. . . . . Z C
N. . . . . Z C
57
58
DAA
DAS
DF
CF
1
1
3
3
59
60
61
62
63
64
DEC
DEC
DEC
DEC
DEC
DEC
A8
A9
B9
B8
AF
BE
1
2
2
3
1
1
2
4
5
5
2
2
65
DIV
9B
1
12
op = op -1
¡È
¡È
¡È
¡È
¡È
Q:A, R:Y ¡ç YA/X
66
67
DI
EI
60
E0
1
1
3
3
I=0
I=1
. . . . . 0 . .
. . . . . 1 . .
68
69
70
71
72
73
74
75
EOR
EOR
EOR
EOR
EOR
EOR
EOR
EOR
#imm
dp
dp+X
!abs
!abs+Y
[dp+X]
[dp]+Y
{X}
A4
A5
A6
A7
B5
B6
B7
B4
2
2
2
3
3
2
2
1
2
3
4
4
5
6
6
3
A = A + op
¡È
¡È
¡È
¡È
¡È
¡È
¡È
N
N
N
N
N
N
N
N
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
Z
Z
Z
Z
Z
Z
Z
Z
.
.
.
.
.
.
.
.
76
77
78
79
80
81
INC
INC
INC
INC
INC
INC
A
dp
dp + X
!abs
X
Y
88
89
99
98
8F
9E
1
2
2
3
1
1
2
4
5
5
2
2
OP = OP + 1
¡È
¡È
¡È
¡È
¡È
N
N
N
N
N
N
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
Z
Z
Z
Z
Z
Z
C
C
C
C
C
C
82
83
84
JMP
JMP
JMP
!abs
[!abs]
[dp]
1B
1F
3F
3
3
2
3
5
4
Branch
. . . . . . . .
. . . . . . . .
. . . . . . . .
85
86
CALL
CALL
!abs
[dp]
3B
5F
3
2
8
8
Subroutine call
¡È
87
88
PCALL
TCALL
upage
n
4F
nA
2
1
6
8
A
dp
dp + X
!abs
X
Y
A -2
Compare A, op
¡È
¡È
¡È
¡È
¡È
¡È
¡È
Dec. adjustment (Add)
Dec. adjustment (Sub)
¡È
¡È
¡È
¡È
N
N
N
N
N
N
N
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
Z
Z
Z
Z
Z
Z
Z
C
C
C
C
C
C
C
N. . . . . Z C
N. . . . . Z C
N. . . . . Z C
N
N
N
N
N
N
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
Z
Z
Z
Z
Z
Z
C
C
C
C
C
C
NV . . H. Z .
. . . . . . . .
. . . . . . . .
. . . . . . . .
. . . . . . . .
Appendix A. Instruction Set Table
No.
MNEMONIC
OP CODE Words
Exec.
Cycle
Flag
MVG HIZC
OPERATION
89
90
91
92
93
94
95
96
97
LDA
LDA
LDA
LDA
LDA
LDA
LDA
LDA
LDA
#imm
dp
dp+X
!abs
!abs+Y
[dp+X]
[dp]+Y
{X}
{X}+
C4
C5
C6
C7
D5
D6
D7
D4
DB
2
2
2
3
3
2
2
1
1
2
3
4
4
5
6
6
3
4
A = op
¡È
¡È
¡È
¡È
¡È
¡È
¡È
A = op, X = X+1
N
N
N
N
N
N
N
N
N
98
LDM
dp, #imm
E4
3
5
dp = #imm
. . . . . . . .
99
100
101
102
LDX
LDX
LDX
LDX
#imm
dp
dp+Y
!abs
1E
CC
CD
DC
2
2
2
3
2
3
4
4
X = op
N
N
N
N
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
Z
Z
Z
Z
.
.
.
.
103
104
105
106
LDY
LDY
LDY
LDY
#imm
dp
dp+X
!abs
3E
C9
D9
D8
2
2
2
3
2
3
4
4
N
N
N
N
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
Z
Z
Z
Z
.
.
.
.
107
108
109
110
LSR
LSR
LSR
LSR
A
dp
dp + X
!abs
48
49
59
58
1
2
2
3
2
4
5
5
op = op >>1
¡È
¡È
¡È
N
N
N
N
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
Z
Z
Z
Z
C
C
C
C
111
MUL
5B
1
9
YA = Y * A
N. . . . . Z .
112
NOP
FF
1
2
No operation
. . . . . . . .
113
114
115
116
117
118
119
120
OR
OR
OR
OR
OR
OR
OR
OR
#imm
dp
dp+X
!abs
!abs+Y
[dp+X]
[dp]+Y
{X}
64
65
66
67
75
76
77
74
2
2
2
3
3
2
2
1
2
3
4
4
5
6
6
3
A = A : op
¡È
¡È
¡È
¡È
¡È
¡È
¡È
N
N
N
N
N
N
N
N
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
Z
Z
Z
Z
Z
Z
Z
Z
.
.
.
.
.
.
.
.
121
122
123
124
PUSH
PUSH
PUSH
PUSH
A
X
Y
PSW
0E
2E
4E
6E
1
1
1
1
4
4
4
4
Push op, SP = SP - 1
¡È
¡È
¡È
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
125
126
127
128
POP
POP
POP
POP
A
X
Y
PSW
0D
2D
4D
6D
1
1
1
1
4
4
4
4
Pop op, SP = SP + 1
¡È
¡È
¡È
. . . . . . . .
. . . . . . . .
. . . . . . . .
(restored)
129
130
131
132
ROL
ROL
ROL
ROL
A
dp
dp+X
!abs
28
29
39
38
1
2
2
3
2
4
5
5
op = op << 1, with C
¡È
¡È
¡È
N
N
N
N
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
Z
Z
Z
Z
C
C
C
C
133
134
135
136
ROR
ROR
ROR
ROR
A
dp
dp+X
!abs
68
69
79
78
1
2
2
3
2
4
5
5
op = op >> 1, with C
¡È
¡È
¡È
N
N
N
N
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
Z
Z
Z
Z
C
C
C
C
¡È
¡È
¡È
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
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.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
Z
Z
Z
Z
Z
Z
Z
Z
Z
.
.
.
.
.
.
.
.
.
Y = op
A -3
¡È
¡È
¡È
Appendix A. Instruction Set Table
No.
MNEMONIC
137
138
RETI
RET
139
140
141
142
143
144
145
146
SBC
SBC
SBC
SBC
SBC
SBC
SBC
SBC
147
148
SETI
SETA1
149
150
SETC
SETG
151
152
153
154
155
156
157
158
STA
STA
STA
STA
STA
STA
STA
STA
159
STOP
160
161
162
STX
STX
STX
163
164
165
STY
STY
STY
166
167
TAX
TAY
168
TST
169
170
171
172
OP CODE Words
Exec.
Cycle
Flag
MVG HIZC
OPERATION
7F
6F
1
1
6
5
Interrupt end
Subroutine end
(restored)
. . . . . . . .
#imm
dp
dp+X
!abs
!abs+Y
[dp+X]
[dp]+Y
{X}
24
25
26
27
35
36
37
34
2
2
2
3
3
2
2
1
2
3
4
4
5
6
6
3
A = A - op - C
¡È
¡È
¡È
¡È
¡È
¡È
¡È
N
N
N
N
N
N
N
N
dp.bit
A.bit
x1
0B
2
2
4
2
op.bit = 1
¡È
. . . . . . . .
. . . . . . . .
A0
C0
1
1
2
2
C=1
G=1
. . . . . . . 1
. . 1 . . . . .
E5
E6
E7
F5
F6
F7
F4
FB
2
2
3
3
2
2
1
1
4
5
5
6
7
7
4
4
op = A
¡È
¡È
¡È
¡È
¡È
¡È
op = A, X=X+1
.
.
.
.
.
.
.
.
EF
1
3
CPU, OSC stop
. . . . . . . .
dp
dp+Y
!abs
EC
ED
FC
2
2
3
4
5
5
op = X
¡È
¡È
. . . . . . . .
. . . . . . . .
. . . . . . . .
dp
dp+X
!abs
E9
F9
F8
2
2
3
4
5
5
op = Y
¡È
¡È
. . . . . . . .
. . . . . . . .
. . . . . . . .
E8
9F
1
1
2
2
X= A
Y=A
N. . . . . Z .
N. . . . . Z .
4C
2
3
Test dp = 0 or not
N. . . . . Z .
TSPX
TXA
TXSP
TYA
AE
C8
8E
BF
1
1
1
1
2
2
2
2
X = SP
A=X
SP = X
A=Y
N
N
.
N
173
174
XAX
XAY
EE
DE
1
1
4
4
A ¡ê X
A ¡ê Y
. . . . . . . .
. . . . . . . .
175
XCN
CE
1
5
A7-4 A3-0
N. . . . . Z .
176
177
178
XMA
XMA
XMA
BC
AD
BB
2
2
1
5
6
5
A ¡ê op
¡È
¡È
N. . . . . Z .
N. . . . . Z .
N. . . . . Z .
179
XYX
FE
1
4
X ¡ê Y
. . . . . . .
dp
dp+X
!abs
!abs+Y
[dp+X]
[dp]+Y
{X}
{X}+
dp
dp
dp+X
{X}
A -4
V
V
V
V
V
V
V
V
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
H
H
H
H
H
H
H
H
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
Z
Z
Z
Z
Z
Z
Z
Z
.
.
.
.
.
.
.
.
Z
Z
.
Z
C
C
C
C
C
C
C
C
.
.
.
.
.
.
.
.
.
.
.
.
Appendix A. Instruction Set Table
No.
MNEMONIC
OP CODE Words
Exec.
Cycle
180
181
182
183
184
185
186
LDYA
STYA
INCW
DECW
ADDW
SUBW
CMPW
dp
dp
dp
dp
dp
dp
dp
7D
DD
9D
BD
1D
3D
5D
2
2
2
2
2
2
2
5
5
6
6
5
5
4
187
188
CBNE
CBNE
dp, rel
dp+X, rel
FD
8D
3
3
189
190
DBNE
DBNE
dp, rel
Y, rel
AC
7B
191
NOT1
M.bit
192
193
OR1
OR1B
194
195
Flag
MVG HIZC
OPERATION
YA = (dp+1)(dp)
(dp+1)(dp) = YA
(dp+1)(dp)++
(dp+1)(dp)-YA + (dp+1)(dp)
YA - (dp+1)(dp)
CP YA, (dp+1)(dp)
N
.
N
N
N
N
N
5/7
6/8
if (op !=A)
then branch
. . . . . . . .
. . . . . . . .
3
2
5/7
4/6
Dec op, if (Z=0)
then branch
. . . . . . . .
. . . . . . . .
4B
3
5
M.bit = M.bit
. . . . . . . .
M.bit
M.bit
6B
6B
3
3
5
5
C = M.bit : C
C = (M.bit) : C
. . . . . . . C
. . . . . . . C
AND1
AND1B
M.bit
M.bit
8B
8B
3
3
4
4
C = M.bit & C
C = (M.bit) & C
. . . . . . . C
. . . . . . . C
196
197
EOR1
EOR1B
M.bit
M.bit
AB
AB
3
3
5
5
C= M.bit + C
C = (M.bit) + C
. . . . . . . C
. . . . . . . C
198
199
LDC
LDCB
M.bit
M.bit
CB
CB
3
3
4
4
C = M.bit
C = (M.bit)
. . . . . . . C
. . . . . . . C
200
STC
M.bit
EB
3
6
M.bit = C
. . . . . . . .
201
TCLR1
!abs
5C
3
6
!abs = A & !abs
N. . . . . Z .
202
TSET1
!abs
3C
3
6
!abs = A : !abs
N. . . . . Z .
A -5
.
.
.
.
V
V
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. .
. .
. .
. .
H.
H.
. .
Z
.
Z
Z
Z
Z
Z
.
.
.
.
C
C
C
OVERVIEW
1
FUNCTION DESCRIPTION
2
I/O PORT
3
PERIPHERAL HARDWARE
4
INTERRUPT
5
STANDBY FUNCTION
6
RESET FUNCTION
7
APPENDIX A.
8
APPENDIX B.
9
Appendix B. PROGRAMMER`S GUIDE
APPENDIX B.
General Circuit Diagram of GMS810series.
VCC
R14 24
2 R12
R15 23
3 R11
R16 22
4 R10
R17 21
6 Xout
7 Xin
8 R00
9 R01
GMS 81016
OSC
RESET 19
TEST
0.1uF
TR1
vcc
18
VCC
R07 17
R06 16
10 R02
R05 15
11 R03
R04 14
12 R20
VSS 13
VCC
Indicator LED
Normally use the above 100uF
capacitor for prevent power drop
during pulse is transmitted.
If you use the SRAM back-up,
use at least 220uF
REMOUT 20
Filter for Vcc-GND
noise
0.1uF
5 VDD
4MHz
Infrared LED
220uF
1 R13
DC3V
We recommend to
use ALKALINE battery.
GND
R12
R11
R10
41
33 25
17
9
1
R00
50
42
34 26
18
10
2
R01
51
43
35 27
19
11
3
R02
52
44
36 28
20
12
4
R03
53
45
37 29
21
13
5
R04
54
46
38 30
22
14
6
R05
55
47
39 31
23
15
7
R06
56
48
40 32
24
16
8
R07
R13
B -1
R14
B-1 Circuit Diagram
R15
= KEY
R16
KEY MATRIX
49
Appendix B. PROGRAMMER`S GUIDE
Mask Option List Example Refer to Circuit B-1
GMS810 MASK OPTION LIST
HYUNDAI ELCTRONICS Co., Ltd.
MCU Application Team.
Code Name : GMS81016 - UAxxx
1. Device & Package
GMS81004
GMS81008
GMS81016
20PIN : SOP
24PIN : SOP
28PIN : SOP
44PIN : PLCC
Please enter check marks as
GMS81024
GMS81032
PDIP
Skinny DIP
Skinny DIP
2. Inclusion of Pull up Resistor
Y : Yes
N : No
- R0 PORT
Port
Y/N
Y/N
R00
R01
R02
R03
R04
R05
R06
R07
y
y
y
y
y
y
y
y
R10
R11
R15*2
R16
R17
n
n
n
n
n
*0
Y : Yes
N : No
- R1 PORT
Port
Y/N
Y/N
R12*2 R13*2 R14*2
n
n
n
*0
Y : Yes
N : No
- R2 PORT
Port
Y/N
Y/N
B-1 ,Circuit Description:
device : GMS81016
package : 24PIN SOP
port R0x : All input port with pull-up resistor
port R1x : All output port with N-MOS
Open drain
port R20 : LED Drive port
R20
R21*1 R22*1 R23*1 R24*1
n
*0
< NOTICE >
. *0 : is only available in Low Voltage detection Option = Y (No . 3)
*1 : is not available for 20PIN & 24PIN. So, Default option is Pull-Up.
. *2 : is not available for 20PIN. So, Default Option is Pull-Up.
3. Low Voltage Detection
Y/N
n
Date
:
Company Name
Section Name
:
:
Signature
:
S/W example Refer to Circuit B-1
; Example program for Port setting.
ORG 0C000H
Reset :
clrg
ldx
#0feh
txsp
DI
ldm R2dd,#0001_1111b
ldm R2,#1111_1111b
ldm R1odc,#1111_1111b
ldm R1dd,#1111_1111b
ldm R1,#0000_0000b
ldm R0dd,#0000_0000b
ldm smrr0,#1111_1111b
ldm smrr1,#0000_0000b
ldm Ienh,#1000_0000b
ldm ckctlr,#0001_1101b
clr1 IRQKSCN
STOP
NOP
ldm R1,#1111_1111b
; GMS81016 Program Start Address
; Clear G-Flag
; Stack Pointer Initialize
; Interrupt disable
; R2 direction setting,R20: Output
; R2 data setting , R20 : High,Led off
; R1 port all open drain
; R1 direction setting ,All output
; R1 data setting , all Low for key scan
; R0 direction setting ,All input
; Stop mode release by R0
; Stop disable by R1
; Key scan interrupt setting
; Ckctlr setting for 16mS time delay after
; release from stop mode, WDT disable.
; key scan interrupt request flag clear
; `NOP instruction must to be used after
; Stop instruction
B -2
Appendix B. PROGRAMMER`S GUIDE
Key Scan
- To secure the key board scanning , read the input port after minimum 60uS delay time from
output port set to `Low `. This time delay is for the port rising time depend on the
input pull-up resistor .
; program example ,See the circuit B-1
.
ldm R1,#1111_1110b
call delay_60uS
lda R0
.
.
;R10 port set to LOW
;60uS time delay routine
;R0 port Read
R0 port Read timing
R10
R11
60uS
60uS
Fig B-2 , Input with pull-up port read time method
B -3
GMS810 MASK OPTION LIST
HYUNDAI ELECTRONICS Co., Ltd.
MCU Application Team.
Code Name :
1. Device & Package
GMS81004
GMS81008
GMS81016
GMS81024
GMS81032
20PIN : SOP
24PIN : SOP
28PIN : SOP
44PIN : PLCC
PDIP
Skinny DIP
Skinny DIP
Please enter check marks as
2. Inclusion of Pull up Resistor
- R0 PORT
Port
Y/N
Y/N
R00
R01
R02
R06
R07
Y : Yes
N : No
R10
R11
R12*2 R13*2 R14*2 R15*2 R16
R17
Y : Yes
N : No
R20
R21*1 R22*1 R23*1 R24*1
R03
R04
R05
*0
- R1 PORT
Port
Y/N
Y/N
*0
- R2 PORT
Port
Y/N
Y/N
Y : Yes
N : No
*0
< NOTICE >
. *0 : is only available in .Low Voltage detection Option = Y ( No. 3 )
*1 : is not available for 20PIN & 24PIN. So, Default Option is Pull-Up.
. *2 : is not available for 20PIN. So Default Option is Pull-Up.
3. Low Voltage Detection
Y/N
Date
:
Company Name :
Section Name
:
Signature
:
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