INTERSIL HIP5061DS

HIP5061
7A, High Efficiency Current
Mode Controlled PWM Regulator
April 1994
Features
Description
• Single Chip Current Mode Control IC
The HIP5061 is a complete power control IC, incorporating
both the high power DMOS transistor, CMOS logic and low
level analog circuitry on the same Intelligent Power IC. The
standard “Boost”, “Buck-Boost”, “Cuk”, “Forward”, “Flyback”
and the “SEPIC” (Single-Ended Primary Inductance Converter) power supply topologies may be implemented with
this single control IC.
• 60V, On-Chip DMOS Power Transistor
• Thermal Protection
• Over-Current Protection
• 250kHz Operation
Over-temperature and rapid short-circuit recovery circuitry is
incorporated within the IC. These protection circuits disable
the drive to the power transistor to protect the transistor and
insure rapid restarting of the supply after the short circuit is
removed.
• Output Rise and Fall Times - 10ns
• On-Chip Reference Voltage - 5.1V
• Slope Compensation
• VDD Clamp Allows 10.8V to 60V Supply
As a result of the power DMOS transistors current (7A at 30%
duty cycle, 5A DC) and 60V capability, supplies with output
power over 50W are possible.
• Supply Current Does Not Increase When Power
Device is On
Applications
Ordering Information
• Distributed / Board Mounted Power Supplies
PART
NUMBER
TEMPERATURE
RANGE
PACKAGE
HIP5061DS
0oC to +85oC
7 Lead Staggered “Gullwing” SIP
• DC - DC Converter Modules
• Voltage Inverters
• Small Uninterruptable Power Supplies
• Cascode Switching for Off Line SMPS
Simplified Functional Diagram
Pinout
HIP5061 (SIP)
TOP VIEW
VIN
VOUT
PIN 7 VDD
PIN 6 VG
PIN 5 DRAIN
PIN 4 SOURCE
PIN 3 FB
PIN 2 VC
PIN 1 GND
DO NOT
USE
VG
VDD
DRAIN
HIP5061
VDD CLAMP
SOURCE
(TAB)
CLOCK
CONTROL
LOGIC
GATE
DRIVER
SOURCE
(TAB)
VC
OVER
TEMP
V/I
AMP
FB
2.5V
UNDER
VOLTAGE
SLOPE
COMPENSATION
5.1V
REFERENCE
GND
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
407-727-9207 | Copyright © Intersil Corporation 1999
7-53
File Number
3390.2
Specifications HIP5061
Absolute Maximum Ratings (Note 1)
Thermal Information
DC Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 16V
DC Supply Current, IDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105mA
DMOS Drain Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 60V
Average DMOS Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 5A
DMOS Source Voltage, VSOURCE, TAB . . . . . . . . . . . . -0.1V to 0.1V
DC Supply Voltage, VG . . . . . . . . . . . . . . . . . . . .-0.3V to VDD + 0.3V
Compensation Pin Current, IVC . . . . . . . . . . . . . . . . . -5mA to 35mA
Voltage at All Other Pins. . . . . . . . . . . . . . . . . . .-0.3V to VDD + 0.3V
Operating Junction Temperature Range. . . . . . . . . . . 0oC to +105oC
Storage Temperature Range . . . . . . . . . . . . . . . . . -55oC to +150oC
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2 - 2KV
Single Pulse Avalanche Energy Rating, µs (Note 2) . . . EAS 100mJ
Thermal Resistance
θJC
Plastic SIP Package . . . . . . . . . . . . . . . . . . . . . . . .
2oC/W
Maximum Package Power Dissipation at +85oC
(Depends Upon Mounting, Heat Sink and Application) . . . . . 10W
Max. Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . +105oC
(Controlled By Thermal Shutdown Circuit)
Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +265oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
SYMBOL
VDD = VG =12V, VC = 5V, VFB = 5.1V, SOURCE = GND = DRAIN = 0V, TJ = 0oC to +105oC,
Unless Otherwise Specified
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
DEVICE PARAMETERS
IDD
Quiescent Supply Current
VDD = VG = 13.2V, VC = 0V,
VFB = 4V
6
12
18
mA
IDD
Operating Supply Current
VDD = VG = 13.2V, VC = 8.5V, VFB = 4V
-
24
31
mA
IVG
Quiescent Current to Gate Driver
VDD = VG = 13.2V, VC = 0V
-
0
10
µA
IVG
Operating Current to Gate Driver
VC = 3V
-
1
2
mA
VDDC
Clamp Voltage
IDD = 100mA
13.3
14
15
V
VREF
Reference Voltage
IVC = 0µA, VC = VFB
5.0
5.1
5.2
V
Input Current
VFB = VREF
-
-0.85
0.5
µA
gm (VFB)
VFB Transconductance
IVC /(VFB - VREF)
/IVC / = 500µA, Note 3
20
30
43
mS
IVCMAX
Maximum Source Current
VFB = 4.6V
-4
-1.8
-1
mA
IVCMAX
Maximum Sink Current
VFB = 5.6V
1
1.8
4
mA
Voltage Gain
/IVC / = 500µA, Note 3
44
50
-
dB
AMPLIFIERS
|IFB|
AOL
VCMAX
Short Circuit Recovery Comparator Rising Threshold Voltage
5.4
6.6
8.9
V
VCHYS
Short Circuit Recovery
Comparator Hysteresis Voltage
0.7
1.1
1.8
V
0
10
25
mA
210
250
290
kHz
IVCOVER
VC Over-Voltage Current
VDD = VG = 10.8V, VC = VCMAX
CLOCK
fq
Internal Clock Frequency
DMOS TRANSISTOR
rDS(ON)
Drain-Source On-State
Resistance
IDRAIN = 5A, VDD = VG = 10.8V
TJ = +25oC
-
0.15
0.22
Ω
rDS(ON)
Drain-Source On-State
Resistance
IDRAIN = 5A, VDD = VG = 10.8V
TJ = +105oC
-
-
0.33
Ω
IDSS
Drain-Source Leakage Current
VDRAIN = 60V
-
0.5
10
µA
IDSH
Average Drain Short Circuit
Current
VDRAIN = 5V, Note 4
-
-
5
A
DRAIN Capacitance
Note 4
-
200
-
pF
CDRAIN
7-54
Specifications HIP5061
Electrical Specifications
SYMBOL
VDD = VG =12V, VC = 5V, VFB = 5.1V, SOURCE = GND = DRAIN = 0V, TJ = 0oC to +105oC,
Unless Otherwise Specified (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
CURRENT CONTROLLED PWM
gm(VC)
∆IDRAIN, PEAK /∆VC
Note 3
1.4
2.2
3.0
A/V
V/IREF
Voltage to Current Converter Reference Voltage
IDRAIN = 0.25A, Note 3
2.4
2.8
3.1
V
Current Comparator Blanking
Time
Note 3
40
100
175
ns
tONMIN
Minimum DMOS “ON” Time
Note 3
60
150
250
ns
tOFFMIN
Minimum DMOS “OFF” Time
Note 3
40
125
200
ns
MinCI
Minimum Controllable DMOS
Peak Current
Note 3
-
100
250
mA
MaxCI
Maximum Controllable DMOS
Peak Current
Duty Cycle = 6% to 30%, Note 3
7
9.5
12
A
MaxCI
Maximum Controllable DMOS
Peak Current
Duty Cycle = 30% to 96%, Note 3
5
8
12
A
tBT
CURRENT COMPENSATION RAMP
∆I/∆t
Compensation Ramp Rate
∆IDRAIN, PEAK /∆Time, Note 3
-1.4
-0.85
-0.45
A/µs
tRD
Compensation Ramp Delay
Note 3
1.3
1.5
1.8
µs
VDDMIN
Rising VDD Threshold Voltage
VFB = 4V
9.3
10.3
10.8
V
VDDHYS
Power-On Hysteresis
VFB = 4V
0.3
0.45
0.6
V
1.0
1.5
2.0
V
4V < VDD < 10.8V, VC = 0.8V
50
500
3000
Ω
Substrate Temperature for
Thermal Monitor to Trip
Note 4
105
-
145
oC
Temperature Hysteresis
Note 4
-
5
-
START-UP
VCEN
Enable Comparator Threshold
Voltage
RVC
Power-Up Resistance
THERMAL MONITOR
TJ
TJHY
o
NOTES:
1. All Voltages relative to pin 1, GND.
2. VD = 10V, Starting TJ = +25oC, L = 4mH, IPEAK = 7A.
3. Test is performed at wafer level only.
4. Determined by design, not a measured parameter.
TABLE 1.
CONDITIONS FOR UNCLAMPED ENERGY CIRCUIT
VD (V)
IL
(PEAK AMPS)
L (mH)
EAS (mJ)
10
5
40
550
NOTE:
10
7
4TZ
120
6
10
0.33
18
6
12.5
0.14
12
7
HIP5061
L
IL
+
VD
-
1
VARY tP TO OBTAIN
REQUIRED PEAK IL
12V
Device Selected to Obtain Peak Current without Clocking
tP
FIGURE 1. UNCLAMPED ENERGY TEST CIRCUIT
7-55
C
HIP5061
Definitions of Electrical Specifications
Refer to the Functional Block Diagram of Figure 1 for locations of functional blocks and devices.
Device Parameters
IDD , Quiescent Supply Current - Supply current with the
chip disabled. The Clock, Error Amplifier, Voltage-to-Current
Converter, and Current Ramp circuits draw only quiescent
current. The supply voltage must be kept lower than the
turn-on voltage of the VDD clamp or else the supply current
increases dramatically.
IDD , Operating Supply Current - Supply current with the
chip enabled. The Error Amplifier is drawing its maximum
current because VFB is less than its reference voltage. The
voltage-to-current amplifier is drawing its maximum because
VC is at its maximum. The ramp circuit is drawing its maximum because it is not being disabled by the DMOS transistor turning off.
IVG , Quiescent Gate Driver Current - Gate Drivers supply
current with the IC disabled. The Gate Driver is not toggling
and so it draws only leakage current.
IVG , Operating Gate Driver Current - Gate Drivers supply
current with the IC enabled. The DMOS transistor drain is
loaded with a large resistor tied to 60V so that it is swinging
from 0V to 60V during each cycle.
VDDC , VDD Clamp - VDD voltage at the maximum allowed
current through the VDD Clamp.
VREF , Reference Voltage - The voltage on FB that sets the
current on VC to zero. This is the reference voltage for the
DC/DC converter.
Amplifiers
|IFB|, Input Current - Current through FB pin when it is at its
normal operating voltage. This current must be considered
when connecting the output of a DC/DC convertor to the FB
pin via a resistor divider.
gm(VFB), Transconductance - The change in current
through the VC pin divided by the change in voltage on FB.
The gm times the resistance between VC and ground gives
the voltage gain of the Error Amplifier.
IVCMAX , Maximum Source Current - The current on VC
when FB is more than a few hundred millivolts less than
VREF .
IVCMAX , Maximum Sink Current - The current on VC when
FB is more than a few hundred millivolts more than VREF .
VCHYS , VCMAX Hysteresis - The voltage on VC that causes
the NMOS transistor to turnoff if it had been turned on by VC
exceeding VCMAX. At this voltage the current out of the Voltageto-Current Converter is at roughly three quarters of full-scale.
IVCOVER , VC Over-Voltage Current - The current drawn
through the VC pin after the NMOS transistor is turned on
due to excessive voltage on VC . The NMOS transistor connected to the VC pin draws more than enough current to
overcome the full scale source current of the Error Amplifier.
Clock
fq, Frequency - The frequency of the DC/DC converter. The
Clock actually runs faster than this value so that various control signals can be internally generated.
DMOS Transistor
rDS(ON) , “On” Resistance - Resistance from DMOS transistor Drain to Source at maximum drain current and minimum
Gate Driver voltage, VG .
IDSS , Leakage Current - Current through DMOS transistor
at the Maximum Rated Voltage.
Current Controlled PWM
gm(VC), Transconductance - The change in the DMOS transistor peak drain current divided by the change in voltage on
VC . When analyzing DC/DC converters the DMOS transistor
and the inductor tied to the drain are sometimes modelled as
a voltage-controlled current source and this parameter is the
gain of the voltage-controlled current source.
V/IREF , Current Control Threshold - The voltage on VC
that causes the DMOS transistor to shut off at the minimum
controllable current. This voltage is greater than the Enable
Comparator Threshold (VCEN) so that as VC rises the IC
does not jump from the disabled state to the DMOS transistor conducting a large current.
tBT , Blanking Time - At the beginning of each cycle there is
a blanking time that the DMOS transistor turns-on and stayson no matter how high drain the current. This blanking time
permits ringing in the external parasitic capacitances and
inductances to dampen and for the charging of the reverse
bias on the rectifier diode.
tONMIN , Minimum DMOS Transistor “On” Time - The minimum on-time for the DMOS transistor where small changes
in the VC voltage make predictable changes in the DMOS
transistor peak current. Converters should be designed to
avoid requiring pulse widths less than the minimum on time.
AOL , Voltage Gain - Change in the voltage on VC divided by
the change in voltage on FB. There is no resistive load on
VC . This is the voltage gain of the error amplifier when gm
times load resistance is larger than this gain.
tOFFMIN , Minimum DMOS Transistor “Off” Time - The minimum off-time for the DMOS transistor that allows enough time
for the IC to get ready for the next cycle. Converters should be
designed to avoid requiring pulse widths so large that the minimum off time is violated. (However, zero off time is allowed, that
is, the DMOS transistor can stay on from one cycle to the next.)
VCMAX , VC Rising Threshold - The voltage on VC that
causes the Voltage-to-Current Amplifier to reach full-scale.
When VC reaches this voltage, the VC NMOS transistor (transistor with its drain connected to the VC pin in the Functional
Block Diagram of Figure 2) turns on and tries to lower the voltage on VC .
MinCI, Minimum Controllable Current - When the voltage
on VC is below V/IREF , the peak current for the DMOS transistor is too small for the Current Comparator to operate reliably. Converters should be designed to avoid operating the
DMOS transistor at this low current.
7-56
HIP5061
VCEN , Enable Comparator Threshold Voltage - The minimum voltage on VC needed to enable the IC. The IC can be
shutdown from an open-collector logic gate by pulling down
the VC pin to GND.
MaxCI, Maximum Controllable Current - The peak current
for the DMOS transistor when the Voltage-to-Current Converter is at its full scale output. The DMOS transistor current
may exceed this value during the blanking time so proper
precautions should be taken. This parameter is unchanged
for the first 3/8 of the cycle and then decreases linearly with
time because of the Current Ramp becoming active.
RVC , Power - Up Resistance - When VDD is below VDDMIN,
the NMOS transistor connected to the VC pin is turned on to
make sure the VC node is low. Thus the voltage on VC can
gradually build up as will the trip current on the DMOS transistor. This is the only form of “soft start” included on the IC.
The resistance is measured between the VC and GND pins.
Current Compensation Ramp
∆I/∆t, Compensation Ramp Rate - At a given voltage on VC
the DMOS transistor will turn off at some current that stays
constant for about the first 1.5µs of the cycle. After 1.5µs, the
turnoff current starts to linearly decrease. This parameter
specifies the change in the DMOS transistor turnoff current.
Thermal Monitor
TJ , Rising Temperature Threshold - The IC temperature
that causes the IC to disable itself so as to prevent damage.
Proper heat-sinking is required to avoid over-temperature
conditions, especially during start-up when the DMOS transistor may stay on for a long time if an external soft-start circuit is not added.
tRD , Compensation Ramp Delay - The time into each cycle
that the compensation ramp turns on. The Current Compensation Ramp, used for Slope Compensation, is developed by
the Current Ramp block shown in the FUNCTIONAL BLOCK
DIAGRAM of Figure 2.
TJHY , Temperature Hysteresis - The IC must cool down
this much after it is disabled by being too hot before it can
resume normal operation.
Start-Up
VDDMIN , Rising VDD Threshold Voltage - The minimum
voltage on VDD needed to enable the IC.
VDDHYS , Power - On Hysteresis Voltage - The difference
between the voltage on VDD that enables the IC and the voltage that disables the IC.
VDD
7
VG
6
VDD
CLAMP
RAMP RESET
RAMP ENABLE
BAND GAP
REFERENCE
REGULATOR
GND
1
-
10.3V
CURRENT
RAMP
VDD
CLOCK
VREF = 5.1V
+
ERROR
AMP
DISABLE
ERROR
AMP
+
ENABLE
TAB
-
100ns
1.5V
VDD VOLTAGE TO
CURRENT
CONVERTER
+
THERMAL
MONITOR
BLANKING
CURRENT
MONITORING
SOURCE
CURRENT SAMPLE
360Ω
ERROR CURRENT
2KΩ
GATE
DRIVER
VDD MONITOR
2KΩ
5.1V
VREF
DRAIN
5
CONTROL
LOGIC
UNDER VOLTAGE
+
LOCK OUT
ENABLE
VC
2
FB
3
BIAS
CIRCUITS
CURRENT
COMPARE
360Ω
+
LIGHT LOAD
COMPARATOR
INTERNAL LEAD
INDUCTANCE
AND RESISTANCE
SOURCE
4
+
SHORT
CIRCUIT
HIP5061
7.0V
FIGURE 2. FUNCTIONAL BLOCK DIAGRAM OF THE HIP5061
7-57
HIP5061
Pin Description
TERMINAL
NUMBER
DESIGNATION
1
GND
2
VC
The output of the transconductance amplifier appears at this terminal. Input to the internal
voltage to current converter also appears at this node. Transconductance amplifier gain
and loop response are set at this terminal. When the VDD terminal voltage is below the
starting voltage, VDDMIN, this terminal is held low. When the voltage at this terminal
exceeds VCMAX, 7V typical, implying an over-current condition, a typical 10mA current,
IVCOVER pulls this terminal towards ground. This current remains “ON” until the voltage on
the VC terminal falls by VCHYS, typically 1.1V, below the upper threshold, VCMAX. When the
voltage on this terminal falls below VCEN, typically 1.5V, the IC is disabled.
3
FB
Feedback from the regulator output is applied to this terminal. This terminal is the input to
the transconductance amplifier. The amplifier compares the internal 5.1V reference and
the feedback signal from the regulator output.
4
SOURCE
The terminal, labeled TAB, has a connection to this terminal, but because of the long lead
length and resulting high inductance of this terminal, it should not be used as a means of
bypassing. Therefore, this terminal is labeled “Do Not Use.”
5
DRAIN
6
VG
Gate drive supply voltage is provided at this terminal. A 10Ω to 150Ω resistor connected
between this terminal and the VDD terminal provides decoupling and the supply voltage
for the gate drivers.
7
VDD
External supply input to the IC. A nominal 14V shunt regulator is connected between this
terminal and the TAB. A series resistor should be connected to this terminal from the
external voltage source to supply a minimum current of 33mA and a maximum current of
105mA under the worst cast supply voltage. The series resistor is not required if the
supply voltage is 12V, ±10%.
TAB
SOURCE
This is the internal power DMOS transistor Source terminal. It should be used as the
ground return for the VDD bypass capacitor. In addition high frequency bypassing for both
the regulator output load voltage and supply input voltage should be returned to this
terminal.
DESCRIPTION
This is the analog ground terminal of the IC.
Connection to the Drain of the internal power DMOS transistor is made at this terminal.
For more information refer to Application Notes AN9208, AN9212, AN9323.
Foot Print For Soldering
0.523
0.120
OPTIONAL Ø 0.151
LIMIT OF SOLDER MASK
FOR HEADER
0.050 TYP
0.212
0.424
0.050 TYP
0.480
0.575
0.675
TO-220 STAGGERED GULL WING SIP
7-58
0.080 TYP
HIP5061
26
20
24
18
22 OPERATING CURRENT, VDD = VG = 13.2V, VC = 8.5V, VFB = 4V
16
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
Typical Performance Curves
20
18
16
14
QUIESCENT CURRENT, VDD = VG = 13.2V, VC = 0V, VFB = 4V
12
10
12
10
8
6
4
2
8
0
6
0
10
20
30
40
50
60
70
AMBIENT TEMPERATURE (oC)
80
90
0
100
2
3
4
24
1.0
22
SUPPLY CURRENT (mA)
26
1.1
0.9
VDD = VG = 12V, VFB = 5.1V, VC = 5V
0.7
0.6
0.5
0.4
0
8
VDD = 12V, VFB = 6V
9
10 11
12 13 14
TA = 0oC
20
TA = +105oC
18
16
14
12
10
10
20
30
40
50
60
70
80
90
4
100
0
1
2
3
AMBIENT TEMPERATURE (oC)
5.18
REFERENCE VOLTAGE (V)
5.20
14.8
14.6
IDD = 100mA
14.2
14.0
13.8
13.6
50
60
AMBIENT TEMPERATURE
70
9
10
11
12
5.10
5.08
5.06
5.02
40
8
5.12
5.04
30
7
80
90
100
(oC)
VDD = VG = 12V, IVC = 0µA, VC = VFB
5.14
13.2
20
6
5.16
13.4
10
5
FIGURE 6. TYPICAL SUPPLY CURRENT vs VOLTAGE
AT PIN VC FOR 0oC AND +105oC
15.0
14.4
4
VOLTAGE AT VC PIN (V)
FIGURE 5. TYPICAL GATE DRIVER OPERATING
CURRENT vs TEMPERATURE
CLAMP VOLTAGE (V)
7
6
0.2
0
6
8
0.3
13.0
5
FIGURE 4. TYPICAL SUPPLY CURRENT vs SUPPLY VOLTAGE
1.2
0.8
1
VDD (V)
FIGURE 3. TYPICAL SUPPLY CURRENT vs TEMPERATURE
GATE DRIVER CURRENT (mA)
VFB = VC = 0V, TA = +25oC
14
5.00
0
10
20
30
40
50
60
70
AMBIENT TEMPERATURE (oC)
FIGURE 7. TYPICAL CLAMP VOLTAGE vs TEMPERATURE
FIGURE 8. TYPICAL REFERENCE VOLTAGE vs
TEMPERATURE
7-59
80
90
100
HIP5061
Typical Performance Curves (Continued)
5.20
-50
-55
IVC = 0mA, VC = VFB
5.14
TA = +105oC
5.12
5.10
o
TA = 0 C
5.08
5.06
-70
-75
-80
-85
-90
5.02
-95
-100
11.2
11.6
12.0
12.4
12.8
VDD (V)
13.2
13.6
14.0
FIGURE 9. TYPICAL REFERENCE VOLTAGE vs SUPPLY
VOLTAGE FOR 0oC AND +105oC
0
36
0.4
35
34
VDD = VG = 12V, VC = 4V, TA = +25oC
0.2
0.1
0
-0.1
-0.2
-0.3
-1
0
1
2
3
30
40
50
60
70
AMBIENT TEMPERATURE (oC)
80
90
100
VDD = VG = 12V, IVC = 500µA
33
32
31
30
29
28
27
26
25
22
4 5 6 7 8 9 10 11 12 13 14
VOLTAGE ON FB PIN (V)
FIGURE 11. TYPICAL INPUT CURRENT TO FB PIN vs VFB
0
10
20
30
40
50
60
70
80
90 100
AMBIENT TEMPERATURE (oC)
FIGURE 12. TYPICAL ERROR AMPLIFIER
TRANSCONDUCTANCE vs TEMPERATURE
2.5
2.5
2.0
2.0
VDD = VG = 12V, VC = 4V, TA = +25oC
OUTPUT CURRENT (mA)
1.5
20
24
23
-0.4
-0.5
10
FIGURE 10. TYPICAL INPUT CURRENT TO FB PIN vs
TEMPERATURE
0.5
0.3
INPUT CURRENT (µA)
-65
5.04
5.00
10.8
VC PIN CURRENT (mA)
VDD = VG = 12V, VC = 5V, VFB = VREF
-60
INPUT CURRENT (nA)
5.16
ERROR AMPLIFIER
TRANSCONDUCTANCE (ms)
REFERENCE VOLTAGE (V)
5.18
1.0
0.5
0.0
-0.5
-1.0
-1.5
-2.0
SINKING CURRENT, VFB = 5.6V
1.5
1.0
0.5
VDD = VG = 12V, VC = 5V
0.0
-0.5
-1.0
-1.5
SOURCING CURRENT, VFB = 4.6V
-2.0
-2.5
-175 -150-125-100 -75 -50 -25 0
-2.5 0
25 50 75 100 125 150 175
FIGURE 13. TYPICAL VC PIN CURRENT IVC PIN vs
VOLTAGE ON FB PIN (SHOWS ERROR
AMPLIFIER TRANSCONDUCTANCE)
10
20
30
40
50
60
70
80
90
AMBIENT TEMPERATURE (oC)
VOLTAGE ON FB PIN (mV) CENTERED AROUND 5.1V
FIGURE 14. TYPICAL ERROR AMPLIFIER SINKING AND
SOURCING CURRENT vs TEMPERATURE
7-60
100
HIP5061
Typical Performance Curves (Continued)
12
2.5
VDD = VG = 12V, VC = 4V, TA = +25oC
2.0
VC PIN CURRENT (mA)
VC PIN CURRENT (mA)
VDD = 9V (UNDER VOLTAGE CONDITION)
10
1.5
1.0
0.5
0.0
-0.5
-1.0
-1.5
TA = 0oC
8
TA = +105oC
6
4
2
-2.0
0
-2.5
0
1
2
3 4 5 6 7 8 9
VOLTAGE ON FB PIN (V)
10 11 12 13
FIGURE 15. TYPICAL VC PIN CURRENT vs
VOLTAGE ON FB PIN
16
VDD = 12V, TA = +25oC
14
FB = 6V
VC PIN CURRENT (mA)
12
10
FB = 4V
8
6
4
FB = 6V
2
0
FB = 4V
-2
-4
0
1
2
3
4
5
6
7
8
0
1
2
9
10
11
12
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
FIGURE 17. TYPICAL VC PIN CURRENT vs VOLTAGE ON VC PIN
FOR VOLTAGES ABOVE AND BELOW VREF
8
9
VDD = VG = 12V
VCHYS
0
10
20
30
40
50
60
70
AMBIENT TEMPERATURE (oC)
80
90 100
FIGURE 18. TYPICAL SHORT CIRCUIT COMPARATOR
THRESHOLD VOLTAGE vs TEMPERATURE
3.0
10.5
PERCENT FREQUENCY CHANGE
11.0
OVER-VOLTAGE CURRENT (mA)
7
VCMAX
VOLTAGE ON VC PIN (V)
VDD = VG = 10.8V, VC = VCMAX
10.0
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
3
4
5
6
VOLTAGE ON VC PIN (V)
FIGURE 16. TYPICAL VC PIN CURRENT vs VOLTAGE ON
VC PIN FOR 0oC AND +105oC
THRESOLD AND HYSTERESIS VOLTAGE (V)
-1
2.5
VDD = VG = 12V, VFB = 5.1V
2.0
1.5
1.0
0.5
0.0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
0
10
20
30
40
50
60
70
AMBIENT TEMPERATURE (oC)
80
FIGURE 19. TYPICAL OVER-VOLTAGE CURRENT vs
TEMPERATURE
90
100
0
10
20
30
40
50
60
AMBIENT TEMPERATURE
70
80
(oC)
FIGURE 20. TYPICAL CLOCK FREQUENCY PERCENT
CHANGE vs TEMPERATURE
7-61
90
100
HIP5061
Typical Performance Curves (Continued)
2.5
0.30
VDD = VG = 12V, VFB = 5.1V
DMOS TRANSISTOR DRAIN TO
SOURCE RESISTANCE (Ω)
PERCENT FREQUENCY CHANGE
3.0
2.0
1.5
o
TA = +100 C
1.0
TA = 0oC
0.5
0.0
-0.5
-1.0
-1.5
-2.0
0.25
VDD = VG = 10.8V, IDRAIN = 5A
0.20
0.15
0.10
0.05
-2.5
11.2
11.6
12.0
12.4
VDD (V)
12.8
13.2
13.6
0.00
14.0
FIGURE 21. TYPICAL CLOCK FREQUENCY PERCENT CHANGE
vs SUPPLY VOLTAGE VDD AT 0oC AND +100oC
0.30
DMOS TRANSISTOR DRAIN TO
SOURCE RESISTANCE (Ω)
0.28
VDD = VG = 10.8V, VFB = 5.1V
0.26
0.24
TA =
+100oC
0.22
0.20
0.18
0.16
TA = 0oC
0.14
0.12
0.10
0
1
2
3
4
5
6
DMOS TRANSISTOR DRAIN CURRENT (A)
7
FIGURE 23. TYPICAL DMOS TRANSISTOR DRAIN TO SOURCE
RESISTANCE vs DRAIN CURRENT IDRAIN AT
0oC AND +100oC
10
20
30
40
50
60
70
AMBIENT TEMPERATURE (oC)
80
90 100
0.50
0.45
VDD = 60V
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
0
10
20
30
40
50
60
70
AMBIENT TEMPERATURE (oC)
80
90
100
FIGURE 24. TYPICAL DMOS TRANSISTOR DRAIN TO SOURCE
LEAKAGE CURRENT vs TEMPERATURE
3.0
2.90
2.8
VDD = VG = 12V
VDD = VG = 12V, IDRAIN = 0.25A
2.88
2.6
REFERENCE VOLTAGE (V)
TRANSCONDUCTANCE (A/V)
0
FIGURE 22. TYPICAL DMOS TRANSISTOR DRAIN TO SOURCE
RESISTANCE vs TEMPERATURE
DMOS TRAISISTOR LEAKAGE CURRENT (µA)
-3.0
10.8
2.4
2.2
2.0
1.8
1.6
1.4
2.86
2.84
2.82
2.80
2.78
2.76
1.2
1.0
0
10
20
30
40
50
60
70
AMBIENT TEMPERATURE (oC)
80
90
2.74
100
FIGURE 25. TYPICAL TRANSCONDUCTANCE FROM VC PIN TO
DMOS TRANSISTOR DRAIN (PEAK CURRENT)
vs TEMPERATURE
0
10
20
30
40
50
60
70
AMBIENT TEMPERATURE (oC)
80
90
100
FIGURE 26. TYPICAL VOLTAGE TO CURRENT CONVERTER
REFERENCE VOLTAGE vs TEMPERATURE
7-62
HIP5061
180
VDD = VG = 12V
175
170
165
160
155
150
145
140
0
10
20
30
40
50
60
AMBIENT TEMPERATURE
70
80
90 100
VDD = VG = 12V
145
140
135
130
125
120
115
0
10
20
30
40
50
60
70
AMBIENT TEMPERATURE (oC)
80
90
100
FIGURE 28. TYPICAL MINIMUM DMOS TRANSISTOR “OFF”
TIME vs TEMPERATURE
-0.50
COMPENSATING RAMP RATE (A/µs)
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
VDD = VG = 12V, DUTY CYCLE = 96%
4.5
4.0
0
10
20
30
40
50
60
70
AMBIENT TEMPERATURE (oC)
80
-0.55
VDD = VG = 12V
-0.60
-0.65
-0.70
-0.75
-0.80
-0.85
-0.90
-0.95
-1.00
90 100
0
10
20
30
40
50
60
70
80
90 100
AMBIENT TEMPERATURE (oC)
FIGURE 29. TYPICAL MAXIMUM CONTROLLABLE PEAK
DMOS DRAIN CURRENT vs TEMPERATURE
FIGURE 30. TYPICAL COMPENSATING RAMP RATE
vs TEMPERATURE
1.80
11
1.75
VDD = VG = 12V
VDDMIN AND VDDHYS VOLTAGE (V)
COMPENSATING RAMP DELAY TIME (µs)
150
(oC)
FIGURE 27. TYPICAL MINIMUM DMOS TRANSISTOR “ON”
TIME vs TEMPERATURE
MAX CONTROLLABLE PEAK CURRENT (A)
MINIMUM DMOS TRANSISTOR "OFF" TIME (ns)
MINIMUN DMOS TRANSISTOR "ON" TIME (ns)
Typical Performance Curves (Continued)
1.70
1.65
1.60
1.55
1.50
1.45
1.40
1.35
1.30
1.25
1.20
10
VDDMIN
9
8
7
6
VFB = 4V
5
4
3
2
VDDHYS
1
0
0
10
20
30
40
50
60
70
80
AMBIENT TEMPERATURE (oC)
FIGURE 31. TYPICAL COMPENSATION RAMP DELAY
TIME vs TEMPERATURE
90
100
0
10
20
30
40
50
60
70
AMBIENT TEMPERATURE (oC)
80
90
100
FIGURE 32. TYPICAL RISING VDD COMPARATOR THRESHOLD
VOLTAGE vs TEMPERATURE
7-63
HIP5061
Typical Application Circuit
Figure 33 shows a Simplified Block Diagram of the HIP5061 in a
typical Boost converter. A resistor connected from the VIN supply
to the VDD terminal of the IC powers the internal 14V shunt
regulator. The Gate Driver supply is decoupled from the main
supply by a small external resistor connected between VDD and
the VG terminal. A bypass capacitor is connected between the
VDD terminal and ground to reduce coupling between analog and
digital circuitry. A Schottky diode insures efficient energy transfer
from the DMOS drain circuit inductor to the load. To set the
output voltage, two resistors are used to scale the output supply
voltage down to the 5.1V internal reference.
The heart of the IC is the high current DMOS power
transistor with its associated gate driver and high-speed
peak current control loop. A portion of the converters DC
output is applied to a transconductance error amplifier that
compares the fed back signal with the internal 5.1V
reference. The output of this amplifier is brought out at
the VC terminal to provide for soft start and frequency
compensation of the control loop. This same signal is also
applied internally to program the peak DMOS transistor
drain current. To assure precise current control, the
response time of this peak current control loop is less
than 50ns.
A 2MHz internal clock provides all the timing signals for the
converter operating at 250kHz. A slope compensation circuit
is also incorporated within the converter IC to eliminate subharmonic oscillation that occurs in continuous-current mode
converters operating with duty cycles greater than 50%.
HIP5061 Description of Operation
Figure 2 shows a more detailed Functional Block Diagram of
the HIP5061. An internal 14V shunt regulator in conjunction
with an external series resistor provides internal operating
voltage to the IC in applications where no 12V auxiliary supply is available. Note that In applications where the input
voltage at VDD is 12V, +/-10%, the regulator is not used. This
regulator is shown as a zener diode on the diagrams of Figure 2 and Figure 33.
The 2MHz clock is processed in the Control Logic block to
provide various timing signals. A cycle of operation begins
when a 100ns pulse (which occurs at a 4µs interval) triggers
the latch that initiates the DMOS transistor on-time. This
pulse also provides a blanking interval in the Current Monitoring block to eliminate false turn-offs caused by high transient pulse currents that occur during turn-on. The output of
VIN
VOUT
VDD
VG
DRAIN
HIP5061
VDD CLAMP
2MHz
CLOCK
CONTROL
LOGIC
GATE
DRIVER
TAB
(SOURCE)
VC
OVER
TEMP
AMP
V/I
FB
2.6V
UNDER
VOLTAGE
SLOPE
COMPENSATION
5.1V
REFERENCE
GND
FIGURE 33. SIMPLIFIED BLOCK DIAGRAM OF THE HIP5061 IN A TYPICAL "BOOST" CONFIGURATION
7-64
HIP5061
the Current Ramp block is summed with the sensed DMOS
transistor current (to provide slope compensation) before
being compared with the Error Current signal. The current
ramp, -0.45A/µs, is inhibited for the first 1.5µs (37.5%) of the
duty cycle by the Ramp Enable signal, since ramp is not
needed for slope compensation during this interval. Inhibiting of the compensating ramp has the effect of reducing the
peak short-circuit current.
The output of the power supply is divided down and
monitored at the FB terminal. A transconductance error
amplifier compares the DC level of the fed back voltage with
an internal bandgap reference, while providing voltage loop
compensation by means of external resistors and
capacitors. The Error Amplifier output (the error voltage) is
then converted into a current (the Error Current) that is used
to program the required peak DMOS transistor current that
produces the desired output voltage. When the sum of the
sensed DMOS transistor current and the compensating
ramp exceed the Error Current signal, the latch is reset and
the DMOS transistor is turned off. Current comparison
around this loop takes place in less than 50ns, allowing for
excellent 250kHz converter operation. The latch can also be
reset by an under-voltage (VDD < 10.3V typical), over
temperature (TJ > +125oC typical) or a shutdown signal
externally applied at the VC terminal. See Figure 36.
Note that if the error voltage (at the VC pin) is less that
2.55V, then the output of the Voltage-to-Current Converter
will be held at zero. This condition will produce the minimum
possible pulse width, typically 150ns (100ns blanking pulse
plus 50ns delay). Error voltages lower than this 2.55V level
will not produce shorter pulse widths. Under very light loads
(when VC goes below 1.5V), the Enable Comparator will
temporarily hold-off the PWM latch (and the DMOS transistor) until the VC voltages rises above 1.5V. This low VC
inhibit circuit results in a burst-mode of operation that maintains regulation under light or no loads.
During an over-current condition, the output of the Error
Amplifier will attempt to exceed the 7.0V threshold. At this
point, the Short-Circuit Comparator will pull down on this signal and induce a low-level oscillation about the threshold,
serving to clamp the peak error voltage. This clamping
action, in turn, will limit the peak current in the DMOS transistor, reducing the duty ratio of the switch as the demand for
current continues to increase. This action, in conjunction
with the Thermal Monitor, serves to protect the IC from overcurrent (short-circuit) conditions.
impedance, ideally infinity. The amplifier gain is typically
50dB and is not significantly altered when operating into the
stages that follow within the IC. To minimize the output stage
idling current, while providing high peak currents to insure
rapid response to load and input transients, a class B type of
output stage was used in the amplifier. Placing a 100k
resistor from the amplifier output terminal, VC , to ground will
bias the output stage to an active state and still minimize
power consumption. In all cases, the resistor shunting the
transconductance amplifier output must be greater than
10kΩ to insure that the output will rise sufficiently high to
obtain the maximum DMOS transistor drain current.
Start-Up Sequence
Upon initial power up of the HIP5061 in a typical application
circuit, the voltage at VC will be zero, and the DMOS transistor will be off. When the voltage at VDD rises above the
10.3V typical threshold, the error amplifier output is enabled
and the VC voltage begins to rise in response to the low voltage at the FB terminal. When the VC voltage rises above
1.5V the DMOS transistor begins to switch at the minimum
duty cycle, and when it rises above 2.55V the duty cycle
begins to increase. The VC voltage (and peak DMOS transistor current) will then continue to rise until the voltage loop
gains control and establishes regulation. Note that the rate
of rise in the VC voltage can be controlled by an external soft
start circuit (See Soft Start Implementation).
If the VC voltage is unrestricted in its rate of rise, then it will
typically rise quickly to its maximum (peak current) value,
causing the DMOS transistor to turn-on and stay on until it
reaches the peak current value. At this point, the DMOS
transistor begins switching, and the VC voltage (and peak
DMOS transistor current) will drop down to the level commanded by the voltage loop.
Using the Shunt Regulator
The internal 14V shunt regulator in conjunction with an
external series resistor allows the IC to operate from quite
high input voltages, limited only by power dissipation in the
external resistor. When only higher voltages are available, a
bootstrap or other 12V auxiliary supply can be used to eliminate this dissipation. The series resistor should be chosen to
be as large as possible to reduce power dissipation at high
line, while ensuring adequate VDD voltage at low line. The
maximum value for this resistor, R, is given by:
R
Using the Transconductance Error Amplifier
A transconductance amplifier with a typical gm of 30mS is
used as the input gain stage where the power supply output
voltage is compared with the internally generated 5.1V
reference voltage. A PNP transistor input structure allows
this amplifier to accommodate large negative going transient
voltages without causing amplifier phase reversal, often
associated with PNP input structures. Negative transients up
to 5V applied to the input though at least 5.1k will not result
in phase reversal. The amplifier output stage has the
customary drain to drain output to help improve the output
MAX
V
– 10.5
I, MIN
( Ω ) = ----------------------------------------0.033
Where VI is the input voltage to the power supply. The value
chosen for this resistor must also result in a current, I, into
the VDD clamp that is less than 105mA when the input voltage is at its maximum:
7-65
I
MAX
V
– 13.3 
 I, MAX

( A ) = --------------------------------------------------
R
MAX
HIP5061
Inductor Selection
TABLE 2. MINIMUM INDUCTANCE FOR STABLE CCM
OPERATION ABOVE 50% DUTY CYCLE
The selection of the energy storage inductor(s) LSTOR for a DC to
DC converter has tremendous influence on the behavior of the
converter. It is particularly important in light of the high level of
integration (and necessarily few degrees of freedom) achieved in
the HIP5061. There are several factors influencing the selection
of this inductor. First, the inductance of LSTOR will determine the
basic mode of operation for the converter: continuous or
discontinuous current. In order to maximize the output power
for the given maximum controllable DMOS transistor current, a
converter may be designed to operate in continuous current
mode (CCM). However, this tends to require a larger inductor,
and for many converter topologies results in a feedback loop
tha is difficult to stabilize. For these and other reasons, the
inductor LSTOR may be chosen so as to operate the converter in
discontinuous current mode (DCM). The relative merits of
CCM and DCM operation for various topologies and the
corresponding selection of LSTOR is well documented and will not
be covered here.
A second factor influencing the selection of LSTOR is the
stability requirement for current-mode control. This constraint is
only applicable for converters operating in CCM, since openloop instabilities of this type are not observed in converters
operating in DCM. For marginal stability, the compensating
ramp (internal to the HIP5061) must have a slope that is
greater than one-half the difference between the inductor
current’s down slope and up slope. (To ensure stability for duty
ratios D > 0.8, the slope of the compensating ramp should be
equal to the inductor current downslope.) A generally accepted
goal is to set the slope of the compensating ramp to be at least
one-half of the inductor current down slope. Since there is no
external control over the internal compensating ramp, one must
be sure that the inductor is large enough so that the down slope
of the inductor current is not too large. Table 2 summarizes this
requirement for minimum inductance for several common
topologies.
A third constraint on the size of the inductor is one that is
common among current-mode controlled PWM converters,
and applies to both DCM and CCM operation. The stable
generation of the desired DMOS transistor pulse width
depends on the accurate comparison of the error signal and
the peak LSTOR (DMOS) transistor drain current. Thus, as
the peak LSTOR ripple current becomes smaller, immunity
from noise on the error signal is eventually reduced until the
pulse width can no longer be adequately controlled. For the
HIP5061, the inductor current ripple must be at least 200mA
peak to peak to ensure proper control of the DMOS
transistor current. This effectively establishes a maximum
value for the inductor LSTOR, so as to maintain at least
200mA of ripple. Note that under extremely light or no load
conditions, all converters will eventually operate in DCM,
and the 200mA requirement will eventually be violated.
Under these conditions, the HIP5061 will continue to
regulate, although the switching of the DMOS transistor will
be in a burst-mode, controlled by the Light Load
Comparator. (See Figure 2.)
CONVERTER TYPE
MINIMUM INDUCTANCE
Boost
V O + V D – V I, MIN
L = ------------------------------------------2M R, MIN
SEPIC (Note 1)
VO + VD
L1 L2
------------------ > ----------------------L 1 + L 2 2M R, MIN
Cuk (Note 2)
L1 L2
VO – VD
------------------ > ----------------------L 1 + L 2 2M R, MIN
Flyback
 NP  ( VO + VD)
L P >  -------  --------------------------- N S  2M R, MIN
Forward
 NS  ( VO + VD)
L >  -------  --------------------------- N P  2M R, MIN
NOTES:
1. Assumes that L1 and L2 are both CCM.
2. L = Inductance in Henrys, VO = Output Voltage,
VD = Diode Voltage Drop, VI = Input Voltage,
MR,MIN = (∆I/∆t)MIN = 0.45A/µs, L1 = Drain Inductor,
L2 = Secondary Inductor, NP = Primary Turns,
NS = Secondary Turns
DMOS Transistor Turn-Off Snubber
In order to reduce dissipation in the DMOS transistor due to
turn-off losses, the turn-off time has been minimized.
However, the rapid reduction of current that occurs in the
drain of the DMOS transistor can result in large transient
voltages being induced across any parasitic inductance in
the drain path. For this reason, it is important that such
parasitic inductance be reduced by good, high frequency
layout practices. Nevertheless, there are many instances
(e.g., transformer isolated topologies) in which voltages in
excess of 60V may be developed at the DMOS transistor
drain. In some cases, a simple R-C snubber may be added
to reduce the overshoot of the drain voltage to a safe level.
It is also possible that the large amount of ringing that can
occur at the DMOS transistor drain at turn-off will induce
noise in the IC. This noise may result in false triggering of
the PWM latch, particularly at high peak DMOS transistor
drain currents. Noise related instability can also be eliminated by the addition of a snubber, which will rapidly damp
out such turn-off ringing. Good layout practices will reduce
the need for such protective measures, and ensure that the
DMOS transistor is not overstressed.
Under-Voltage Lockout
The VDD input voltage is monitored by a comparator that
holds off the DMOS transistor gate drive signal when the
VDD voltage is less that about 10.3V. The typical 0.5V hyster-
7-66
HIP5061
esis of this comparator is intended to reduce oscillation
when the voltage at VDD is in the vicinity of 10V. Note, however, that when an external series resistor is used to feed the
shunt regulator, the voltage drop across this resistor (which
sharply decreases when the IC shuts down), effectively
reduces the hysteresis. To reduce the tendency for oscillation in the vicinity of the 10V threshold, the impedance of the
source that feeds the DC to DC converter input should be
minimized. The addition of a capacitor (1µF-47µF) at the
VDD terminal can also help to provide smooth turn-on or turnoff of the converter if the input supply rises or falls gradually
through the VDD Comparator threshold.
Peak Controllable DMOS Transistor Current
Figure 34 shows the guaranteed minimum, peak controllable
DMOS transistor current versus duty cycle. This peak current value is established by the current limit circuitry, which
effectively clamps the voltage at VC (the error voltage) to
perform current limiting. Since the sensed DMOS transistor
current is summed with a compensating current ramp that
begins its rise 1.5µs after the initiation of a cycle, current limiting will begin to occur at a peak DMOS transistor current
that varies with the operating duty cycle. The highest current
limit threshold occurs for D<0.375, where no ramp is added
to the sensed DMOS transistor current. At higher operating
duty ratios, the onset of current limit will occur at increasingly
lower currents, due to the effect of adding the compensating
ramp to the sensed current. Note that this curve represents
guaranteed minimum values. The guaranteed maximum values are considerable higher, although they are still limited to
levels that protect the IC.
DMOS Transistor Turn-On Noise
Although the large DMOS transistor turn-on current spikes are
“blanked over” by the control circuit, it is important to minimize
these current spikes, since they often result in voltage spikes
considerably below the device substrate that can activate parasitic devices within the IC. Such activation of parasitic
devices will often result in improper operation of the IC. An
external terminal labeled VG brings out the power supply to
the gate drive circuitry. This allows for the control of the peak
current delivered to the gate of the DMOS transistor, which in
turn establishes the turn-on speed. The VG pin may be externally bypassed for the fastest possible turn-on, or series resistance may be added with no bypassing capacitor to slow
down the turn-on of the DMOS transistor. Depending upon the
actual layout of the supply, it is generally recommended that a
series resistor be added (10Ω-150Ω) so that the DMOS transistor turn-on speed is reduced. By properly adjusting the
turn-on speed, undershoot can be avoided while turn-on
switching losses are kept to a minimum.
Soft Start Implementation
It is often desirable to allow the regulator to start up slowly,
Figure 35 shows one means of implementing this action. The
normally high output current from the HIP5061 transconductance amplifier (when VFB = 0 and VREF = 5.1V) is directed to
an external capacitor through a diode. This slows down the
rate of rise of the voltage at the VC terminal. After the regulator starts, the external capacitor is charged to VDD and is
effectively removed from the frequency compensation network by a reverse biased diode. To ensure rapid recycling of
the capacitor voltage with removal of power, a diode is placed
across the 100kΩ resistor. Logic Shutdown Input (VC Pin).
PEAK DMOS CURRENT (A)
7
100kΩ
5
VDD
2mA, TYP
VG
DRAIN
VC
GATE DRIVER
AND CONTROL
CIRCUITRY
20µF
3
1
SOFT START
NETWORK
0.06
0.375
DUTY CYCLE
GND
100kΩ
1.0
HIP5061
FB
SOURCE
0.1µF
TYPICAL FREQUENCY
COMPENSATION NETWORK
FIGURE 34. PEAK DMOS TRANSISTOR DRAIN CURRENT vs
DUTY CYCLE
FIGURE 35. SOFT START CIRCUIT FOR THE HIP5061
When the DMOS transistor first turns ON there may be substantial current spikes exceeding the normal maximum peak
current established by the current control stages within the
IC. To prevent these spurious spikes from conveying erroneous information to the Current Comparator, a 100ns blanking
signal is applied to the current monitoring circuitry. Thus,
there is no peak current protection during the first 6% of the
duty cycle (see Figure 36).
The DC to DC converter may be shut down by returning the
VC output terminal to ground. A sinking current greater than
4mA will insure that this output is pulled to ground. It must be
remembered that once switching operation ceases, the drain
of the DMOS transistor is open. When the supply is in the
Boost configuration, the output voltage is not zero but the input
voltage less diode and inductor voltage drops. If the SEPIC
7-67
HIP5061
topology is used, this is not the case. Shutting down the regulator via the VC terminal will cut off the output. Figure 36 shows
two methods of shutting down the IC. In each case the current
sinking circuit must be able to sink at least 4mA, the maximum
current from the HIP5061 VC terminal.
FROM CD4049UB
VDD
4mA
VG
DRAIN
VC
GATE DRIVER
AND CONTROL
CIRCUITRY
OFF
FB
OFF
All the capacitors shown with values of 1µF or less are of the
multilayer ceramic type with the X7R dielectric material. This
material has a fairly flat voltage and temperature coefficient
that assures that the capacitance remains comparatively constant at extreme operating temperatures and voltages. The
multilayer construction allows for comparatively large values
with good volumetric efficiency and low inductance. Capacitors around the power input and output circuits should be
returned to the device TAB via a low inductance ground plane.
This TAB is internally connected to the DMOS transistor
source. The schematic diagram of Figure 38 was drawn with
the diagonal leads to show the critical paths for the various
high frequency elements. These short interconnects assure
the lowest inductance around the output power circuit.
Design of a 28V, 1.8A Boost Converter
GND
ALTERNATE METHOD
HIP5061
SOURCE
Figure 38 shows the schematic diagram and a parts list of a
50W supply designed with the HIP5061. Table 3 tabulates
the performance of the power supply.
NOTE: FREQUENCY
COMPENSATION NETWORK
NOT SHOWN
TABLE 3. TYPICAL LABORATORY PERFORMANCE OF
50W, 28V/1.8A REGULATOR
FIGURE 36. TWO METHODS OF SHUTTING DOWN THE HIP5061
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11V to 16V
Mounting, Layout and Component
Selection
Line Regulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12mV/V
Output Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.0V
Load Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 64mV/A
The TO-220 package with its gullwing leads was designed to
be surface mounted. To aid in the external reduction of lead
length and hence inductance and resistance, the IC leads
were staggered. To keep the inductance and resistance of
the critical drain terminal as low as possible, it is suggested
that the PC trace to the DMOS transistor drain terminal be
made as wide as possible. The adjacent source terminal is
not recommended to be used and therefore allows the metal
to the drain terminal to be widened beyond the normal
widths for these terminals. Figure 37 illustrates these points.
One of the most important aspects to the proper application
of this device is high frequency bypassing. In a Boost converter, for example, there should be a low-inductance interconnect from the DMOS transistor drain, through the output
diode and capacitors, and returning to the TAB (source) of
the HIP5061. Inductance in this line results in large transient
voltages on the DMOS transistor drain terminal which can
result in voltages above the maximum DMOS transistor
drain voltage rating.
IC SOLDERED TO PC BOARD
VG PC METAL
Output Ripple, FL . . . . . . . . . . . . . . . . . . . . . . . . . . 600mV P-P
(20MHz BW)
Output Ripple, after Filter, FL . . . . . . . . . . . . . . . . . 80mV P-P
(20MHz BW)
Efficiency: VI = 11V, IL = 0.18A. . . . . . . . . . . . . . . 90%
VI = 11V, IL = 1.8A. . . . . . . . . . . . . . . . 89%
VI = 16V, IL = 0.18A. . . . . . . . . . . . . . . 73%
VI = 16V, IL = 1.8A. . . . . . . . . . . . . . . . 93%
Inductor Selection
In order to maximize the output power for the given maximum controllable DMOS transistor current, this converter
has been designed to operate in continuous current mode
(CCM). In this mode, the inductor value will generally be
large, resulting in a lower inductor ripple current and a lower
peak DMOS current. To ensure that the converter operates
in CCM over the usable range of input voltage and output
current, the value of L2 must be greater than the “critical
inductance,” given by
VDD PC METAL
WIDER
DRAIN
PC METAL
FOR LOWER
INDUCTANCE
2
L
HIP5061
NORMAL
PC METAL
FOR FB
AND VC
V +V –V
T
V V
O I, MAX  O
D
I, MAX  S
= ----------------------------------------------------------------------------------------------------------CRIT
2
V +V 
2P
O, MIN  O
D
2
–6
( 28 ) ( 16 ) ( 28 + 0.5 – 16 ) 4 ×10
= -------------------------------------------------------------------------------------------------2
2 ( 5.6 ) ( 28 + 0.5 )
GROUND PC METAL
= 39µH
FIGURE 37. SHOWING WIDER PC BOARD METAL FOR
CRITICAL
7-68
HIP5061
where PO,MIN has been arbitrarily chosen as 5.6W, corresponding to an output current of 0.2A, and VD is the forward
voltage of CR1. Thus, for L2 > 39µH, the converter will be in
CCM for VI = 11V to 16V and IL = 0.2A to 1.8A.
A second factor influencing the selection of L2 is the stability
requirement for current-mode control. Using the above
equation for LMIN for the Boost converter:
V +V –V
O
D
I, MIN
28 + 0.5 – 11
L > ----------------------------------------------------- = --------------------------------------------------------- = 19 µH
2×M
6


RAMP, MIN
2 ×  0.45 ×10 A ⁄ S 
Thus, L2 must be at least 19µH to ensure good stability of
the current loop, and a choice of L2 = 40µH satisfies this
requirement, while maintaining CCM operation over an
extremely wide load range.
The chosen core material for L2 is Kool Mu ferrous alloy powder from Magnetics, Inc. This material was chosen because of
its relatively low cost, while its losses due to AC flux are five to
ten times less than conventional powdered iron.
Loop Compensation
The control to output transfer function for this current-mode
boost converter has the following characteristics over the
specified load and line conditions:
INPUT
11VDC - 16VDC
C4
RA
20Ω, 1W
C5
7
47µF,
50V VDD
1µF,
50V
D.C. Gain: 20dB-40dB
Pole at 88Hz-880Hz
LHP Zero at 1MHz
RHP Zero at 11.0kHz-110kHz
Double Pole at 80kHz (from filter)
To stabilize the voltage loop, it is necessary to establish the
unity gain crossover frequency well below the RHP zero, since
this zero introduces positive gain and negative phase. A crossover of 4kHz is fairly conservative, and is achieved by adding a
1µF capacitor at the VC pin, which provides near infinite DC
gain, and about -5dB of gain at 4kHz. This results in a phase
margin of about 15o at full load. Note that R4 is required for
proper operation of the transconductance amplifier, since it is
providing bias current for the output stage as discussed under
Using the Transconductance Error Amplifier section.
Output Filter Design
Inductor L3 was chosen with C11 to provide at least 15dB of
ripple attenuation at the switching frequency. The corner frequency (80kHz) of this filter is well above the crossover frequency of the voltage loop (4kHz), and has no effect on
stability. This secondary LC filter was used to reduce output
ripple instead of a lower-cost, high-value, low ESR aluminum electrolytic capacitor to demonstrate the reduction in
volume possible at this switching frequency. A lower cost
solution could achieve the same output ripple by replacing
C9,10,12 and L3 with one or two large capacitors (e.g.,
L2, 40µH
6
5
VG
C13
1nF,
100V
DRAIN
GATE DRIVERS,
CONTROL CIRCUITRY
AND LOGIC
FB
GND
HIP5061
RA
R1
R2
R4
R5
R11
PARTS LIST
20Ω, 1W, Wirebound - Dale RWR81S20R0FR or Equivalent
10K, 1%
2.2K, 1%
100K, 1/4W
10Ω, 1/4W
7.5Ω, 1/2W, Carbon - Allen Bradley EB75G5
VC
C9
6.8µF,
50V
R1
10K,
1%
OUTPUT
28VDC
0A - 1.8A
OPTIONAL
FILTER
3
1
C1
2
1µF,
50V
C1, C3, C4 and C11
C5 and C12
C9 and C10
C13
CR1
L2
L3
R4
100K
R2
2.21K, 1%
1µF, 50V, Ceramic - Murata Erie RPE113X7R105050V
47µF, 50V, Alum - United Chemicon 515D476M050
6.8µF, 50V, Ceramin - Mallory M60u6r8M50
1nF, 100V, Ceramin - Kemet C322C102K1G5CA
Schottky Diode - Motorola MBRD360
40µH at 5A, Pulse Engineering PE - 53571
4µH at 5.5A, Pulse Engineering PE - 53570
FIGURE 38. HIP5061 50W, 28V BOOST REGULATOR SCHEMATIC AND PARTS LIST
7-69
C11
1µF,
50V
C10
6.8µF,
50V
TAB
(SOURCE)
C12
47µF,
50V
C3
1µF,
50V
R11
7.5Ω, 1/2W
R5
10Ω, 1/4W
L3, 4µH
CR1
HIP5061
390µF, 50V, type 673D from United Chemicon). This change
would also greatly improve load transient response, provided that the loop compensation is appropriately adjusted.
Note that in the circuit of Figure 38, capacitor C12 does not
significantly affect output ripple, but is necessary to absorb
the energy stored in L2 during severe load transients. In the
event of a step change in load from 1.8A to 0A, C12 will limit
the output voltage overshoot to about 10V and protect the
drain of the DMOS transistor from overvoltage breakdown.
Input and VDD Filters
Since the boost converter is current fed, input filtering is easily achieved by the addition of a small capacitor C4. This
capacitor provides nearly 40dB of ripple current attenuation
for the input, reducing the AC ripple current flowing into the
converter to less than 200mA.
R5 and C3 have been chosen to provide good filtering of
high frequency pulse currents. R5 provides isolation
between the analog VDD pin and the high pulse current VG
pin, and also provides a means to control the turn-on speed
of the DMOS transistor by limiting the peak current available
to the internal gate drive circuitry. Thus the output transition
time may be increased to prevent drain voltage undershoot.
Undershoot may result in activation of device parasitics and
improper circuit operation. For the two-layer board used for
this design, C3 could be reduced to 0.22µF without affecting
circuit operation. C5 was added to provide low-frequency filtering at the VDD pin. This reduces the tendency of the circuit
to oscillate off and on when the voltage at the VDD pin s in
the vicinity of the under voltage lockout threshold, typically
10V, and the output power is high (30W - 50W).
Shunt Regulator Resistor
Resistor RA has been chosen to be as large as possible to
reduce power dissipation at high line, while ensuring adequate VDD voltage at low line. Note that the guaranteed
range of input voltage for proper operation of this circuit is
11.2V to 15.3VDC, based upon data sheet limits. However,
the circuit was found to perform well at room temperature for
VI = 10.7VDC to 17VDC. The maximum value for RA is
R
MAX
V
– 10.5
I, MIN
= ----------------------------------------- = 21Ω
0.033
RA has been chosen as 20Ω, which results in a current into
the VDD clamp that is less than 105mA when the input voltage is at its maximum:
I
MAX
Snubber Network
A snubber network has been added to reduce the ringing at
the drain due to parasitic layout inductances. In particular,
under severe load transient conditions, this snubber is necessary to protect the drain from voltage breakdown. A second benefit of reducing the noise and ringing at the drain is
that it reduces the tendency of the HIP5061 to exhibit noiserelated instabilities at high peak DMOS transistor currents
(4A-6A). A value of 1000pF was chosen for C13, since this
is adequate to dampen the ringing associated with the
200pF drain capacitance of the DMOS transistor. R11 was
chosen as 7.5Ω to provide the best possible dampening
given the parasitic inductances that exist in the layout. Note
that this snubber may not be necessary if the layout of the
circuit were improved, or if the application did not push the
envelope of DMOS transistor current.
Other Power Supply Topologies
Figure 39 shows three other topologies besides the Boost that
may be implemented with the grounded source DMOS power
transistor used in the HIP5061. Other, more complex power
supply topologies such as the Quadratic are also possible to
implement with the HIP5061. One noteworthy feature of the
Quadratic topology as shown in Figure 41 is the wide input to
output voltage transfer ratio possible with reasonable duty
cycles. Duty cycles that are not near the Minimum DMOS transistor “ON” Time specification shown in the Data Sheet. This
permits easier control at the extremes of the transfer ratios.
Compensating the control loop can pose challenges because
of the wider changes in the transfer ratio and hence loop gain.
The SEPIC topology[11,13] does not have quite as wide inputoutput voltage range with reasonably controlled duty cycles
as the Quadratic converter mentioned above, but it does
allow both voltage increase and decrease with the same circuit. This is particularly advantageous when a power supply
is being used in the stabilizing mode and isolation is not
required. For example, in an application where a regulated
24V output is required and the input voltage varies ±20%
from a nominal 24V. The SEPIC supply can provide both the
Boost and Buck functions.
Another outstanding advantage of the SEPIC topology is its
fault isolation of the input and output voltage. All energy is
transferred via the coupling capacitor. Moreover if the clock
stops, voltage transfer stops. If the switching transistor shorts
there is no output. The Buck circuit will apply full input voltage
to the load with a shorted transistor. This is reason that the
SEPIC topology is referred to as the fail-safe Buck.
V
– 13.3 
 I, MAX

= -------------------------------------------------- = 100mA < 105mA
20.0
7-70
HIP5061
+
+
+
VDD
VG
+
DRAIN
VOUT
VIN
GATE DRIVER
AND CONTROL
CIRCUITRY
VC
FB
VOUT
VDD
HIP5061
VIN
GND
-
SOURCE
-
VC
VG
DRAIN
GATE DRIVER
AND CONTROL
CIRCUITRY
FB
HIP5061
-
FIGURE 39A. SEPIC (FAIL-SAFE BUCK) CONVERTER
GND
-
+
VDD
VG
VC
AND CONTROL
CIRCUITRY
HIP5061
GND
SOURCE
FIGURE 40. FLYBACK CONVERTER
DRAIN
GATE DRIVER
VIN
COUPLING
MEANS
ISOLATED
OR DIRECT
FB
VOUT
It should be noted that when the Cuk topology is implemented, a transistor current source is used to convert the
negative output voltage of the Cuk converter to a current that
is level shifted to the FB terminal on the HIP5061.
Two other useful topologies that may be used are the Forward and the Flyback as shown in Figure 40 and Figure 41.
As shown, they may either be operated as an isolated or
non-isolated converter.
SOURCE
FIGURE 39B. CUK CONVERTER
+
+
+
VOUT
-
+
VDD
VG
DRAIN
VDD
VIN
VC
GATE DRIVER
AND CONTROL
CIRCUITRY
VOUT
VIN
FB
VC
VG
DRAIN
GATE DRIVER
AND CONTROL
CIRCUITRY
HIP5061
-
GND
SOURCE
HIP5061
-
-
GND
FB
COUPLING
MEANS
ISOLATED
OR DIRECT
SOURCE
FIGURE 39C. QUADRATIC CONVERTER
FIGURE 41. FORWARD CONVERTER
FIGURE 39. THREE OTHER TOPOLOGIES
7-71
HIP5061
Both the SEPIC and the Boost topologies may be operated
at high voltages with the addition of a high voltage cascode .
Figure 42 shows the Cascode SEPIC converter that is
essentially limited by the selection of the external power
transistor. The burden of voltage, and power is placed upon
the external transistor. The HIP5061 still performs the drain
current sampling and the control function is the same as the
non cascode configuration.
VOUT
160V
VIN
VDD
VC
VG
DRAIN
GATE DRIVER
AND CONTROL
CIRCUITRY
GND
FB
SOURCE
-
[8] Severns and Bloom, Modern DC-to-DC Switchmode
Power Converter Circuits, Van Nostrand Reinhold, 1985
Figure 43 shows the voltage transfer as a function of duty
cycle for the power supply topologies discussed.
[9] Sum, K., Switch Mode Power Conversion - Basic Theory
and Design, Marcel Dekker, In., 1984
[10] Pressman, A., Switching and Linear Power Supply,
Power Converter Design, Hayden Book Co., 1977
[11] Massey, R.P. and Snyder, E.C., High Voltage SingleEnded DC-DC Converter, IEEE Power Electronics Specialists Conference (PESC) record, 1977, pp. 156-159
100
BUCK-BOOST, CUK AND SEPIC
M = D/(1-D)
10
[12] Clarke, P., A New Switched-Mode Power Conversion
Topology Provides Inherently Stable Response, POWERCON 10 proceedings, March 1983, pp. E2-1 through E2-7
M = 1/(1 - D) BOOST
M = VOUT /VIN
[5] Maksimovic and Cuk, General Properties and Synthesis of
PWM DC-to-DC Converters, IEEE Power Electronics
Specialists Conference (PESC) record, June 1989
[7] Mansmann, Jeff; Shafer, Peter and Wildi, Eric, Maximizing
the Impact of Power ICs Via a Time-to-Market CAD Driven
Power ASIC Strategy, Applied Power and Electronics
Conference and Exposition (APEC) proceedings, February 1992, pp. 23-27
FIGURE 42. OFF LINE CASCODE SEPIC
1
[13] Intersil Application Notes AN9208 and AN9212.1
0.1
0.01
0
[2] Smith, Craig D. and Cassani, Distributed Power Systems Via
ASICs Using SMT, Surface Mount Technology, October 1990
[6] Sokal and Sokal, Class E - A New Class of High Efficiency
Tuned Single-Ended Switching Power Amplifiers, IEEE
Journal of Solid-State Circuits, June 1975, pp. 168-176
HIP5061
-
[1] Cassani, John C.; Hurd, Jonathan J. and Thomas, David
R., Wittlinger, H.A.; Hodgins, Robert G.; Sophisticated
Control IC Enhances 1MHz Current Controlled Regulator
Performance, High Frequency Power Conversion (HFPC)
conference proceedings, May 1992, pp. 167-173
[3] Maksimovic and Cuk, Switching Converters With Wide DC
Conversion Range, High Frequency Power Conversion
(HFPC) conference record, May 1989
+
+
References
BUCK
M=D
QUADRATIC
M = D2/(1 - D)2
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
DUTY CYCLE (D)
FIGURE 43. VOLTAGE TRANSFER AS A FUNCTION OF DUTY
CYCLE FOR VARIOUS TOPOLOGIES
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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7-72