IRF IRF6723M2DTRPBF

PD - 97441
IRF6723M2DTRPbF
IRF6723M2DTR1PbF
Applications
l
DirectFET™ Power MOSFET ‚
Dual Common Drain Control MOSFETs for
Multiphase DC-DC Converters
Typical values (unless otherwise specified)
Features
VDSS
Replaces Two Discrete MOSFETs
Optimized for High Frequency Switching
Low Profile (<0.7 mm)
Dual Sided Cooling Compatible
Ultra Low Package Inductance
Compatible with existing Surface Mount
Techniques
l RoHS Compliant and Halogen Free
l 100% Rg tested
l
l
l
l
l
l
VGS
RDS(on)
30V max ±20V max 5.2mΩ@ 10V 8.6mΩ@ 4.5V
Qg
tot
9.4nC
Qgd
Qgs2
Qrr
Qoss
Vgs(th)
3.3nC
1.2nC
17nC
6.3nC
1.8V
G1
G2
D
D
S1
S2
DirectFET™ ISOMETRIC
Applicable DirectFET Outline and Substrate Outline 
S1
S2
SB
RDS(on)
M2
M4
MA
L4
L6
L8
Description
The IRF6723M2DPbF combines two MOSFET switches optimized for high side applications into a single medium can DirectFET package.
The switches have low gate resistance and low charge along with ultra low package inductance providing significant reduction in switching
losses. The reduced losses make this product ideal for high efficiency multiphase DC-DC converters that power the latest generation of
processors operating at higher frequencies.
The IRF6723M2DPbF combines the latest HEXFET® Power MOSFET Silicon technology with the advanced DirectFETTM packaging to
achieve the highest power density for two MOSFETs in a package that has the footprint of a SO-8 and only 0.7 mm profile. The DirectFET
package is compatible with existing layout geometries used in power applications, PCB assembly equipment and vapor phase, infra-red or
convection soldering techniques, when application note AN-1035 is followed regarding the manufacturing methods and processes. The
DirectFET package allows dual sided cooling to maximize thermal transfer in power systems, improving previous best thermal resistance by
80%.
Absolute Maximum Ratings (each die operating consecutively)
Parameter
Drain-to-Source Voltage
Gate-to-Source Voltage
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
VGS
ID @ TA = 25°C
ID @ TA = 70°C
ID @ TC = 25°C
IDM
EAS
IAR
g
Pulsed Drain Current
Single Pulse Avalanche Energy
Avalanche Current
g
h
Typical RDS(on) (mΩ)
25
ID = 15A
20
15
T J = 125°C
10
5
T J = 25°C
0
2
4
6
8
10
12
14
16
18
e
e
f
20
VGS, Gate -to -Source Voltage (V)
Fig 1. Typical On-Resistance vs. Gate Voltage
VGS, Gate-to-Source Voltage (V)
VDS
14.0
ID= 12A
12.0
10.0
Max.
Units
30
±20
15
13
47
130
71
12
V
A
mJ
A
VDS= 24V
VDS= 15V
8.0
6.0
4.0
2.0
0.0
0
5
10
15
20
25
QG Total Gate Charge (nC)
Fig 2. Typical Total Gate Charge vs Gate-to-Source Voltage
Notes:
 Click on this section to link to the appropriate technical paper.
‚ Click on this section to link to the DirectFET Website.
ƒ Surface mounted on 1 in. square Cu board, steady state.
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„ TC measured with thermocouple mounted to top (Drain) of part.
… Repetitive rating; pulse width limited by max. junction temperature.
† Starting TJ = 25°C, L = 0.99mH, RG = 25Ω, IAS = 12A.
1
12/16/09
IRF6723M2DTR/TR1PbF
Static @ TJ = 25°C (each die unless otherwise specified)
Parameter
BVDSS
∆ΒVDSS/∆TJ
RDS(on)
VGS(th)
∆VGS(th)/∆TJ
IDSS
IGSS
gfs
Qg
Qgs1
Qgs2
Qgd
Qgodr
Qsw
Qoss
RG
td(on)
tr
td(off)
tf
Ciss
Coss
Crss
Conditions
Min.
Typ. Max. Units
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
30
–––
–––
20
–––
–––
Static Drain-to-Source On-Resistance
–––
–––
5.2
8.6
6.6
11.3
Gate Threshold Voltage
Gate Threshold Voltage Coefficient
1.35
–––
1.8
-7.2
Drain-to-Source Leakage Current
–––
–––
–––
–––
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
–––
–––
–––
–––
100
-100
nA
VDS = 24V, VGS = 0V, TJ = 125°C
VGS = 20V
Forward Transconductance
Total Gate Charge
34
–––
–––
9.4
–––
14
S
VGS = -20V
VDS = 15V, ID =12A
Pre-Vth Gate-to-Source Charge
Post-Vth Gate-to-Source Charge
–––
–––
2.2
1.2
–––
–––
Gate-to-Drain Charge
Gate Charge Overdrive
Switch Charge (Qgs2 + Qgd)
–––
–––
3.3
2.7
–––
–––
Output Charge
–––
–––
4.5
6.3
–––
–––
Gate Resistance
Turn-On Delay Time
–––
–––
0.4
14
–––
–––
Rise Time
Turn-Off Delay Time
–––
–––
41
15
–––
–––
Fall Time
Input Capacitance
–––
–––
20
1380
–––
–––
Output Capacitance
Reverse Transfer Capacitance
–––
–––
290
120
–––
–––
V VGS = 0V, ID = 250µA
mV/°C Reference to 25°C, ID = 1mA
mΩ VGS = 10V, ID = 15A
i
= 12A i
VGS = 4.5V, ID
2.35
V VDS = VGS, ID = 25µA
––– mV/°C
1.0
µA VDS = 24V, VGS = 0V
150
VDS = 15V
nC
VGS = 4.5V
ID = 12A
See Fig. 2
nC
VDS = 16V, VGS = 0V
Ω
i
VDD = 15V, VGS = 4.5V
ID = 12A
ns
RG= 6.8Ω
pF
VGS = 0V
VDS = 15V
ƒ = 1.0MHz
Diode Characteristics
Min.
Typ. Max. Units
IS
Continuous Source Current
(Body Diode)
Parameter
–––
–––
32
ISM
Pulsed Source Current
(Body Diode)
–––
–––
130
VSD
Diode Forward Voltage
–––
–––
trr
Reverse Recovery Time
Reverse Recovery Charge
–––
–––
16
17
Qrr
g
Conditions
A
MOSFET symbol
showing the
1.0
V
integral reverse
p-n junction diode.
TJ = 25°C, IS = 12A, VGS = 0V
24
26
ns
nC
TJ = 25°C, IF =12A
di/dt = 370A/µs
i
i
Notes:
… Repetitive rating; pulse width limited by max. junction temperature.
‡ Pulse width ≤ 400µs; duty cycle ≤ 2%.
2
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IRF6723M2DTR/TR1PbF
Absolute Maximum Ratings (each die operating consecutively)
Max.
Units
2.7
1.9
25
270
-55 to + 175
W
Parameter
e
e
f
Power Dissipation
Power Dissipation
Power Dissipation
Peak Soldering Temperature
Operating Junction and
Storage Temperature Range
PD @TA = 25°C
PD @TA = 70°C
PD @TC = 25°C
TP
TJ
TSTG
°C
Thermal Resistance (each die operating consecutively)
Parameter
el
jl
kl
fl
RθJA
RθJA
RθJA
RθJC
RθJ-PCB
Junction-to-Ambient
Junction-to-Ambient
Junction-to-Ambient
Junction-to-Case
Junction-to-PCB Mounted
Linear Derating Factor
e
Typ.
Max.
Units
–––
12.5
20
–––
1.0
56
–––
–––
5.9
–––
°C/W
0.018
W/°C
100
Thermal Response ( Z thJA )
D = 0.50
10
0.20
0.10
0.05
1
0.02
0.01
τJ
0.1
R1
R1
τJ
τ1
R2
R2
R3
R3
τA
τ1
τ2
τ2
τ3
τ3
τ4
τ4
Ci= τi/Ri
Ci= τi/Ri
0.01
0.001
1E-006
0.0001
τA
τi (sec)
3.1440
0.000878
23.201
0.291662
19.855
1.970485
9.7220
0.027200
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthja + Tc
SINGLE PULSE
( THERMAL RESPONSE )
1E-005
Ri (°C/W)
R4
R4
0.001
0.01
0.1
1
10
t1 , Rectangular Pulse Duration (sec)
Fig 3. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient 
Notes:
‰ Mounted on minimum footprint full size board with metalized
ƒ Surface mounted on 1 in. square Cu board, steady state.
„ TC measured with thermocouple incontact with top (Drain) of part. back and with small clip heatsink.
Š Rθ is measured at TJ of approximately 90°C.
ˆ Used double sided cooling, mounting pad with large heatsink.
ƒ Surface mounted on 1 in. square Cu
board (still air).
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‰ Mounted on minimum footprint full size board with metalized
back and with small clip heatsink. (still air)
3
IRF6723M2DTR/TR1PbF
1000
1000
ID, Drain-to-Source Current (A)
100
BOTTOM
10
TOP
ID, Drain-to-Source Current (A)
TOP
VGS
10V
5.0V
4.5V
4.0V
3.5V
3.0V
2.8V
2.5V
100
1
0.1
2.5V
10
2.5V
≤60µs PULSE WIDTH
Tj = 25°C
0.01
0.1
BOTTOM
1
Tj = 175°C
100
0.1
Fig 4. Typical Output Characteristics
100
2.0
ID = 15A
VDS = 15V
≤60µs PULSE WIDTH
Typical RDS(on) (Normalized)
ID, Drain-to-Source Current (A)
10
Fig 5. Typical Output Characteristics
1000
100
10
T J = 175°C
T J = 25°C
T J = -40°C
1
0.1
V GS = 10V
V GS = 4.5V
1.5
1.0
0.5
1
2
3
4
5
6
Fig 7. Normalized On-Resistance vs. Temperature
Fig 6. Typical Transfer Characteristics
10000
-60 -40 -20 0 20 40 60 80 100120140160180
T J , Junction Temperature (°C)
VGS, Gate-to-Source Voltage (V)
22
VGS = 0V,
f = 1 MHZ
C iss = C gs + C gd, C ds SHORTED
C rss = C gd
18
Typical RDS(on) ( mΩ)
Ciss
1000
Coss
T J = 25°C
Vgs = 3.5V
Vgs = 4.0V
Vgs = 4.5V
Vgs = 5.0V
Vgs = 10V
20
C oss = C ds + C gd
C, Capacitance(pF)
1
V DS, Drain-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
16
14
12
10
8
Crss
6
4
100
0.1
1
10
100
VDS, Drain-to-Source Voltage (V)
Fig 8. Typical Capacitance vs.Drain-to-Source Voltage
4
≤60µs PULSE WIDTH
1
10
VGS
10V
5.0V
4.5V
4.0V
3.5V
3.0V
2.8V
2.5V
0
25
50
75
100
125
150
ID, Drain Current (A)
Fig 9. Typical On-Resistance vs.
Drain Current and Gate Voltage
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IRF6723M2DTR/TR1PbF
1000
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
1000
100
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100
T J = 175°C
T J = 25°C
T J = -40°C
10
1
100µsec
1msec
10
DC
10msec
1
Tc = 25°C
Tj = 175°C
Single Pulse
VGS = 0V
0
0.1
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
0
VSD, Source-to-Drain Voltage (V)
Fig 10. Typical Source-Drain Diode Forward Voltage
ID, Drain Current (A)
40
30
20
10
0
50
75
100
125
150
100
3.0
2.5
2.0
1.5
ID = 25µA
ID = 250µA
ID = 1.0mA
1.0
ID = 1.0A
0.5
-75 -50 -25 0
175
25 50 75 100 125 150 175 200
T J , Temperature ( °C )
T C , Case Temperature (°C)
Fig 13. Typical Threshold Voltage vs. Junction
Temperature
Fig 12. Maximum Drain Current vs. Case Temperature
300
EAS , Single Pulse Avalanche Energy (mJ)
80
Gfs, Forward Transconductance (S)
10
Fig 11. Maximum Safe Operating Area
Typical VGS(th) Gate threshold Voltage (V)
50
25
1
VDS, Drain-to-Source Voltage (V)
T J = 25°C
60
T J = 175°C
40
20
V DS = 15V
380µs PULSE WIDTH
2
ID
1.9A
3.0A
BOTTOM 12A
TOP
250
200
150
100
50
0
0
0
10
20
30
ID,Drain-to-Source Current (A)
40
25
50
75
100
125
150
175
Starting T J , Junction Temperature (°C)
Fig 14. Typ. Forward Transconductance vs. Drain Current Fig 15. Maximum Avalanche Energy vs. Drain Current
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5
IRF6723M2DTR/TR1PbF
100
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆Tj = 150°C and
Tstart =25°C (Single Pulse)
Avalanche Current (A)
Duty Cycle = Single Pulse
10
0.01
0.05
0.10
1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆Τ j = 25°C and
Tstart = 150°C.
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 16. Typical Avalanche Current vs.Pulsewidth
80
TOP
Single Pulse
BOTTOM 1.0% Duty Cycle
ID = 12A
EAR , Avalanche Energy (mJ)
70
60
50
40
30
20
10
0
25
50
75
100
125
150
Starting T J , Junction Temperature (°C)
Fig 17. Maximum Avalanche Energy
vs. Temperature
6
175
Notes on Repetitive Avalanche Curves , Figures 16, 17:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of Tjmax. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 19a, 19b.
4. PD (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 16, 17).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see figure 11)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
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IRF6723M2DTR/TR1PbF
Id
Vds
Vgs
L
VCC
DUT
0
20K
1K
Vgs(th)
S
Qgodr
Fig 18a. Gate Charge Test Circuit
Qgs2 Qgs1
Qgd
Fig 18b. Gate Charge Waveform
V(BR)DSS
tp
15V
DRIVER
L
VDS
D.U.T
RG
+
- VDD
IAS
20V
I AS
0.01Ω
tp
Fig 19a. Unclamped Inductive Test Circuit
VDS
VGS
RG
A
RD
Fig 19b. Unclamped Inductive Waveforms
VGS
90%
D.U.T.
+
- VDD
V10V
GS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 20a. Switching Time Test Circuit
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10%
VDS
td(off)
tf
td(on)
tr
Fig 20b. Switching Time Waveforms
7
IRF6723M2DTR/TR1PbF
D.U.T
Driver Gate Drive
ƒ
+
-
-
„
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
+
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt

RG
•
•
•
•
di/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
P.W.
Period
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
‚
D=
Period
P.W.
+
V DD
+
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor
Current
Inductor Curent
-
ISD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 19. Diode Reverse Recovery Test Circuit for N-Channel
HEXFET® Power MOSFETs
DirectFET™ Board Footprint, MA Outline (Medium Size Can).
Please see DirectFET application note AN-1035 for all details regarding the assembly of DirectFET.
This includes all recommendations for stencil and substrate designs.
CL
G = GATE
D = DRAIN
S = SOURCE
D
D
8
D
G
G
S
S
D
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IRF6723M2DTR/TR1PbF
DirectFET™ Outline Dimension, MA Outline (Medium Size Can).
Please see AN-1035 for DirectFET assembly details and stencil and substrate design recommendations
DIMENSIONS
METRIC
CODE
A
B
C
D
E
F
G
H
J
K
L
M
R
P
S
IMPERIAL
MAX
MIN MAX
MIN
0.250
6.25
6.35
0.246
0.199
4.80 5.05
0.189
0.156
3.85
3.95
0.152
0.018
0.35
0.45
0.014
0.024
0.58
0.62
0.023
0.020
0.48
0.52
0.019
0.044
1.08 1.12
0.043
0.020
0.48
0.52
0.019
0.017
0.38
0.42
0.015
0.059
1.40 1.50
0.055
0.118
2.90 3.00
0.114
0.616 0.676 0.0235 0.0274
0.020 0.080 0.0008 0.0031
0.007
0.08
0.17
0.003
0.008
0.155 0.195 0.006
DirectFET™ Part Marking
GATE MARKING
LOGO
PART NUMBER
BATCH NUMBER
DATE CODE
Line above the last character of
the date code indicates "Lead-Free"
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9
IRF6723M2DTR/TR1PbF
DirectFET™ Tape & Reel Dimension (Showing component orientation).
NOTE: Controlling dimensions in mm
Std reel quantity is 4800 parts. IRF6723M2D
REEL DIMENSIONS
STANDARD OPTION (QTY 4800)
IMPERIAL
METRIC
CODE
MIN
MIN
MAX
MAX
A
12.992 N.C
330.0
N.C
B
0.795
20.2
N.C
N.C
C
0.504
12.8
0.520
13.2
D
0.059
1.5
N.C
N.C
E
3.937
100.0
N.C
N.C
F
N.C
N.C
0.724
18.4
G
0.488
12.4
0.567
14.4
H
0.469
11.9
0.606
15.4
LOADED TAPE FEED DIRECTION
NOTE: CONTROLLING
DIMENSIONS IN MM
CODE
A
B
C
D
E
F
G
H
DIMENSIONS
METRIC
IMPERIAL
MIN
MIN
MAX
MAX
0.311
0.319
7.90
8.10
0.154
0.161
3.90
4.10
0.469
0.484
11.90
12.30
0.215
0.219
5.45
5.55
0.201
0.209
5.10
5.30
0.256
0.264
6.50
6.70
0.059
1.50
N.C
N.C
0.059
1.50
1.60
0.063
Data and specifications subject to change without notice.
This product has been designed and qualified to MSL1 rating for the Consumer market.
Additional storage requirement details for DirectFET products can be found in application note AN1035 on IR’s Web site.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.12/2009
10
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