May 1997 NDH8503N Dual N-Channel Enhancement Mode Field Effect Transistor General Description Features TM SuperSOT -8 N-Channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications such as notebook computer power management, and other battery powered circuits where fast switching, and low in-line power loss are needed in a very small outline surface mount package. 3.8 A, 30 V. RDS(ON) = 0.033 Ω @ VGS = 10 V RDS(ON) = 0.05 Ω @ VGS = 4.5 V. Proprietary SuperSOTTM-8 package design using copper lead frame for superior thermal and electrical capabilities. High density cell design for extremely low RDS(ON). Exceptional on-resistance and maximum DC current capability. ____________________________________________________________________________________________ 5 4 6 3 7 2 8 1 Absolute Maximum Ratings T A = 25°C unless otherwise note Symbol Parameter NDH8503N Units VDSS VGSS Drain-Source Voltage 30 V Gate-Source Voltage ±20 V ID Drain Current - Continuous 3.8 A PD Maximum Power Dissipation TJ,TSTG Operating and Storage Temperature Range (Note 1) - Pulsed 10.5 (Note 1 ) 0.8 W -55 to 150 °C 156 °C/W 40 °C/W THERMAL CHARACTERISTICS RθJA Thermal Resistance, Junction-to-Ambient RθJC Thermal Resistance, Junction-to-Case © 1997 Fairchild Semiconductor Corporation (Note 1) (Note 1) NDH8503N Rev.C ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units 1 µA OFF CHARACTERISTICS BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA IDSS Zero Gate Voltage Drain Current VDS = 24 V, VGS = 0 V 30 V TJ = 55oC 10 µA IGSSF Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V 100 nA IGSSR Gate - Body Leakage, Reverse VGS = -20 V, VDS= 0 V -100 nA V ON CHARACTERISTICS (Note 2) VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 µA TJ = 125oC RDS(ON) Static Drain-Source On-Resistance 1 1.67 2 0.8 1.04 1.6 0.027 0.033 0.04 0.06 0.041 0.05 VGS = 10 V, ID = 3.8 A TJ = 125oC VGS = 4.5 V, ID = 3.2 A ID(on) gFS On-State Drain Current Forward Transconductance VGS = 10 V, VDS = 5 V 10.5 VGS = 4.5 V, VDS = 5 V 9 Ω A VDS = 5 V, ID = 3.8 A 9 S VDS = 15 V, VGS = 0 V, f = 1.0 MHz 500 pF 310 pF 125 pF DYNAMIC CHARACTERISTICS Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2) tD(on) Turn - On Delay Time tr Turn - On Rise Time tD(off) Turn - Off Delay Time tf Turn - Off Fall Time Qg Total Gate Charge Qgs Gate-Source Charge Qgd Gate-Drain Charge VDD = 10 V, ID = 1 A, VGS = 10 V, RGEN = 6 Ω VDS = 10 V, ID = 3.8 A, VGS = 4.5 V 10 18 ns 15 28 ns 20 35 ns 9 18 ns 18 25 nC 1.8 nC 4.2 nC NDH8503N Rev.C ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units 0.67 A 1.2 V DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS IS Maximum Continuous Drain-Source Diode Forward Current VSD Drain-Source Diode Forward Voltage VGS = 0 V, IS = 0.67 A (Note 2) 0.72 otes: 1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design. PD(t ) = T J −TA R θJA(t ) = T J −TA R θJC+RθCA(t ) = I 2D (t ) × RDS (ON ) TJ Typical RθJA for single device operation using the board layout shown below on 4.5"x5" FR-4 PCB in a still air environment: 156oC/W when mounted on a 0.0025 in2 pad of 2oz copper. Scale 1 : 1 on letter size paper. 2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%. NDH8503N Rev.C Typical Electrical Characteristics 2.5 20 6.0 5.0 VGS = 3.5V 4.5 16 2.25 R DS(on) , NORMALIZED 4.0 12 3.5 8 4 3.0 DRAIN-SOURCE ON-RESISTANCE I D , DRAIN-SOURCE CURRENT (A) V GS =10V 0 2 4.0 1.75 4.5 5.0 1.5 6.0 1.25 7.0 10 1 0.75 0 0.5 V DS 1 1.5 2 , DRAIN-SOURCE VOLTAGE (V) 2.5 3 0 Figure 1. On-Region Characteristics. V R DS(on), NORMALIZED 1 .4 1 .2 1 0 .8 -25 0 25 50 75 100 125 DRAIN-SOURCE ON-RESISTANCE R DS(ON) , NORMALIZED DRAIN-SOURCE ON-RESISTANCE GS V GS = 10V 20 = 10V 1.75 TJ = 125°C 1.5 1.25 25°C 1 0.75 -55°C 0.5 0.25 150 0 4 T , JUNCTION TEMPERATURE (°C) I J D 8 12 , DRAIN CURRENT (A) 16 20 Figure 4. On-Resistance Variation with Drain Current and Temperature. Figure 3. On-Resistance Variation with Temperature. 1.2 T = -55°C J V DS = 5V 25°C 16 V th, NORMALIZED 125°C 12 D 8 4 0 1 1.5 V 2 2.5 3 3.5 , GATE TO SOURCE VOLTAGE (V) GS Figure 5. Transfer Characteristics. 4 4.5 GATE-SOURCE THRESHOLD VOLTAGE 20 I , DRAIN CURRENT (A) 16 2 I D = 3.8A 0 .6 -50 8 12 I D , DRAIN CURRENT (A) Figure 2. On-Resistance Variation with Gate Voltage and Drain Current. 1 .8 1 .6 4 VDS = VGS I D = 250µA 1.1 1 0.9 0.8 0.7 0.6 -50 -25 0 25 50 75 100 T , JUNCTION TEMPERATURE (°C) 125 150 J Figure 6. Gate Threshold Variation with Temperature. NDH8503N Rev.C Typical Electrical Characteristics 15 I D = 250µA 1.08 1.04 1 TJ = 125°C 1 25°C -55°C 0 .1 0 .0 1 0 .0 0 1 S 0.96 0.92 -50 -25 0 T 25 50 75 100 , JUNCTION TEMPERATURE (°C) J 125 150 0 .0 0 0 1 0 1500 V GS, GATE-SOURCE VOLTAGE (V) Ciss Coss 300 200 Crss f = 1 MHz V GS = 0 V 0 .2 0 .5 V 1 .2 VDS = 10V DS 1 3 5 10 8 4 2 0 30 0 5 15 Figure 10. Gate Charge Characteristics. t on t d(on) t off tr RL t d(off) tf 90% 90% V OUT D VOUT 10% 10% INVERTED DUT G 20 Q g , GATE CHARGE (nC) VDD R GEN 10 , DRAIN TO SOURCE VOLTAGE (V) V IN 15V 20V 6 Figure 9. Capacitance Characteristics. VGS 0 .4 0.6 0 .8 1 , BODY DIODE FORWARD VOLTAGE (V) I D = 3.8A 500 50 0 .1 SD 10 1000 800 100 0 .2 V Figure 8. Body Diode Forward Voltage Variation with Current and Temperature. Figure 7. Breakdown Voltage Variation with Temperature. CAPACITANCE (pF) VGS =0V 5 I , REVERSE DRAIN CURRENT (A) BV DSS , NORMALIZED DRAIN-SOURCE BREAKDOWN VOLTAGE 1.12 90% S V IN 50% 50% 10% PULSE WIDTH Figure 11. Switching Test Circuit. Figure 12. Switching Waveforms. NDH8503N Rev.C Typical Electrical and Thermal Characteristics 20 20 10 TJ = -55°C 5 16 12 I , DRAIN CURRENT (A) 25°C 125°C 4 S RD (O N) LIM IT 10 0u s 1m s 10 10 1 V GS = 10V s 10 s DC SINGLE PULSE 0.1 R 0.03 ms 0m 1s 0.3 D 8 θJ A = See Note 1 TA = 25°C g FS , TRANSCONDUCTANCE (SIEMENS) V DS = 5V 0 0 4 8 I D 12 16 20 0.01 0.1 0.2 0.5 1 2 5 10 V , DRAIN-SOURCE VOLTAGE (V) , DRAIN CURRENT (A) 30 50 DS Figure 13. Transconductance Variation with Drain Current and Temperature. Figure 14. Maximum Safe Operating Area. TRANSIENT THERMAL RESISTANCE r(t), NORMALIZED EFFECTIVE 1 D = 0.5 R 0.2 0.1 0.1 θJA (t) = r(t) * R θJA R JA = See Note 1 θ 0.05 P(pk) 0.02 t1 0.01 0.01 t2 Single Pulse TJ - T =P *R (t) θJA Duty Cycle, D = t1 / t2 A 0.001 0.0001 0.001 0.01 0.1 t 1 , TIME (sec) 1 10 100 300 Figure 15. Transient Thermal Response Curve. Note: Thermal characterization performed using the conditions described in note 1. Transient thermal response will change depending on the circuit board design. NDH8503N Rev.C