INTEGRATED CIRCUITS DATA SHEET OQ2535HP SDH/SONET STM16/OC48 multiplexer Product specification Supersedes data of 1997 Nov 27 File under Integrated Circuits, IC19 1999 Oct 04 Philips Semiconductors Product specification SDH/SONET STM16/OC48 multiplexer OQ2535HP FEATURES GENERAL DESCRIPTION • Normal and loop (test) modes The OQ2535HP is a 32-channel multiplexer intended for use in STM16/OC48 applications. It combines data from a total of 32 × 78 Mbits/s input channels onto a single 2.5 Gbits/s output channel. It features 3.3 V TTL data inputs and a 5 V TTL clock output at the low speed interface, and CML compatible inputs and outputs at the high speed interface. • 3.3 V TTL compatible data inputs • Differential Current-Mode Logic (CML) clock and data outputs • 5 V TTL clock output (low speed interface) • High input sensitivity (100 mV for the high speed clock input) • Boundary Scan Test (BST) at low speed interface, in accordance with “IEEE Std 1149.1-1990” • Low power dissipation (typically 1.65 W). ORDERING INFORMATION PACKAGE TYPE NUMBER OQ2535HP NAME DESCRIPTION VERSION HLQFP100 plastic heat-dissipating low profile quad flat package; 100 leads; body 14 × 14 × 1.4 mm SOT470-1 BLOCK DIAGRAM handbook, full pagewidth 78 D0 Mbits/s to D31 ENL (1) 4× 8 : 1 MUX 32 TRST TMS TCK TDI TDO CDIV 4 : 1 MUX 82 62 65 OQ2535HP SYNCHRONIZATION 58 2 5 3 7 6 66 68 69 2.5 GHz DIVIDE BY 8 71 DIVIDE BY 4 72 74 BAND GAP REFERENCE 1 61 38 REFC1 REFC2 10 BGCAP1 75 BAND GAP REFERENCE 2 COUT COUTQ DLOOP DLOOPQ CLOOP CLOOPQ 12, 39, 87, 88 5 4 31 BGCAP2 VCC(T) VDD VEE VCC GND 16 Fig.1 Block diagram. 2 CIN CINQ DIOA DIOC (2) 14, 37, 63, 85, 86 78 (1) See Chapter “Pinning” for D0 to D31 pin numbers. (2) Pins 1, 4, 8, 9, 11, 15, 17, 21, 25, 36, 40, 56, 64, 67, 70, 73, 76, 77, 79, 80, 81, 84, 89, 92 to 98 and 100. 1999 Oct 04 DOUTQ 622 MHz 78 MHz 13 DOUT clock 59 BST LOGIC SYNSEL2 91 83 load pulse SYNSEL1 4 90 2.5 Gbits/s 622 Mbits/s 60 MGK351 Philips Semiconductors Product specification SDH/SONET STM16/OC48 multiplexer OQ2535HP PINNING SYMBOL PIN TYPE(1) DESCRIPTION GND 1 S ground TRS 2 I test reset input for BST mode (active LOW) TCK 3 I test clock input for BST mode GND 4 S ground TMS 5 I test mode select input for BST mode TDO 6 O serial test data output for BST mode TDI 7 I serial test data input for BST mode GND 8 S ground GND 9 S ground BGCAP1 10 A pin for connecting external band gap decoupling capacitor (4 × 8 : 1 MUX) GND 11 S ground VEE 12 S supply voltage (−4.5 V) CDIV 13 O 78 MHz clock output VDD 14 S supply voltage (+3.3 V) GND 15 S ground VCC(T) 16 S supply voltage for TTL buffer (+5.0 V); not connected internally to VCC GND 17 S ground D31 18 I 78 Mbits/s data input channel for D31 D27 19 I 78 Mbits/s data input channel for D27 D23 20 I 78 Mbits/s data input channel for D23 GND 21 S ground D19 22 I 78 Mbits/s data input channel for D19 D15 23 I 78 Mbits/s data input channel for D15 D11 24 I 78 Mbits/s data input channel for D11 GND 25 S ground D7 26 I 78 Mbits/s data input channel for D7 D3 27 I 78 Mbits/s data input channel for D3 D30 28 I 78 Mbits/s data input channel for D30 D26 29 I 78 Mbits/s data input channel for D26 D22 30 I 78 Mbits/s data input channel for D22 D18 31 I 78 Mbits/s data input channel for D18 D14 32 I 78 Mbits/s data input channel for D14 D10 33 I 78 Mbits/s data input channel for D10 D6 34 I 78 Mbits/s data input channel for D6 D2 35 I 78 Mbits/s data input channel for D2 GND 36 S ground VDD 37 S supply voltage (+3.3 V) REFC2 38 A pin for connecting external reference decoupling capacitor (3.3 V CMOS reference) VEE 39 S supply voltage (−4.5 V) 1999 Oct 04 3 Philips Semiconductors Product specification SDH/SONET STM16/OC48 multiplexer OQ2535HP PIN TYPE(1) GND 40 S ground D29 41 I 78 Mbits/s data input channel for D29 D25 42 I 78 Mbits/s data input channel for D25 D21 43 I 78 Mbits/s data input channel for D21 D17 44 I 78 Mbits/s data input channel for D17 D13 45 I 78 Mbits/s data input channel for D13 D9 46 I 78 Mbits/s data input channel for D9 D5 47 I 78 Mbits/s data input channel for D5 D1 48 I 78 Mbits/s data input channel for D1 D28 49 I 78 Mbits/s data input channel for D28 D24 50 I 78 Mbits/s data input channel for D24 D20 51 I 78 Mbits/s data input channel for D20 D16 52 I 78 Mbits/s data input channel for D16 D12 53 I 78 Mbits/s data input channel for D12 D8 54 I 78 Mbits/s data input channel for D8 D4 55 I 78 Mbits/s data input channel for D4 GND 56 S ground D0 57 I 78 Mbits/s data input channel for D0 SYNSEL2 58 I selection input 2 for synchronization pulse timing SYNSEL1 59 I selection input 1 for synchronization pulse timing SYMBOL DESCRIPTION VCC 60 S supply voltage (+5.0 V) REFC1 61 A pin for connecting external reference decoupling capacitor (for standard TTL reference) ENL 62 I loop mode enable (active LOW) VDD 63 S supply voltage (+3.3 V) GND 64 S ground DLOOP 65 O data output to demultiplexer IC OQ2536 (loop mode) DLOOPQ 66 O inverted data output to demultiplexer IC OQ2536 (loop mode) GND 67 S ground CLOOP 68 O clock output to demultiplexer IC OQ2536 (loop mode) CLOOPQ 69 O inverted clock output to demultiplexer IC OQ2536 (loop mode) GND 70 S ground CIN 71 I clock input from VCO IC CINQ 72 I inverted clock input from VCO IC GND 73 S ground DIOA 74 A anode of temperature diode array DIOC 75 A cathode of temperature diode array GND 76 S ground GND 77 S ground BGCAP2 78 A pin for connecting external band gap decoupling capacitor (4 : 1 MUX) GND 79 S ground 1999 Oct 04 4 Philips Semiconductors Product specification SDH/SONET STM16/OC48 multiplexer OQ2535HP PIN TYPE(1) GND 80 S GND 81 S ground COUT 82 O clock output to laser driver IC COUTQ 83 O inverted clock output to laser driver IC SYMBOL DESCRIPTION ground GND 84 S ground VDD 85 S supply voltage (+3.3 V) VDD 86 S supply voltage (+3.3 V) VEE 87 S supply voltage (−4.5 V) VEE 88 S supply voltage (−4.5 V) GND 89 S ground DOUT 90 O data output to laser driver IC DOUTQ 91 O inverted data output to laser driver IC GND 92 S ground GND 93 S ground GND 94 S ground GND 95 S ground GND 96 S ground GND 97 S ground GND 98 S ground i.c. 99 − internally connected, to be left open-circuit GND 100 S ground Note 1. Pin type abbreviations: O = Output, I = Input, S = power Supply, A = Analog function. 1999 Oct 04 5 Philips Semiconductors Product specification 76 GND 77 GND 78 BGCAP2 79 GND 81 GND 80 GND 82 COUT 83 COUTQ 84 GND 86 VDD 85 VDD OQ2535HP 88 VEE 87 VEE 89 GND 90 DOUT 92 GND 93 GND 94 GND 95 GND 96 GND 97 GND 98 GND 99 i.c. 100 GND handbook, full pagewidth 91 DOUTQ SDH/SONET STM16/OC48 multiplexer GND 1 75 DIOC TRST 2 74 DIOA TCK 3 73 GND GND 4 72 CINQ TMS 5 71 CIN TDO 6 70 GND TDI 7 69 CLOOPQ GND 8 68 CLOOP GND 9 67 GND BGCAP1 10 66 DLOOPQ GND 11 65 DLOOP VEE 12 64 GND OQ2535HP CDIV 13 VDD 14 63 VDD 62 ENL GND 15 61 REFC1 VCC(T) 16 GND 17 60 VCC 59 SYNSEL1 D31 18 58 SYNSEL2 D27 19 57 D0 D23 20 56 GND Fig.2 Pin configuration. 1999 Oct 04 6 D24 50 D28 49 D1 48 D5 47 D9 46 D13 45 D17 44 D21 43 D25 42 D29 41 GND 40 VEE 39 REFC2 38 VDD 37 GND 36 D2 35 D6 34 D10 33 51 D20 D14 32 52 D16 D18 31 D11 24 GND 25 D22 30 53 D12 D26 29 D15 23 D30 28 54 D8 D3 27 55 D4 D19 22 D7 26 GND 21 MGK350 Philips Semiconductors Product specification SDH/SONET STM16/OC48 multiplexer FUNCTIONAL DESCRIPTION The outputs CLOOP, CLOOPQ, DLOOP and DLOOPQ are terminated internally with 100 Ω resistors to GND and are specifically designed to drive 50 Ω printed-circuit board transmission lines. The OQ2535HP is a 32-channel multiplexer intended for use in STM16/OC48 applications. It multiplexes 32 × 78 Mbits/s input channels onto a single 2.5 Gbits/s output channel. The 2.5 GHz clock connected to CIN and CINQ is terminated internally with 50 Ω to GND. The multiplexing is performed in two stages. The 32 input channels are fed into four 8 : 1 multiplexers to generate four 622 Mbits/s channels. These four channels are then combined into a single 2.5 Gbits/s data stream. Power supply connections The power supply pins need to be individually decoupled using chip capacitors mounted as close as possible to the IC. If multiple decoupling capacitors are used for a single supply node, they must be placed close to each other to avoid RF resonance. The ENL control input is used for switching between normal and loop modes. When loop mode is enabled, (ENL = LOW), the output signal is switched to DLOOP and DLOOPQ (these outputs could be connected to the DLOOP and DLOOPQ inputs on the OQ2536HP demultiplexer to form part of a test loop). To minimize low frequency switching noise in the vicinity of the OQ2535HP, all power supply lines should be filtered once by an LC-circuit with a low cut-off frequency (as shown in the application diagram, Fig.6). VCC(T) needs to be filtered separately via an LC-circuit because of the high switching currents present at the CDIV TTL output. As this current contains only 78 MHz harmonics, filtering can be achieved with relatively small values of L and C. The 2.5 GHz clock at CIN and CINQ is used as the system reference. It is divided down to 78 MHz and made available on the CDIV TTL output for timing the input data (D0 to D31). Low bit rate stage: 4 × 8 : 1 MUX Ground connection This part of the circuit consists of four 8-bit shift registers, each acting as an 8 : 1 multiplexer, together with a synchronization block. The ground connection on the printed-circuit board needs to be a large copper area fill connected to a common ground plane with low inductance. The 32 data input signals are loaded into the shift registers before being shifted out on a 622 MHz clock. RF connections The load pulse for the shift registers is generated in the synchronization block. The inputs SYNSEL1 and SYNSEL2 can be used to adjust the phase of the load pulse with respect to the input data (see Table 3) to synchronize the data and clock signals. A coupled stripline or microstrip with an odd mode characteristic impedance of 50 Ω (nominal value) should be used for the RF connections on the printed-circuit board. The connections should be kept as short as possible. This applies to the CML differential line pairs CIN and CINQ, DOUT and DOUTQ, COUT and COUTQ, DLOOP and DLOOPQ, and CLOOP and CLOOPQ. In addition, the following lines should not vary in length by more than 5 mm: High bit rate stage: 4 : 1 MUX The four 622 Mbits/s data outputs from the low bit rate stage are combined into a single 2.5 Gbits/s data stream in two stages: two 2 : 1 multiplexers are used to generate two 1244 Mbits/s data streams; these signals are then fed into a third 2 : 1 multiplexer to generate the 2.5 Gbits/s data stream. • CIN and CINQ • DOUT, DOUTQ, COUT and COUTQ • DLOOP, DLOOPQ, CLOOP and CLOOPQ. The 2.5 Gbits/s serial data stream is passed either to the DOUT and DOUTQ outputs (normal mode), or to the DLOOP and DLOOPQ outputs (loop mode). The output sequence is D31 (MSB) to D0 (LSB). Data and clock output buffers are terminated internally with 100 Ω resistors to GND and are capable of driving 50 Ω loads. The unused output buffers are switched off to help minimize power dissipation. 1999 Oct 04 OQ2535HP Interface to transmit logic The 78 Mbits/s interface lines, CDIV and D0 to D31, should not vary in length by more than 20 mm. The parasitic capacitance of these lines should be as small as possible. 7 Philips Semiconductors Product specification SDH/SONET STM16/OC48 multiplexer ESD protection OQ2535HP 1 –1 1 R th h-a ≤ -------- – -------------- – R th j-c – R th c-h R th R th j-a All pads are protected by ESD protection diodes with the exception of the high frequency outputs DOUT, DOUTQ, DLOOP, DLOOPQ, COUT, COUTQ, CLOOP and CLOOPQ and clock inputs CIN and CINQ. (4) where: Rth h-a = thermal resistance from heatsink to ambient Rth c-h = thermal resistance from case to heatsink Cooling Rth j-c = thermal resistance from junction to case, see Chapter “Thermal characteristics”. In many cases it is necessary to mount a special cooling device on the package. The thermal resistance from junction to case, Rth j-c and from junction to ambient, Rth j-a, are given in Chapter “Thermal characteristics”. Since the heat-slug in the package is connected to the die, the cooling device should be electrically isolated. If for instance Rth c-h = 0.5 K/W and Rth j-a = 33 K/W then: 1 1 –1 R th h-a ≤ ----------- – ------ – 3.1 (5) 12.5 33 ≤ 17.0 K/W To calculate if a heatsink is necessary, the maximum allowed total thermal resistance Rth is calculated as: T j – T amb (1) R th = ----------------------P tot Built in temperature sensor Tj = junction temperature Three series-connected diodes have been integrated for measuring junction temperature. The diode array, accessed by means of the DIOA (anode) and DIOC (cathode) pins, has a temperature dependency of approximately −6 mV/°C. With a diode current of 1 mA, the voltage will be somewhere in the range of 1.7 to 2.5 V, depending on temperature. Tamb = ambient temperature. Boundary Scan Test (BST) interface where: Rth = total thermal resistance from junction to ambient in the application As long as Rth is greater than Rth j-a of the OQ2536HP including environmental conditions such as air flow and board layout, no heatsink is necessary. For example if Tj = 120 °C, Tamb = 55 °C and Ptot = 1.65 W, then: ( 120 – 55 ) R th = --------------------------- = 39.4 K/W (2) 1.65 Boundary scan test logic has been implemented for all digital inputs and outputs on the low frequency interface, in accordance with “IEEE Std 1149.1-1990”. All scan tests other than SAMPLE mode are available. The boundary scan test logic consists of a TAP controller, a BYPASS register, a 2-bit instruction register, a 32-bit identification register and a 36-bit boundary scan register (the last two are combined). The architecture of the TAP controller and the BYPASS register is in accordance with IEEE recommendations. The four command modes, selected by means of the instruction register, are: EXTEST (00), PRELOAD (01), IDCODE (10) and BYPASS (11). All boundary scan test inputs, TDI, TMS, TCK and TRST, have internal pull-up resistors. The maximum test clock frequency at TCK is 12 MHz. which is more than the worst case Rth j-a = 33 K/W, so no heatsink is necessary. Another example; if for safety reasons Tj should stay as low as 110 °C, while Tamb = 85 °C and Ptot = 2 W, then: ( 110 – 85 ) R th = --------------------------- = 12.5 K/W (3) 2.0 In this case extra cooling is needed. The thermal resistance of the heatsink is calculated as follows: Table 1 BST identifier code VERSION OQ 2535 (BINARY) PHILIPS SEMICONDUCTORS LSB(1) 0001 01 00 1001 1110 0111 0000 0010 101 1 Note 1. LSB is shifted out first on the TDO pin. 1999 Oct 04 8 Philips Semiconductors Product specification SDH/SONET STM16/OC48 multiplexer Table 2 BST bit order BIT NUMBER SYMBOL PIN 35 (MSB) CDIV 13 34 ENL 62 33 SYNSEL2 58 32 SYNSEL1 59 31 D31 18 30 D30 28 29 D29 41 28 D28 49 27 D27 19 26 D26 29 25 D25 42 24 D24 50 23 D23 20 22 D22 30 21 D21 43 20 D20 51 19 D19 22 18 D18 31 17 D17 44 16 D16 52 15 D15 23 14 D14 32 13 D13 45 12 D12 53 11 D11 24 10 D10 33 9 D9 46 8 D8 54 7 D7 26 6 D6 34 5 D5 47 4 D4 55 3 D3 27 2 D2 35 1 D1 48 0 (LSB)(1) D0 57 Note 1. LSB is shifted out first on the TDO pin. 1999 Oct 04 9 OQ2535HP Philips Semiconductors Product specification SDH/SONET STM16/OC48 multiplexer OQ2535HP LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER MIN. MAX. UNIT VCC, VCC(T) supply voltage −0.5 +6.0 V VEE supply voltage −6.0 +0.5 V VDD supply voltage −0.5 +5.0 V Vn DC voltage pins 18 to 20, 22 to 24, 26 to 35, 41 to 55 and 57 −0.5 VDD + 0.5 V pins 2, 3, 5, 7, 38, 61 and 62 −0.5 VCC + 0.5 V pins 65, 66, 68, 69, 71, 72, 82, 83, 90 and 91 −1.0 +0.5 V pins 10 and 78 VEE − 0.5 0.5 V pins 74 and 75 VEE − 0.5 VCC + 0.5 V pins 6 and 13 − 50 mA pins 74 and 75 − 10 mA In DC current Ptot total power dissipation − 2.35 W Tj junction temperature − 120 °C Tstg storage temperature −65 +150 °C THERMAL CHARACTERISTICS SYMBOL PARAMETER Rth j-c thermal resistance from junction to case Rth j-a thermal resistance from junction to ambient CONDITIONS VALUE UNIT 2.6 K/W airflow = 0 ft/min 33 K/W airflow = 100 ft/min 28 K/W airflow = 200 ft/min 25 K/W airflow = 400 ft/min 22 K/W airflow = 600 ft/min 20 K/W see note 1 Note 1. The thermal resistance from junction to ambient is strongly depending on the board design and airflow. The values given in the table are typical values and are measured on a single sided test board with dimensions of 76 × 114 × 1.6 mm. Better values can be obtained when mounted on multilayer boards with large ground planes. 1999 Oct 04 10 Philips Semiconductors Product specification SDH/SONET STM16/OC48 multiplexer OQ2535HP DC CHARACTERISTICS All typical values are at Tamb = 25 °C and at typical supply voltages; minimum and maximum values are valid over the entire ambient temperature range and supply voltage range. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT General VCC, VCC(T) supply voltage VEE VDD note 1 4.75 5.0 5.25 V supply voltage −4.75 −4.5 −4.25 V supply voltage 3.14 3.3 3.47 V ICC supply current − 2.3 4 mA ICC(T) supply current − 20 40 mA IEE supply current − 265 400 mA IDD supply current − 20 28 mA Ptot total power dissipation − 1.65 2.35 W Tj junction temperature − − 120 °C Tamb ambient temperature −40 − +85 °C TTL 3.3 V inputs: D0 to D31; note 2 VIL LOW-level input voltage − − 0.8 V VIH HIGH-level input voltage 2.0 − − V IIL LOW-level input current −65 − 0 µA IIH HIGH-level input current 0 − 110 µA TTL inputs: ENL, SYNSEL1, SYNSEL2, TDI, TCK, TMS and TRST VIL LOW-level input voltage − − 0.8 V VIH HIGH-level input voltage 2.0 − − V IIL LOW-level input current note 3 −100 − 0 µA IIH HIGH-level input current note 3 0 − 210 µA 50 Ω measurement system 100 250 500 mV −25 − +25 mV −600 − +250 mV for DC signal − 50 − Ω CML clock inputs: CIN and CINQ; note 4 Vi(p-p) input voltage (peak-to-peak value) VIO permitted input offset voltage VI, VIQ input voltages Zi single ended input impedance TTL outputs: CDIV and TDO; note 5 VOL LOW-level output voltage IOL = 4 mA − 0.3 0.5 V VOH HIGH-level output voltage IOH = −400 µA 2.4 4.0 − V IOZ output current in high-impedance state − − 1 µA CML outputs in normal mode: COUT, COUTQ, DOUT and DOUTQ; note 4 Vo(p-p) output voltage (peak-to-peak value) VOO output offset voltage VO, VOQ output voltages Zo output impedance 1999 Oct 04 outputs terminated externally with 50 Ω resistors 230 300 500 mV −25 0 +25 mV −600 − 0 mV for DC signal − 100 − Ω 11 Philips Semiconductors Product specification SDH/SONET STM16/OC48 multiplexer SYMBOL PARAMETER OQ2535HP CONDITIONS MIN. TYP. MAX. UNIT CML outputs in loop mode: CLOOP, CLOOPQ, DLOOP and DLOOPQ; note 4 Vo(p-p) output voltage (peak-to-peak value) VOO output offset voltage VO, VOQ output voltages Zo output impedance outputs terminated externally with 50 Ω 230 300 500 mV −25 0 +25 mV −600 − 0 mV for DC signal − 100 − Ω II(d) = 1 mA − 2.1 − V Temperature diode array ∆VDIOA-DIOC diode voltage range; note 6 Notes 1. VCC and VCC(T) require the same power supply voltage. However, a filter is needed to isolate VCC(T) because of the high peak currents that occur at 78 MHz. 2. The output sequence is D31 (MSB) to D0 (LSB). 3. Only for inputs ENL, SYNSEL1 and SYNSEL2. TDI, TMS, TCK and TRST are connected to VCC through 90 kΩ resistors. 4. See Fig.3 for symbol definitions. 5. TDO is switched to high impedance state if BST is inactive. 6. The temperature diode array can be used to measure the temperature of the die. The temperature dependency of this voltage is approximately −6 mV/K. handbook, full pagewidth CML INPUT CML OUTPUT VI(max) GND GND VO(max) VIQH VOQH VOH VIH Vi(p-p) VIQL VIL Vo(p-p) VOQL VOL VIO VO(min) VI(min) Fig.3 Logic level symbol definitions for CML. 1999 Oct 04 12 VOO MGK144 Philips Semiconductors Product specification SDH/SONET STM16/OC48 multiplexer OQ2535HP TIMING Typical values at Tamb = 25 °C and at typical supply voltages; minimum and maximum values are valid over the entire ambient temperature range and supply voltage range. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT TTL input timing fclk(CIN) = 2.488 GHz − 77.76 − tr(CDIV), tf(CDIV) CDIV rise/fall time capacitive load of 15 pF − − 2600 ps tsu input data set-up time note 1 1200 − − ps th input data hold time note 1 2600 − − ps fclk(CIN) = 2.488 GHz − 2.488 − GHz fclk(CDIV) low speed output clock frequency MHz CML output timing; note 2 fclk(COUT) output clock frequency tCDV clock edge to data valid time − − 250 ps tDI data invalid time − − 120 ps tr(CML), tf(CML) CML output rise/fall time − − 150 ps δCOUT output clock duty factor 45 50 55 % Notes 1. The set-up and hold times given are valid for SYNSEL1 = SYNSEL2 = HIGH. Different SYNSEL1, SYNSEL2 combinations will produce different set-up and hold times (see Table 3). 2. All CML outputs must be terminated externally with 50 Ω to GND. The specified timing characteristics are applicable in both normal and loop modes. Table 3 Timing relationship between the clock edge and the data valid region (minimum values) SYNSEL2 SYNSEL1 tsu th UNIT HIGH HIGH 1200 2600 ps HIGH LOW 2800 1000 ps LOW HIGH 1700 2100 ps LOW LOW 3300 500 ps 1999 Oct 04 13 Philips Semiconductors Product specification SDH/SONET STM16/OC48 multiplexer OQ2535HP Tcy(CDIV) handbook, full pagewidth tf tr 2.0 V 1.5 V CDIV 0.8 V 1.5 V D0 to D31 th valid data MGK352 tsu Fig.4 TTL input timing. handbook, full pagewidth tf Tcy(COUT) tr +100 mV COUT − COUTQ, CLOOP − CLOOPQ 0V −100 mV +100 mV DOUT − DOUTQ, DLOOP − DLOOPQ −100 mV MGK353 tCDV tDI Fig.5 CML output timing. 1999 Oct 04 14 Philips Semiconductors Product specification SDH/SONET STM16/OC48 multiplexer OQ2535HP APPLICATION INFORMATION system reference handbook, full pagewidth DATA INTERFACE PHASE DETECTOR D0 to D31 CDIV 13 D0 to D31 10 VEE BGCAP1 10 nF VEE 78 ENL microcontroller 61 BGCAP2 10 nF PLL LOOP FILTER REFC1 68 nF 62 38 REFC2 68 nF TDI TCK BOUNDARY SCAN TEST EQUIPMENT 59 7 58 3 TMS TRST TDO 5 71 2 72 16 OQ2536 DLOOPQ DMUX CLOOP CLOOPQ DLOOP DLOOPQ CLOOP CLOOPQ 65 (1) 66 VCO 2.488 GHz CINQ ferrite bead VCC VCC(T) 100 nF ferrite bead 1 µF 100 nF 1 µF ferrite bead VDD 100 nF 69 (3) 90 D DOUTQ DQ COUT CL 100 nF GND COUTQ CLQ OQ2545 LASER DRIVER LA LAQ LASER DIODE MGK354 Fig.6 Application diagram. 15 1 µF ferrite bead VEE 83 82 91 DOUT 1999 Oct 04 CIN 68 (2) (1) VDD pins 14, 37, 63, 85 and 86 should be connected together, and to the filter network. (2) VEE pins 12, 39, 87 and 88 should be connected together, and to the filter network. (3) All GND pins (pins 1, 4, 8, 9, 11, 15, 17, 21, 25, 36, 40, 56, 64, 67, 70, 73, 76, 77, 79, 80, 81, 84, 89, 92 to 98 and 100) must be connected directly to the printed-circuit board ground plane. GND or VCC SYNSEL2 OQ2535 6 60 DLOOP SYNSEL1 1 µF Philips Semiconductors Product specification SDH/SONET STM16/OC48 multiplexer OQ2535HP PACKAGE OUTLINE HLQFP100: plastic heat-dissipating low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm SOT470-1 c y X A 51 75 50 Z E 76 e J E HE A A2 w M (A 3) A1 bp θ Lp pin 1 index L 100 detail X 26 1 25 ZD e v M A w M bp D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 1.6 0.20 0.05 1.5 1.3 0.25 0.28 0.16 0.18 0.12 14.1 13.9 14.1 13.9 0.5 HD HE J(2) 16.25 16.25 10.15 15.75 15.75 9.15 L Lp v w y 1.0 0.75 0.45 0.2 0.12 0.1 Z D (1) Z E (1) θ 1.15 0.85 7 0o 1.15 0.85 Notes 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. 2. Heatsink intrusion 0.0127 maximum. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 97-01-13 SOT470-1 1999 Oct 04 EUROPEAN PROJECTION 16 o Philips Semiconductors Product specification SDH/SONET STM16/OC48 multiplexer • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: 1999 Oct 04 OQ2535HP 17 Philips Semiconductors Product specification SDH/SONET STM16/OC48 multiplexer OQ2535HP Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE REFLOW(1) WAVE BGA, LFBGA, SQFP, TFBGA not suitable suitable(2) HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not PLCC(3), SO, SOJ suitable LQFP, QFP, TQFP SSOP, TSSOP, VSO suitable suitable suitable not recommended(3)(4) suitable not recommended(5) suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 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