TI SN65HVD256

SN65HVD255
SN65HVD256, SN65HVD257
www.ti.com
SLLSEA2B – DECEMBER 2011 – REVISED JUNE 2012
CAN Transceivers with Fast Loop Times for Highly Loaded Networks and Features For
Functional Safety Networks
Check for Samples: SN65HVD255, SN65HVD256, SN65HVD257
FEATURES
DESCRIPTION
•
•
This CAN transceiver meets the ISO1189-2 High
Speed CAN (Controller Area Network) Physical Layer
standard. It is designed for data rates in excess of 1
megabit per second (Mbps) in short networks, and
enhanced timing margin and higher data rates in long
and highly-loaded networks. The device provides
many protection features to enhance device and
CAN-network robustness. The SN65HVD257 adds
additional features, allowing easy design of redundant
and multi-topology networks with fault indication for
higher levels of functional safety in the CAN system.
1
•
•
•
•
Meets the Requirements of ISO11898-2
'Turbo CAN': Short Propagation Delay Times
and Fast Loop Times; Higher Data Rates in
Network; Enhances System Timing Margins
I/O Voltage Range Supports 3.3V and 5V MCUs
Ideal Passive Behavior When Unpowered
– Bus Pins are High Impedance (no load to
operating bus)
– Logic Pins are High Impedance
– Power Up/Down With Glitch Free Operation
On Bus
Protection Features:
– ESD Protection of Bus Pins
– HBM ESD Protection Exceeds ±12kV
– Bus Fault Protection –27V to 40V
– Undervoltage Protection on Supply Pins
– Driver Dominant Time Out (TXD DTO)
– SN65HVD257: Receiver Dominant Time Out
(RXD DTO)
– SN65HVD257: FAULT Output Pin
– Thermal Shutdown Protection
Characterized for –40°C to 125°C Operation
NC / VRXD / FAULT
(See Note A)
5
VCC
VCC
3
FAULT LOGIC
MUX (See Note A)
VCC
OVER
TEMPERATURE
7
TXD
S
1
DOMINANT
TIME OUT
8
6
CANH
CANL
MODE SELECT
UNDER
VOLTAGE
VCC or V RXD (See Note B)
RXD
4
LOGIC
OUTPUT
DOMINANT
TIME OUT
(See Note B)
2
GND
APPLICATIONS
•
•
•
•
•
•
•
1Mbps Operation in Highly Loaded CAN
Networks Down to 10kbps Networks Using
TXD DTO
Industrial Automation, Control, Sensors and
Drive Systems
Building and Climate Control Automation
Security Systems
Telecom Base Station Status and Control
SN65HVD257: Functional Safety With
Redundant and Multi-topology CAN networks
CAN Bus Standards Such as CANopen,
DeviceNet, NMEA2000, ARNIC825, ISO11783,
CAN Kingdom, CANaerospace
A.
Pin 5 function is device dependent; NC on
SN65HVD255, VRXD for RXD output levelshifting device on SN65HVD256, and
FAULT Output on SN65HVD257
B.
RXD logic output is driven to 5V VCC on
5V-only supply devices (SN65HVD255,
SN65HVD257) and driven to VRXD on
output level-shifting device (SN65HVD256).
C.
RXD (Receiver) Dominant State Time Out
is a device dependent option available only
on SN65HVD257.
Figure 1. Functional Block Diagram
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2012, Texas Instruments Incorporated
SN65HVD255
SN65HVD256, SN65HVD257
SLLSEA2B – DECEMBER 2011 – REVISED JUNE 2012
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Figure 2. D PACKAGE (TOP VIEW)
SN65HVD255
SN65HVD257
SN65HVD256
TXD
1
8
S
TXD
1
8
S
TXD
1
8
S
GND
2
7
CANH
GND
2
7
CANH
GND
2
7
CANH
VCC
3
6
CANL
VCC
3
6
CANL
VCC
3
6
CANL
RXD
4
5
NC
RXD
4
5
VRXD
RXD
4
5
FAULT
5V Supply and Fault
Output
5V Supply with RXD
Level-Shifting
5V Supply
DEVICE OPTIONS
PART NUMBER
I/O
SUPPLY
for RXD
TXD
DTO
RXD
DTO
FAULT
Output
COMMENT
SN65HVD255
No
Yes
No
No
'251 and '1050 functional upgrade with 'Turbo CAN' fast loop times and
TXD DTO protection allowing data rates down to 10kbps
SN65HVD256
Yes
Yes
No
No
'251 and '1050 functional upgrade with 'Turbo CAN' fast loop times and
TXD DTO protection allowing data rates down to 10kbps. RXD output
level shifting via RXD supply input.
SN65HVD257
No
Yes
Yes
Yes
'251 and '1050 functional upgrade with 'Turbo CAN' fast loop times,
TXD & RXD DTO protection allowing data rates down to 10kbps and
fault output pin
PIN FUNCTIONS
PIN
NAME
NO.
TYPE
TXD
1
I
GND
2
GND
VCC
3
Supply
RXD
4
O
NC
5
NC
VRXD
Supply
FAULT
DESCRIPTION
CAN transmit data input (LOW for dominant and HIGH for recessive bus states)
Ground connection
Transceiver 5V supply voltage
CAN receive data output (LOW for dominant and HIGH for recessive bus states)
SN65HVD255: No Connect
SN65HVD256: RXD output supply voltage
O
SN65HVD257: open drain FAULT output pin
CANL
6
I/O
Low level CAN bus line
CANH
7
I/O
High level CAN bus line
S
8
I
Mode select: S (silent mode) select pin (active high)
ORDERING INFORMATION (1)
(1)
(2)
2
TA
PACKAGE (2)
–40°C to 125°C
SOIC – D
ORDERABLE PART NUMBER
TOP SIDE MARKING
SN65HVD255D and SN65HVD255DR
HVD255
SN65HVD256D and SN65HVD256DR
HVD256
SN65HVD257D and SN65HVD257DR
HVD257
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
Submit Documentation Feedback
Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Links: SN65HVD255 SN65HVD256 SN65HVD257
SN65HVD255
SN65HVD256, SN65HVD257
www.ti.com
SLLSEA2B – DECEMBER 2011 – REVISED JUNE 2012
FUNCTIONAL DESCRIPTION
OPERATING MODES
The device has two main operating modes: normal mode and silent mode. Operating mode selection is made via
the S input pin.
Table 1. Operating Modes
(1)
S Pin
MODE
DRIVER
RECEIVER
RXD Pin
LOW
Normal Mode
Enabled (ON)
Enabled (ON)
Mirrors Bus State (1)
HIGH
Silent Mode
Disabled (OFF)
Enabled (ON)
Mirrors Bus State
Mirrors bus state: low if CAN bus is dominant, high if CAN bus is recessive.
CAN BUS STATES
The CAN bus has two states during powered operation of the device; dominant and recessive. A dominant bus
state is when the bus is driven differentially, corresponding to a logic low on the TXD and RXD pin. A recessive
bus state is when the bus is biased to VCC / 2 via the high-resistance internal input resistors RIN of the receiver,
corresponding to a logic high on the TXD and RXD pins. See Figure 3 and Figure 4.
Typical Bus Voltage (V)
Normal & Silent Mode
4
CANH
3
Vdiff(D)
2
Vdiff(R)
CANL
1
Recessive
Logic H
Dominant
Logic L
Recessive
Logic H
Time, t
Figure 3. Bus States (Physical Bit Representation)
CANH
VCC/2
RXD
CANL
Figure 4. Simplified Recessive Common Mode Bias and Receiver
NORMAL MODE
Select the normal mode of device operation by setting S low. The CAN driver and receiver are fully operational
and CAN communication is bi-directional. The driver is translating a digital input on TXD to a differential output
on CANH and CANL. The receiver is translating the differential signal from CANH and CANL to a digital output
on RXD.
Copyright © 2011–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: SN65HVD255 SN65HVD256 SN65HVD257
3
SN65HVD255
SN65HVD256, SN65HVD257
SLLSEA2B – DECEMBER 2011 – REVISED JUNE 2012
www.ti.com
SILENT MODE
Activate silent mode (receive only) by setting S high. The CAN driver is turned off while the receiver remains
active and RXD outputs the received bus state.
APPLICATION NOTE: Silent mode may be used to implement babbling idiot protection, to ensure that the
driver does not disrupt the network during a local fault. Silent mode may also be used in redundant systems
to select or de-select the redundant transceiver (driver) when needed.
DRIVER AND RECEIVER FUNCTION TABLES
Table 2. Driver Function Table
DEVICE
All Devices
INPUTS
S (1) (2)
L or Open
H
(1)
(2)
(3)
OUTPUTS
TXD (1) (3)
CANH (1)
CANL (1)
DRIVEN BUS
STATE
L
H
L
Dominant
H or Open
Z
Z
Recessive
X
Z
Z
Recessive
H = high level, L = low level, X= irrelevant, Z = common mode (recessive) bias to VCC / 2. See
Figure 3 and Figure 4 for bus state and common mode bias information.
Devices have an internal pull down to GND on S pin. If S pin is open the pin will be pulled low and the
device will be in normal mode.
Devices have an internal pull up to VCC on TXD pin. If the TXD pin is open the pin will be pulled high
and the transmitter will remain in recessive (non-driven) state.
Table 3. Receiver Function Table
DEVICE MODE
Normal or Silent
(1)
(2)
CAN DIFFERENTIAL INPUTS
VID = VCANH – VCANL
BUS STATE
RXD PIN (1)
VID ≥ 0.9 V
Dominant
L (2)
0.5 V < VID < 0.9 V
?
?
VID ≤ 0.5 V
Recessive
H
Open (VID ≈ 0 V)
Open
H
H = high level, L = low level, ? = indeterminate.
RXD output remains dominant (low) as long as the bus is dominant. On SN65HVD257 device with
RXD dominant timeout, once the bus has been dominant longer than the dominant timeout, tRXD_DTO,
the RXD pin will return recessive (high). See RXD Dominant Timeout (SN65HVD257) for a description
of behavior during receiving a bus stuck dominant condition.
DIGITAL INPUTS AND OUTPUTS
5 V VCC Only Devices (SN65HVD255 and SN65HVD257):
The 5V VCC device is supplied by a single 5 V rail. The digital inputs are 5 V and 3.3 V compatible. This device
has a 5 V (VCC) level RXD output. TXD is internally pulled up to VCC and S is internally pulled down to GND.
APPLICATION NOTE: TXD is internally pulled up to VCC and the S pin is internally pulled down to GND.
However, the internal bias may only put the device into a known state if the pins float. The internal bias may
be inadequate for system-level biasing. TXD pullup strength and CAN bit timing require special consideration
when the SN65HVD25x devices are used with an open-drain TXD output on the CAN controller. An
adequate external pullup resistor must be used to ensure that the CAN controller output of the μP maintains
adequate bit timing input to the SN65HVD25x.
5 V VCC with VRXD RXD output Supply Devices (SN65HVD256):
This device is a 5V VCC CAN transceiver with a separate supply for the RXD output, VRXD. The digital inputs are
5 V and 3.3 V compatible. These devices have a VRXD-level RXD output. TXD remains weakly pulled up to VCC.
APPLICATION NOTE: On device versions with a VRXD supply that shifts the RXD output level, the input pins
of the device remain the same. TXD remains weakly pulled up to VCC internally. Thus, a small IIH current
flows if the TXD input is used below VCC levels.
4
Submit Documentation Feedback
Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Links: SN65HVD255 SN65HVD256 SN65HVD257
SN65HVD255
SN65HVD256, SN65HVD257
www.ti.com
SLLSEA2B – DECEMBER 2011 – REVISED JUNE 2012
5 V VCC with FAULT Open-Drain Output Device (SN65HVD257):
This device has a FAULT output pin (open-drain). FAULT must be pulled up to VCC or I/O supply level via an
external resistor.
APPLICATION NOTE: Because the FAULT output pin is open-drain, it actively pulls down when there is no
fault, and becomes high-impedance when a fault condition is detected. An external pullup resistor to the VCC
or I/O supply of the system must be used to pull the pin high to indicate a fault to the host microprocessor.
The open-drain architecture makes the fault pin compatible with 3.3 V and 5 V I/O-level systems. The pullup
current, selected by the pullup resistance value, should be as low as possible while achieving the desired
voltage level output in the system with margin against noise.
PROTECTION FEATURES
TXD Dominant Timeout (DTO)
During normal mode (the only mode where the CAN driver is active), the TXD DTO circuit prevents the
transceiver from blocking network communication in the event of a hardware or software failure where TXD is
held dominant longer than the timeout period tTXD_DTO. The DTO circuit timer starts on a falling edge on TXD.
The DTO circuit disables the CAN bus driver if no rising edge is seen before the timeout period expires. This
frees the bus for communication between other nodes on the network. The CAN driver is re-activated when a
recessive signal is seen on TXD pin, thus clearing the TXD DTO condition. The receiver and RXD pin still reflect
the CAN bus, and the bus pins are biased to recessive level during a TXD dominant timeout.
APPLICATION NOTE: The minimum dominant TXD time allowed by the TXD DTO circuit limits the minimum
possible transmitted data rate of the device. The CAN protocol allows a maximum of eleven successive
dominant bits (on TXD) for the worst case, where five successive dominant bits are followed immediately by
an error frame. This, along with the tTXD_DTO minimum, limits the minimum data rate. Calculate the minimum
transmitted data rate by: Minimum Data Rate = 11 / tTXD_DTO.
RXD Dominant Timeout (SN65HVD257)
The SN65HVD257 device has a RXD dominant timeout (RXD DTO) circuit that prevents a bus stuck dominant
fault from permanently driving the RXD output dominant (low) when the bus is held dominant longer than the
timeout period tRXD_DTO. The RXD DTO timer starts on a falling edge on RXD (bus going dominant). If no rising
edge (bus returning recessive) is seen before the timeout constant of the circuit expires (tRXD_DTO), the RXD pin
returns high (recessive). The RXD output is re-activated to mirror the bus receiver output when a recessive signal
is seen on the bus, clearing the RXD dominant timeout. The CAN bus pins are biased to the recessive level
during a RXD DTO.
APPLICATION NOTE: The minimum dominant RXD time allowed by the RXD DTO limits the minimum
possible received data rate of the device. The CAN protocol allows a maximum of eleven successive
dominant bits for the worst case transmission, where five successive dominant bits are followed immediately
by an error frame. This, along with the tRXD_DTO minimum, limits the minimum data rate. The minimum
received data rate may be calculated by: Minimum Data Rate = 11 / tRXD_DTO.
Thermal Shutdown
If the junction temperature of the device exceeds the thermal shut down threshold the device turns off the CAN
driver circuits thus blocking the TXD to bus transmission path. The shutdown condition is cleared when the
junction temperature drops below the thermal shutdown temperature of the device.
APPLICATION NOTE: During thermal shutdown the CAN bus drivers turn off; thus no transmission is
possible from TXD to the bus. The CAN bus pins are biased to recessive level during a thermal shutdown,
and the receiver to RXD path remains operational.
Copyright © 2011–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: SN65HVD255 SN65HVD256 SN65HVD257
5
SN65HVD255
SN65HVD256, SN65HVD257
SLLSEA2B – DECEMBER 2011 – REVISED JUNE 2012
www.ti.com
Undervoltage Lockout
The supply pins have undervoltage detection that places the device in protected mode. This protects the bus
during an undervoltage event on either the VCC or VRXD supply pins.
Table 4. Undervoltage Lockout 5V Only Devices (SN65HVD255 and SN65HVD257)
VCC
DEVICE STATE
BUS OUTPUT
RXD
GOOD
Normal
Per Device State and TXD
Mirrors Bus
BAD
Protected
High Impedance
High Impedance (3-state)
Table 5. Undervoltage Lockout 5V and VRXD Device (SN65HVD256)
VCC
VRXD
DEVICE STATE
BUS OUTPUT
RXD
GOOD
GOOD
Normal
Per Device State and TXD
Mirrors Bus
BAD
GOOD
Protected
High Impedance
High (Recessive)
GOOD
BAD
Protected
Recessive
High Impedance (3-state)
BAD
BAD
Protected
High Impedance
High Impedance (3-state)
APPLICATION NOTE: After an undervoltage condition is cleared and the supplies have returned to valid
levels, the device typically resumes normal operation in 300 µs.
FAULT Pin (SN65HVD257)
If one or more of the faults (TXD-Dominant Timeout, RXD dominant Timeout, Thermal Shutdown or
Undervoltage Lockout) occurs, the FAULT pin (open-drain) turns off, resulting in a high level when externally
pulled up to VCC or IO supply.
VCC or VIO
µP
FAULT
Input
FAULT
TXD
DTO
RXD
DTO
Thermal
Shutdown
GND
UV
Lockout
Figure 5. FAULT Pin Function Diagram and Application
6
Submit Documentation Feedback
Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Links: SN65HVD255 SN65HVD256 SN65HVD257
SN65HVD255
SN65HVD256, SN65HVD257
www.ti.com
SLLSEA2B – DECEMBER 2011 – REVISED JUNE 2012
Bus Fault stuck dominant , example CANH
short to supply =5V and CAN L short to GND .
Fault is repaired and normal
communication returns
SN65HVD255
SN65HVD256
CAN
Bus
Signal
SN65HVD257
CAN PHY With RXD
DTO AND FAULT
CAN PHY
CAN BUS
Normal CAN
communication
RXD
(receiver)
RXD will also be “stuck dominant” blocking
alternative communication paths
RXD
(reciever)
t RXD_DTO
RXD output is returned recessive (high)
and FAULT is signaled to μP and link
layer / protocol.
RXD mirrors
bus
FAULT cleared signal
is given
FAULT
Figure 6. Example Timing Diagram for Devices With and Without RXD DTO and FAULT Pin
Unpowered Device
The device is designed to be an 'ideal passive' or 'no load' to the CAN bus if it is unpowered. The bus pins
(CANH, CANL) have extremely low leakage currents when the device is unpowered so they will not load down
the bus. This is critical if some nodes of the network will be unpowered while the rest of the of network remains in
operation. The logic pins also have extremely low leakage currents when the device is unpowered to avoid
loading down other circuits that may remain powered.
Floating Pins
The device has internal pull ups and pull downs on critical pins to place the device into known states if the pins
float. The TXD pin is pulled up to VCC to force a recessive input level if the pin floats. The S pin is pulled down to
GND to force the device into normal mode if the pin floats.
Copyright © 2011–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: SN65HVD255 SN65HVD256 SN65HVD257
7
SN65HVD255
SN65HVD256, SN65HVD257
SLLSEA2B – DECEMBER 2011 – REVISED JUNE 2012
www.ti.com
CAN Bus Short Circuit Current Limiting
The device has several protection features that limit the short circuit current when a CAN bus line is shorted.
These include driver current limiting (dominant and recessive). The device has TXD dominant state time out to
prevent permanent higher short circuit current of the dominant state during a system fault. During CAN
communication the bus switches between dominant and recessive states with the data and control fields bits,
thus the short circuit current may be viewed either as the instantaneous current during each bus state, or as a
DC average current. For system current (power supply) and power considerations in the termination resistors
and common-mode choke ratings, use the average short circuit current. Determine the ratio of dominant and
recessive bits by the data in the CAN frame plus the following factors of the protocol and PHY that force either
recessive or dominant at certain times:
• Control fields with set bits
• Bit stuffing
• Interframe space
• TXD dominant time out (fault case limiting)
These ensure a minimum recessive amount of time on the bus even if the data field contains a high percentage
of dominant bits.
APPLICATION NOTE: The short circuit current of the bus depends on the ratio of recessive to dominant bits
and their respective short circuit currents. The average short circuit current may be calculated with the
following formula:
IOS(AVG) = %Transmit × [(%REC_Bits × IOS(SS)_REC) + (%DOM_Bits × IOS(SS)_DOM)] + [%Receive × IOS(SS)_REC]
Where
• IOS(AVG) is the average short circuit current
• %Transmit is the percentage the node is transmitting CAN messages
• %Receive is the percentage the node is receiving CAN messages
• %REC_Bits is the percentage of recessive bits in the transmitted CAN messages
• %DOM_Bits is the percentage of dominant bits in the transmitted CAN messages
• IOS(SS)_REC is the recessive steady state short circuit current
• IOS(SS)_DOM is the dominant steady state short circuit current
APPLICATION NOTE: Consider the short circuit current and possible fault cases of the network when sizing
the power ratings of the termination resistance and other network components.
8
Submit Documentation Feedback
Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Links: SN65HVD255 SN65HVD256 SN65HVD257
SN65HVD255
SN65HVD256, SN65HVD257
www.ti.com
SLLSEA2B – DECEMBER 2011 – REVISED JUNE 2012
ABSOLUTE MAXIMUM RATINGS (1) (2)
1.0
RATING
UNIT
–0.3 to 6
V
–0.3 to 6 and VRXD ≤ VCC + 0.3
V
CAN Bus I/O voltage range (CANH, CANL)
–27 to 40
V
VLogic_Input
Logic input pin voltage range (TXD, S)
–0.3 to 6
V
VLogic_Output
Logic output pin voltage range (RXD)
SN65HVD255, SN65HVD257
–0.3 to 6
V
1.6
VLogic_Output
Logic output pin voltage range (RXD)
SN65HVD256
–0.3 to 6 and VI ≤ VRXD + 0.3
V
1.7
IO(RXD)
RXD (Receiver) output current
12
mA
1.8
IO(FAULT)
FAULT output current
20
mA
1.9
TJ
Operating virtual junction temperature range (see THERMAL
CHARACTERISTICS)
–40 to 150
°C
1.10
TA
Ambient temperature range (see THERMAL CHARACTERISTICS)
–40 to 125
°C
1.1
VCC
Supply voltage range
1.2
VRXD
RXD Output supply voltage range
1.3
VBUS
1.4
1.5
(1)
(2)
SN65HVD256
SN65HVD257
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to ground terminal.
TRANSIENT AND ELECTROSTATIC DISCHARGE PROTECTION
2.0
TEST CONDITIONS
RATING
All pins (1)
±2.5
CAN bus pins (CANH, CANL) (2)
±12
UNIT
2.1
Human-Body Model
kV
2.2
Charged-Device Model
All pins (3)
±750
V
2.3
Machine Model
All pins (4)
±250
V
2.4
IEC 61400-4-2 according to GIFT-ICT CAN EMC test
CAN bus pins (CANH, CANL) to GND
spec (5)
±8
kV
2.5
Pulse 1
–100
V
2.6
Pulse 2
+75
V
Pulse 3a
–150
V
Pulse 3b
+100
V
ISO7637 Transients according to GIFT - ICT CAN
EMC test spec (6)
2.7
CAN bus pins
(CANH, CANL)
2.8
(1)
(2)
(3)
(4)
(5)
(6)
Tested in accordance to JEDEC Standard 22, Test Method A114.
Test method based upon JEDEC Standard 22 Test Method A114, CAN bus pins stressed with respect to GND.
Tested in accordance to JEDEC Standard 22, Test Method C101.
Tested in accordance to JEDEC Standard 22, Test Method A115.
IEC 61000-4-2 is a system level ESD test. Results given here are specific to the GIFT-ICT CAN EMC Test specification conditions.
Different system level configurations may lead to different results.
ISO7637 is a system level transient test. Results given here are specific to the GIFT-ICT CAN EMC Test specification conditions.
Different system level configurations may lead to different results.
RECOMMENDED OPERATING CONDITIONS
3.0
MIN
MAX
3.1
VCC
Supply voltage
4.5
5.5
3.2
VRXD
RXD supply (SN65HVD256 only)
2.8
5.5
3.3
VI or VIC
CAN bus terminal voltage (separately or common mode)
–2
7
3.4
VID
CAN bus differential voltage
-6
6
3.5
VIH
Logic HIGH level input (TXD, S)
2
5.5
3.6
VIL
Logic LOW level input (TXD, S)
0
0.8
3.7
IOH(DRVR)
CAN BUS Driver High level output current
3.8
IOL(DRVR)
CAN BUS Driver Low level output current
3.9
IOH(RXD)
RXD pin HIGH level output current
3.10
IOL(RXD)
RXD pin LOW level output current
3.11
IO(FAULT)
FAULT pin LOW level output current
3.12
TA
Operational free-air temperature (see THERMAL CHARACTERISTICS)
Copyright © 2011–2012, Texas Instruments Incorporated
UNIT
V
–70
70
–2
mA
2
SN65HVD257
2
–40
125
Submit Documentation Feedback
Product Folder Links: SN65HVD255 SN65HVD256 SN65HVD257
°C
9
SN65HVD255
SN65HVD256, SN65HVD257
SLLSEA2B – DECEMBER 2011 – REVISED JUNE 2012
www.ti.com
ELECTRICAL CHARACTERISTICS
Over recommended operating conditions, TA = –40°C to 125°C (unless otherwise noted). SN65HVD256 device VRXD = VCC.
PARAMETER
4.0
TEST CONDITIONS / COMMENT
MIN
TYP (1)
SUPPLY CHARACTERISTICS
4.1
Normal Mode
(Driving Dominant)
See Figure 9, TXD = 0 V, RL = 50 Ω,
CL = open, RCM = open, S = 0V
4.2
Normal Mode
(Driving
Dominant – bus
fault)
See Figure 9, TXD = 0 V, S = 0V,
CANH = -12V, RL = open, CL =
open, RCM = open
Normal Mode
(Driving Dominant)
4.4
4.5
4.3
ICC
5-V Supply current
60
85
130
180
See Figure 9, TXD = 0 V, RL = open
(no load), CL = open, RCM = open,
S = 0V
10
20
Normal Mode
(Recessive)
See Figure 9, TXD = VCC, RL = 50
Ω, CL = open, RCM = open,
S = 0V
10
20
Silent Mode
See Figure 9, TXD = VCC, RL = 50
Ω,CL = open, RCM = open,
S = VCC
2.5
5
All modes
RXD Floating, TXD = 0V
4.6
IRXD
RXD Supply
current
(SN65HVD256
only)
4.7
UVVCC
Undervoltage detection on VCC for
protected mode
4.8
VHYS(UVVCC)
Hysteresis voltage on UVVCC
4.9
UVRXD
Undervoltage detection on VRXD for
protected mode (SN65HVD256 only)
4.10
VHYS(UVRXD)
Hysteresis voltage on UVRXD
(SN65HVD256 only)
5.0
S PIN (MODE SELECT INPUT)
5.1
VIH
HIGH-level input voltage
5.2
VIL
LOW-level input voltage
5.3
IIH
HIGH-level input leakage current
S = VCC = 5.5 V
5.4
IIL
Low-level input leakage current
S = 0 V, VCC = 5.5 V
5.5
ILKG(OFF)
Unpowered leakage current
S = 5.5 V, VCC = 0 V, VRXD = 0 V
6.0
TXD PIN (CAN TRANSMIT DATA INPUT)
6.1
VIH
HIGH level input voltage
6.2
VIL
LOW level input voltage
6.3
IIH
HIGH level input leakage current
TXD = VCC = 5.5 V
–2.5
6.4
IIL
Low level input leakage current
TXD = 0 V, VCC = 5.5 V
–100
6.5
ILKG(OFF)
Unpowered leakage current
TXD = 5.5 V, VCC = 0 V, VRXD = 0 V
–1
0
6.6
CI
Input Capacitance
7.0
RXD Pin (CAN RECEIVE DATA OUTPUT)
7.1
VOH
HIGH level output voltage
See Figure 10, IO = –2 mA. For
devices with VRXD supply VOH = 0.8
× VRXD
7.2
VOL
LOW level output voltage
See Figure 10, IO = 2 mA
7.3
ILKG(OFF)
Unpowered leakage current
RXD = 5.5 V, VCC = 0 V, VRXD = 0 V
7.4
tR
Output signal rise time
See Receiver Rise Time
7.5
tF
Output signal fall time
See Receiver Fall Time
(1)
10
MAX UNIT
3.5
500
µA
4.45
V
200
1.3
mA
mV
2.75
80
V
mV
2
V
7
0.8
V
100
µA
–1
0
1
µA
7
35
100
µA
2
V
0.8
V
0
1
µA
-25
–7
µA
1
µA
3.5
pF
0.8×VCC
–1
V
0
0.4
V
1
µA
All typical values are at 25°C and supply voltages of VCC = 5 V and VRXD = 5 V, RL = 60 Ω.
Submit Documentation Feedback
Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Links: SN65HVD255 SN65HVD256 SN65HVD257
SN65HVD255
SN65HVD256, SN65HVD257
www.ti.com
SLLSEA2B – DECEMBER 2011 – REVISED JUNE 2012
ELECTRICAL CHARACTERISTICS (continued)
Over recommended operating conditions, TA = –40°C to 125°C (unless otherwise noted). SN65HVD256 device VRXD = VCC.
PARAMETER
TEST CONDITIONS / COMMENT
8.0
DEVICE SWITCHING CHARACTERISTICS
8.1
Total loop delay, driver input (TXD) to
tPROP(LOOP1) receiver output (RXD), recessive to
dominant
tPROP(LOOP2)
8.3
IMODE
Mode change time, from Normal to Silent
See Figure 11
or from Silent to Normal
9.0
DRIVER ELECTRICAL CHARACTERISTICS
9.2
CANH
Bus output voltage
(dominant
VO(R)
Bus output voltage (recessive)
CANL
MAX UNIT
150
8.2
VO(D)
TYP (1)
See Figure 12, S = 0 V, RL = 60 Ω,
CL = 100 pF, CL_RXD = 15 pF
Total loop delay, driver input (TXD) to
receiver output (RXD), dominant to
recessive
9.1
MIN
ns
150
20
See Figure 3 and Figure 9, TXD = 0
V, S = 0 V, RL = 60 Ω, CL = open,
RCM = open
2.75
4.5
0.5
2.25
See Figure 3 and Figure 9, TXD =
VCC, VRXD = VCC, S = VCC or 0 V (2),
RL = open (no load), RCM = open
2
See Figure 3 and Figure 9, TXD = 0
V, S = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL =
open, RCM = 330 Ω, –2 V ≤ VCM ≤ 7
V, 4.75 V≤ VCC ≤ 5.25 V
1.5
9.5
See Figure 3 and Figure 9, TXD = 0
V, S = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL =
open, RCM = 330 Ω, –2 V ≤ VCM ≤ 7
V, 4.5V ≤ VCC ≤ 5.5 V
1.25
3.2
9.6
See Figure 3 and Figure 9, TXD =
VCC, S = 0 V, RL = 60 Ω, CL = open,
RCM = open
–0.12
0.012
9.3
9.4
VOD(D)
VOD(R)
Differential output voltage (dominant)
Differential output voltage (recessive)
9.7
9.8
VSYM
Output symmetry (dominant or
recessive)
(VCC – VO(CANH) – VO(CANL))
IOS(SS)_DOM
short circuit steady-state output current,
Dominant
9.9
9.10
0.5×VCC
3
V
V
V
–0.100
0.050
See Figure 3 and Figure 9, S at 0 V,
RL = 60 Ω, CL = open, RCM = open
–0.4
0.4
See Figure 3 and Figure 14, VCANH
= 0 V, CANL = open, TXD = 0 V
–160
V
mA
See Figure 3 and Figure 14, VCANL =
32 V, CANH = open, TXD = 0 V
160
9.11
IOS(SS)_REC
short circuit steady-state output current,
Recessive
See Figure 3 and Figure 14, –20 V ≤
VBUS ≤ 32 V, Where VBUS = CANH =
CANL, TXD = VCC, Normal and
Silent Modes
9.12
CO
Output capacitance
See receiver input capacitance
10.0
DRIVER SWITCHING CHARACTERISTICS
10.1
tpHR
Propagation delay time, HIGH TXD to
Driver Recessive
10.2
tpLD
Propagation delay time, LOW TXD to
Driver Dominant
10.3
tsk(p)
Pulse skew (|tpHR - tpLD|)
10.4
tR
Differential output signal rise time
10
30
10.5
tF
Differential output signal fall time
17
30
(2)
V
3
See Figure 3 and Figure 9, TXD =
VCC, S = 0 V, RL = open (no load),
CL = open, RCM = open, –40°C ≤ TA
≤ 85°C
See Figure 9, S = 0 V, RL = 60 Ω,
CL = 100 pF, RCM = open
µS
–8
8
50
70
40
70
mA
ns
10
For the bus output voltage (recessive) will be the same if the device is in normal mode with S pin LOW or if the device is in silent mode
with the S pin is HIGH.
Copyright © 2011–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: SN65HVD255 SN65HVD256 SN65HVD257
11
SN65HVD255
SN65HVD256, SN65HVD257
SLLSEA2B – DECEMBER 2011 – REVISED JUNE 2012
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
Over recommended operating conditions, TA = –40°C to 125°C (unless otherwise noted). SN65HVD256 device VRXD = VCC.
PARAMETER
TEST CONDITIONS / COMMENT
MIN
TYP (1)
MAX UNIT
10.6
tR(10k)
Differential output signal rise time,
RL = 10 kΩ
10.7
tF(10k)
Differential output signal fall time,
RL = 10 kΩ
10.8
tTXD_DTO
Dominant timeout (3)
11.0
RECEIVER ELECTRICAL CHARACTERISTICS
11.1
VIT+
Positive-going input threshold voltage,
normal mode
11.2
VIT–
Negative-going input threshold voltage,
normal mode
11.3
VHYS
Hysteresis voltage (VIT+ - VIT–)
11.4
IIOFF(LKG)
Power-off (unpowered) bus input
leakage current
CANH = CANL = 5 V, VCC = 0 V,
VRXD = 0 V
11.5
CI
Input capacitance to ground (CANH or
CANL)
TXD = VCC, VRXD = VCC, VI = 0.4 sin
(4E6 π t) + 2.5 V
25
pF
11.6
CID
Differential input capacitance
TXD = VCC, VRXD = VCC, VI = 0.4 sin
(4E6 π t)
10
pF
11.7
RID
Differential input resistance
11.8
RIN
Input resistance (CANH or CANL)
11.9
RIN(M)
Input resistance matching:
[1 – RIN(CANH) / RIN(CANL)] × 100%
12.0
RECEIVER SWITCHING CHARACTERISTICS
12.1
tpHR
Propagation delay time, recessive input
to high output
12.2
tPDL
Propagation delay time, dominant input
to low output
12.3
tR
12.4
35
See Figure 9, S = 0 V, RL = 10 kΩ,
CL = 10 pF, RCM = open
See Figure 13, RL = 60 Ω, CL =
open
ns
100
1175
See Figure 10 and Table 3.
3700
µs
900
mV
500
mV
125
TXD = VCC = VRXD = 5 V, S = 0 V
V(CANH) = V(CANL), –40°C ≤ TA ≤
85°C
mV
5.5
µA
30
80
kΩ
15
40
kΩ
–3%
3%
70
90
ns
70
90
ns
Output signal rise time
4
20
ns
tF
Output signal fall time
4
20
ns
12.5
tRXD_DTO (4)
Receiver dominant time out
(SN65HVD257 only) See Figure 7,
CL_RXD = 15 pF
4200
µs
13.0
FAULT Pin (Fault Output), SN65HVD257 only
13.1
ICH
Output current high level
FAULT = VCC, See Figure 8
13.2
ICL
Output current low level
FAULT = 0.4 V, See Figure 8
(3)
(4)
12
See Figure 10, CL_RXD = 15 pF
1380
–10
5
10
12
µA
mA
The TXD dominant timeout (tTXD_DTO) disables the driver of the transceiver once the TXD has been dominant longer than tTXD_DTO,
which releases the bus lines to recessive, preventing a local failure from locking the bus dominant. The driver may only transmit
dominant again after TXD has been returned HIGH (recessive). While this protects the bus from local faults, locking the bus dominant, it
limits the minimum data rate possible. The CAN protocol allows a maximum of eleven successive dominant bits (on TXD) for the worst
case, where five successive dominant bits are followed immediately by an error frame. This, along with the tTXD_DTO minimum, limits the
minimum bit rate. The minimum bit rate may be calculated by: Minimum Bit Rate = 11 / tTXD_DTO = 11 bits / 1175 µs = 9.4 kbps.
The RXD timeout (tRXD_DTO) disables the driver of the transceiver once the RXD has been dominant longer than tRXD_DTO, which
releases the bus lines to recessive, preventing a local failure from locking the bus dominant. The driver may only transmit dominant
again after RXD has been returned HIGH (recessive). While this protects the bus from local faults, locking the bus dominant, it limits the
minimum data rate possible. The CAN protocol allows a maximum of eleven successive dominant bits (on RXD) for the worst case,
where five successive dominant bits are followed immediately by an error frame. This, along with the tRXD_DTO minimum, limits the
minimum bit rate. The minimum bit rate may be calculated by: Minimum Bit Rate = 11 / tRXD_DTO = 11 bits / 1380 µs = 8 kbps.
Submit Documentation Feedback
Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Links: SN65HVD255 SN65HVD256 SN65HVD257
SN65HVD255
SN65HVD256, SN65HVD257
www.ti.com
SLLSEA2B – DECEMBER 2011 – REVISED JUNE 2012
THERMAL CHARACTERISTICS
THERMAL METRIC (1)
13.0
TEST CONDITIONS
High-K thermal resistance (2)
13.1
θJA
Junction-to-air thermal resistance
13.2
θJB
Junction-to-board thermal resistance (3)
13.3
θJC(TOP)
Junction-to-case (top) thermal resistance (4)
ΨJT
Junction-to-top characterization parameter
ΨJB
Junction-to-board characterization parameter (6)
Average power dissipation
13.7
13.8
Thermal shutdown temperature
13.9
Thermal shutdown hysteresis
(1)
(2)
(3)
(4)
(5)
(6)
56.7
(5)
13.5
PD
UNIT
48.9
13.4
13.6
TYP
107.5
°C/W
12.1
48.2
VCC = 5 V, VRXD = 5 V, TJ = 27°C, RL = 60 Ω, S at
0 V, Input to TXD at 250 kHz, 25% duty cycle
square wave, CL_RXD = 15 pF. Typical CAN
operating conditions at 500kbps with 25%
transmission (dominant) rate.
115
VCC = 5.5 V, VRXD = 5.5 V, TJ = 150°C, RL = 50 Ω,
S at 0 V, Input to TXD at 500 kHz, 50% duty cycle
square wave, CL_RXD = 15 pF. Typical high load
CAN operating conditions at 1mbps with 50%
transmission (dominant) rate and loaded network.
268
mW
170
°C
5
°C
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
he junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-top characterization parameter, ΨJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ΨJB estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
Copyright © 2011–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: SN65HVD255 SN65HVD256 SN65HVD257
13
SN65HVD255
SN65HVD256, SN65HVD257
SLLSEA2B – DECEMBER 2011 – REVISED JUNE 2012
www.ti.com
PARAMETER MEASUREMENT INFORMATION
VID(D)
CANH
VID
RXD
0.9V
0.5V
0V
VID
CL_RXD
CANL
VO
VOH
RXD
50%
0V
t RXD_DTO
Figure 7. RXD Dominant Timeout Test Circuit and Measurement
IFAULT
TXD
DTO
FAULT
RXD
DTO
+
-
Thermal
Shutdown
UV
Lockout
GND
Figure 8. FAULT Test and Measurement
RCM
CANH
TXD
VCC
TXD
RL
CL
VOD
VO(CANL)
50%
0V
VCM
VO(CANH)
CANL
50%
tpHR
tpLD
90%
RCM
VOD
0.9 V
0.5 V
10%
tR
tF
Figure 9. Driver Test Circuit and Measurement
14
Submit Documentation Feedback
Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Links: SN65HVD255 SN65HVD256 SN65HVD257
SN65HVD255
SN65HVD256, SN65HVD257
www.ti.com
SLLSEA2B – DECEMBER 2011 – REVISED JUNE 2012
PARAMETER MEASUREMENT INFORMATION (continued)
CANH
1 .5 V
RXD
0 .9 V
IO
V ID
0 .5 V
0V
VID
CL_RXD
CANL
t pDL
t pRH
VO
V OH
90 %
V O(RXD)
50 %
10 %
V OL
tF
tR
Figure 10. Receiver Test Circuit and Measurement
CANH
0V
VCC
TXD
RL
CL
S
50%
CANL
VI
S
0V
tMODE
RXD
VO
VOH
CL_RXD
RXD
50%
VOL
Figure 11. tMODE Test Circuit and Measurement
Copyright © 2011–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: SN65HVD255 SN65HVD256 SN65HVD257
15
SN65HVD255
SN65HVD256, SN65HVD257
SLLSEA2B – DECEMBER 2011 – REVISED JUNE 2012
www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
CANH
VCC
TXD
RL
VI
CL
50%
TXD
0V
CANL
S
0V
tPROP(LOOP1)
RXD
VO
tPROP(LOOP2)
VOH
CL_RXD
50%
RXD
VOL
Figure 12. TPROP(LOOP) Test Circuit and Measurement
CANH
TXD
VIH
TXD
RL
CL
0V
VOD
VOD(D)
CANL
0.9 V
VOD
0.5 V
0V
tTXD_DTO
Figure 13. TXD Dominant Timeout Test Circuit and Measurement
CANH
IOS
200 ms
TXD
IOS
CANL
VBUS
VBUS
VBUS
0V
or
0V
VBUS
VBUS
Figure 14. Driver Short Circuit Current Test and Measurement
16
Submit Documentation Feedback
Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Links: SN65HVD255 SN65HVD256 SN65HVD257
SN65HVD255
SN65HVD256, SN65HVD257
www.ti.com
SLLSEA2B – DECEMBER 2011 – REVISED JUNE 2012
APPLICATION INFORMATION
VIN
VIN
VOUT
5-V Voltage
Regulator
(e.g.TPSxxxx)
VCC
VCC
3
Port x
S
7
CANH
8
SN65HVD255
5-V MCU
CAN Transceiver
RXD
TXD
RXD
TXD
4
1
5
6
2
CANL
GND
NC
Figure 15. Typical 5V Application
VIN
VIN
VOUT
5-V Voltage
Regulator
(e.g. TPSxxxx)
VCC
VCC
3
Port x
S
SN65HVD256
CAN Transceiver
VOUT
RXD
3-V Voltage
Regulator
(e.g. TPSxxxx)
CANH
8
3-V MCU
VIN
7
TXD
RXD
TXD
4
1
5
VRXD
6
2
CANL
GND
Figure 16. Typical 3.3V Application
Copyright © 2011–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: SN65HVD255 SN65HVD256 SN65HVD257
17
SN65HVD255
SN65HVD256, SN65HVD257
SLLSEA2B – DECEMBER 2011 – REVISED JUNE 2012
www.ti.com
CAN TERMINATION
The CAN bus uses twisted pair cabling of 120 Ω characteristic impedance in a bus topology. The bus requires
proper termination at both ends with 120 Ω resistors that match this impedance to avoid signal reflections. If
nodes may be removed from the bus, the termination must be carefully placed so that it is not removed from the
bus.
Node n
(with termination)
Node 1
Node 2
Node 3
MCU or DSP
MCU or DSP
MCU or DSP
CAN
Controller
CAN
Controller
CAN
Controller
CAN
Transceiver
CAN
Transceiver
CAN
Transceiver
MCU or DSP
CAN
Controller
CAN
Transceiver
RTERM
RTERM
Figure 17. Typical CAN Bus
Termination may be a single 120 Ω resistor at the end of the bus, either on the cable or in a terminating node. If
filtering and stabilization of the common mode voltage of the bus is desired, then split termination may be used.
(See Figure 18). Split termination improves the electromagnetic emissions behavior of the network by eliminating
fluctuations in the bus common-mode voltages at the start and end of message transmissions.
Standard Termination
CANH
Split Termination
CANH
RTERM/2
CAN
CAN
Transceiver
RTERM
Transceiver
CSPLIT
RTERM/2
CANL
CANL
Figure 18. CAN Bus Termination Concepts
18
Submit Documentation Feedback
Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Links: SN65HVD255 SN65HVD256 SN65HVD257
SN65HVD255
SN65HVD256, SN65HVD257
www.ti.com
SLLSEA2B – DECEMBER 2011 – REVISED JUNE 2012
Example: Functional Safety Using the SN65HVD257 in a Redundant Physical Layer CAN
Network Topology
CAN is a standard linear bus topology using 120 Ω twisted pair cabling. The SN65HVD257 CAN device includes
several features to use the CAN physical layer in nonstandard topologies with only one CAN link layer controller
(μP) interface. This allows much greater flexibility in the physical topology of the bus while reducing the digital
controller and software costs. The combination of RXD DTO and the FAULT output allows great flexibility, control
and monitoring of these applications.
A simple example of this flexibility is to use two SN65HVD257 devices in parallel with an AND gate to achieve
redundancy (parallel) of the physical layer (cabling & PHYs) in a CAN network.
For the CAN bit-wise arbitration to work, the RXD outputs of the transceivers must connect via AND gate logic so
that a dominant bit (low) from any of the branches is received by the link layer logic (μP), and appears to the link
layer and above as a single physical network. The RXD DTO feature prevents a bus stuck dominant fault in a
single branch from taking down the entire network by forcing the RXD pin for the transceivers on the branch with
the fault back to the recessive after the tRXD_DTO time. The remaining branch of the network continues to function.
The FAULT pin of the transceivers on the branch with the fault indicates this via the FAULT output to their host
processors, which diagnose the failure condition. The S pin (silent mode pin) may be used to put a branch in
silent mode to check each branch for other faults. Thus it is possible to implement a robust and redundant CAN
network topology in a very simple and low cost manner.
These concepts can be expanded into more complicated & flexible CAN network topologies to solve various
system level challenges with a networked infrastructure.
μP
μP
SN65HVD 257
A1
~~
~
~
SN65HVD 257
B1
RX D_A
RXD_B
SN65HVD 257
A2
RX D
TXD
S_A
FAULT_ A
S_B
RX D_A
RXD_B
SN65HVD 257
B2
FAULT_ B
RX D
SN65HVD 257
A3
TXD
S_A
FAULT_ A
S_B
SN65 HVD 257
B3
RX D_A
RXD_B
RXD_A
RXD_B
SN65 HVD257
An
FAULT_ B
RX D
TXD
S_A
FAULT_ A
S_B
FAULT_ B
RXD
TXD
S_A
FAULT_A
S_B
FAULT_B
SN65HVD 257
Bn
μP
μP
A.
CAN nodes with termination are PHY A, PHY B, PHY An and PHY Bn.
B.
RXD DTO prevents a single branch-stuck-dominant condition from blocking the redundant branch via the AND logic
on RXD. The transceivers signal a received bus stuck dominant fault via the FAULT pin. The system detects which
branch is stuck dominant, and issues a system warning. Other network faults on a single branch that appear as
recessive (not blocking the redundant network) may be detected through diagnostic routines, and using the Silent
Mode of the PHYs to use only one branch at a time for transmission during diagnostic mode. This combination allows
robust fault detection and recovery within single branches so that they may be repaired and again provide
redundancy of the physical layer.
Figure 19. Typical Redundant Physical Layer Topology Using the SN65HVD257
Copyright © 2011–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: SN65HVD255 SN65HVD256 SN65HVD257
19
PACKAGE OPTION ADDENDUM
www.ti.com
11-Jul-2012
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
SN65HVD255D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN65HVD255DR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN65HVD256D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN65HVD256DR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN65HVD257D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN65HVD257DR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
(3)
Samples
(Requires Login)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Jul-2012
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN65HVD255DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
SN65HVD256DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
SN65HVD257DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN65HVD255DR
SOIC
D
8
2500
340.5
338.1
20.6
SN65HVD256DR
SOIC
D
8
2500
340.5
338.1
20.6
SN65HVD257DR
SOIC
D
8
2500
340.5
338.1
20.6
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which
have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such
components to meet such requirements.
Products
Applications
Audio
www.ti.com/audio
Automotive and Transportation
www.ti.com/automotive
Amplifiers
amplifier.ti.com
Communications and Telecom
www.ti.com/communications
Data Converters
dataconverter.ti.com
Computers and Peripherals
www.ti.com/computers
DLP® Products
www.dlp.com
Consumer Electronics
www.ti.com/consumer-apps
DSP
dsp.ti.com
Energy and Lighting
www.ti.com/energy
Clocks and Timers
www.ti.com/clocks
Industrial
www.ti.com/industrial
Interface
interface.ti.com
Medical
www.ti.com/medical
Logic
logic.ti.com
Security
www.ti.com/security
Power Mgmt
power.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Microcontrollers
microcontroller.ti.com
Video and Imaging
www.ti.com/video
RFID
www.ti-rfid.com
OMAP Applications Processors
www.ti.com/omap
TI E2E Community
e2e.ti.com
Wireless Connectivity
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2012, Texas Instruments Incorporated