SN74SSTE32882 www.ti.com SCAS840 – NOVEMBER 2006 28-Bit to 56-Bit Registered Buffer With Address Parity Test and One Pair to Four Pair Differential Clock PLL Driver • FEATURES • • • • • Pinout Optimizes DDR3 DIMM PCB Layout 1-to-2 Register Outputs and 1-to-4 Clock Pair Outputs Support Stacked DDR3 DIMMs Chip-Select Inputs Gate the Data Outputs from Changing State and Minimizes System Power Consumption Supports SSTL_15 Data Inputs Checks Parity on Command and Address (CS-gated) Data Inputs • • 1.5-V Phase Lock Loop Clock Driver for Buffering One Differential Clock Pair (CK and CK) and Distributing to Four Differential Outputs Supports LVCMOS Levels on RESET Input RESET Input Disables Differential Input Receivers, Resets All Registers, and Forces All Outputs Low, Except QERR APPLICATIONS • DDR3 RDIMM This 28-bit 1:2 configurable registered buffer is designed for 1.425-V to 1.575-V VCC operation. One device per DIMM is required to drive up to 36 SDRAM loads (maximum 2 Ranks × 4). The SN74SSTE32882 includes a high-performance, low-jitter, low-skew PLL based clock buffer that distributes a differential input clock signal (CK and CK) to four differential pairs of clock outputs (QCKn and QCKn) and to one differential pair of feedback clock outputs (FBOUT and FBOUT). The clock outputs are controlled by the input clocks (CK and CK), the feedback clocks (FBIN and FBIN) and the analog power inputs (AVDD and AVSS). The SN74SSTE32882 is able to track spread spectrum clocking (SSC) for reduced EMI. All device inputs are SSTL_15, except reset (RESET), which is LVCMOS. All outputs are edge-controlled circuits optimized for terminated DIMM loads, and meet SSTL_15 specifications at the DRAM inputs, except the open-drain error (QERR) output. The clock outputs (Yn, Yn) and control outputs (QACSn, QBCSn, QACKEn, QBCKEn, QAODTn and QBODTn) are designed with different drive strengths, from the other data Qn outputs, to adapt to different loading conditions. The SN74SSTE32882 operates from the differential clock (CK and CK). Data are registered at the crossing of CK going high and CK going low. The SN74SSTE32882 accepts a parity bit from the memory controller on the parity bit (PAR_IN) input and compares it with the data received on the DCSn gated D-inputs (DA0..DA15, DBA0..DBA2, DRAS, DCAS, DWE) during the previous clock cycle. The convention is even parity, i.e., valid parity is defined as an even number of ones across the DCSn gated D-inputs combined with the parity input bit. For correct operation, all DCSn gated D-inputs must be tied to corresponding outputs of the memory controller used for parity generation. Parity errors are flagged on the open-drain QERR pin (active low). ORDERING INFORMATION TX TBD (1) PACKAGE (1) XXXX –ZAL Tape and reel ORDERABLE PART NUMBER TOP-SIDE MARKING SN74SSTE32882ZALR Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. Copyright © 2006, Texas Instruments Incorporated PRODUCT PREVIEW DESCRIPTION SN74SSTE32882 www.ti.com SCAS840 – NOVEMBER 2006 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ZAL PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 TERMINAL ASSIGNMENT FOR DEVICE 8 9 10 11 1 2 3 4 5 6 7 8 9 10 11 A QA A13 QA A8 RSVD GND RESET RSVD QERR GND RSVD QB A8 QB A13 QB A7 QB A14 B QA A14 QA A7 A C QA A9 QA A6 V DD V DD V DD V DD V DD QB A6 QB A9 B D QA A11 QA A5 GND GND GND GND GND QB A5 QBA11 E QA A2 QA A4 V DD V DD V DD V DD V DD QB A4 QB A2 F QA A1 QA A3 GND GND GND GND GND QB A3 QB A1 D G QA A0 QA BA1 V DD V DD V DD V DD V DD QB BA1 QB A0 E H QA A12 QA BA0 GND GND GND GND GND QB BA0 QB A12 J QA BA2 QACS1 V DD V DD V DD V DD V DD QBCS1 QB BA2 K QA A15 QACKE0 GND GND GND GND GND QBCKE0 QB A15 C F G L QA WE QA CS0 H M QA A10 QACKE1 N QA CAS QAODT0 V DD V DD P QA RAS QAODT1 D8 (A3) GND GND R DCKE1 D A14 D9 (A 15) D A5 RSVD D A2 T DCKE0 DCS0 U D A12 D BA2 Y1 PV SS V DD PV DD V D A9 D A11 Y1 PV SS GND PV DD N W D A8 D A6 FBIN Y3 AV SS CK RSVD Y2 FBOUT D A0 D BA0 P Y D A7 RSVD FBIN Y3 AV DD CK Y2 FBOUT PAR_IN D BA1 J PRODUCT PREVIEW K L V DD V DD V DD V DD V DD QBCS0 QB WE GND GND GND GND GND QBCKE1 QB A10 V DD V DD QB ODT0 QB CAS GND D A4 QB ODT1 QB RAS D A1 D A10 DODT1 DCS1 DODT 0 Y0 D A13 D CAS Y0 D RAS D WE ) V DD M R (1) Each pin name in parentheses indicates the DDR3 DIMM signal name. (2) Balls A3, A9, R6, W7 and Y2 are reserved for future functions, and must not be connected on the system. However, a ball on the device and connecting pad on the module are required in those locations. (3) Ball A6 is reserved for future function. The device needs to tolerate floating on this pin. T U V W Y V REF TERMINAL FUNCTIONS TERMINAL NAME ELECTRICAL TYPE Analog ground (PLL) Analog ground input AVDD Analog power (PLL) 1.5 V nominal PVSS Logic and output ground (PLL) Ground input PVDD Logic and output power (PLL) 1.5 V nominal GND Ground (register) Ground input VDD Power supply voltage (register) 1.5 V nominal VREF Input reference voltage VDD/2 (0.75 V) nominal Positive master clock input with a (10 kΩ to 100 kΩ) pull-down resistor Differential input Complementary master clock input with a (10 kΩ to 100 kΩ) pull-down resistor Differential input Positive feedback clock input with a (10 kΩ to 100 kΩ) pull-down resistor Differential input Complementary feedback clock input with a (10 kΩ to 100 kΩ) pull-down resistor Differential input Asynchronous reset input – Resets registers and disables VREF, data and clock differential-input receivers. When RESET is low, all the Q outputs are inactive with QCKEx being forced low and the QERR outputs are forced high. LVCMOS input CK FBIN RESET 2 DESCRIPTION AVSS Submit Documentation Feedback SN74SSTE32882 www.ti.com SCAS840 – NOVEMBER 2006 TERMINAL FUNCTIONS (continued) DESCRIPTION ELECTRICAL TYPE D0–D21 Chip-select gated D-inputs. Data inputs – Clocked in on the crossing of the rising edge of CK and the falling edge of CK. Re-driven only when either DCS0 or DCS1 is low. SSTL_15 inputs DCS0, DCS1 Chip select inputs – These pins initiate DRAM address/command decodes, and as such at least one will be low when a valid address/command is present. The register can be programmed to redrive all D-inputs only when at least one chip select input is low. If DCS0 and DCS1 inputs are high, D-inputs will be ignored with the Q outputs being floating or help at previous state. SSTL_15 inputs DOTD0, DODT1 Ungated inputs – The corresponding outputs of these register bit inputs will not be suspended by the DCS0 and DCS1 control unless a CMR access occurs. SSTL_15 inputs DCKE0, DCKE1 Ungated inputs – The corresponding outputs of these register bit inputs will not be suspended by the DCS0 and DCS1 control unless a CMR access occurs. SSTL_15 inputs PAR_IN Parity input – Arrives one clock cycle after the corresponding data input. SSTL_15 inputs YB0, YA0, YB1, YA1 Positive clock outputs 1.5 V CMOS output YB0, YA0, YB1, YA1 Complementary clock outputs 1.5 V CMOS output Positive feedback clock output 1.5 V CMOS output Complementary feedback clock output 1.5 V CMOS output Q0A–Q21A, Q0B–Q21B Data outputs corresponding to inputs D0 .. D21 1.5 V CMOS output QCS0A, QCS0B, QCS1A, QCS1B Data outputs corresponding to inputs DCS0 and DCS1 1.5 V CMOS output QOTD0A, QODT0B, QOTD1A, QODT1B Data outputs corresponding to inputs DODT0 and DODT1 1.5 V CMOS output QCKE0A, QCKE0B, QCKE1A, QCKE1B Data outputs corresponding to inputs DCKE0 and DCKE1 1.5 V CMOS output QERR Output error – Generated three clock cycles after the corresponding data is registered. Open-drain output FBOUT Submit Documentation Feedback PRODUCT PREVIEW TERMINAL NAME 3 SN74SSTE32882 www.ti.com SCAS840 – NOVEMBER 2006 REGISTER LOGIC DIAGRAM (POSITIVE LOGIC) Vref DA0. .DA9, DA11, DA13. . DA15, DBA0. . DBA2 QxA0. . QxA9, QxA11, Q Q 0 R CE 1 3 DA0 . . DA2, DBA2 Qxa13. . QxA15, QxBA0. . QxBA2 Address Inversion 4 B-Enable Control Word State Machine and A-Enable Y0. . Y3 Enable Control Logic DA3 . . DA4, DBA0, DBA1 DA10. .DA12, DRAS, DCAS, DWE QxA10, QxA12, QxRAS, QxCAS, QxWE Q Q R DCS0 CMR Address CE PreLaunch 4 Q Q 180 ps delay R PRODUCT PREVIEW DCS 0 1 QxCS0 0 1 QxCS1 Q Q 180 ps delay R DCKE0, DCKE1 Q Q 180 ps delay R DODT0, DODT1 0 1 QxCKE0, QxCKE1, 0 1 QxODT0, QxODT1 Q Q 180 ps delay R RESET Y0 Y0 CK CK 10 kW Y1 100 kW PLL Y1 Y2 Y2 FBIN FBIN Y3 Y3 FBOUT FBOUT 4 Submit Documentation Feedback SN74SSTE32882 www.ti.com SCAS840 – NOVEMBER 2006 ABSOLUTE MAXIMUM RATINGS AVDD, PVDD, or VDD Supply voltage range VI Input voltage range (2) (3) VO Output voltage range (1) (2) IIK IOK IO (1) VALUE UNIT –0.7 to 2.2 V –0.5 to 2.2 V –0.5 to VCC + 0.5 V Input clamp current, (VI < 0 or VI > VCC) ±50 mA Output clamp current, (VO < 0 or VO > VCC) ±50 mA Continuous output current (VO = 0 to VCC) ±50 mA Continuous current through each VCC or GND θJA Package thermal Tstg Storage temperature range (1) (2) (3) (4) mA impedance (4) TBD TBD –65 to 150 °C Stress beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. This value is limited to 2.2 V maximum. The package thermal impedance is calculated in accordance with JESD 51-7. RECOMMENDED OPERATING CONDITIONS (1) MIN NOM MAX UNIT VDD DC supply voltage 1.425 1.5 1.575 V PVDD DC analog (PLL) output supply voltage 1.425 1.5 1.575 V AVDD DC PLL supply voltage VREF DC reference voltage VTT (2) PVDDQ V 0.49 × VDD 0.5 × VDD 0.51 × VDD V DC termination voltage VREF– 40 mV VREF VREF + 40 mV V VIH(AC) AC high-level input voltage VREF + 0.175 VDD + 0.3 V VIL(AC) AC low-level input voltage –0.3 VREF– 0.175 V VIH(DC) DC high-level input voltage VREF +0.1 VDD V VIL(DC) DC low-level input voltage 0 VREF– 0.1 V VIH_CMOS DC high-level input voltage RESET 0.65 × VDD VDD V VIL_CMOS DC low-level input voltage RESET 0 0.35 × VDD V 1/2PVDD +0.175 V VDD + 0.6 (4) V (3) Data (Dn), DCSn, DODTn, DCKEn, and PAR_IN inputs VIX Common-mode input voltage range CLK, CLK, FBIN, FBIN 1/2PVDD– 0.175 VID Peak-to-peak input voltage CLK, CLK, FBIN, FBIN 0.35 IOH High-level output current IOL Low-level output current (5) (5) Qn, QCSn, WCKEn, QODTn –TBD QCLKn, QCLKn –TBD Qn, QCSn, WCKEn, QODTn (1) (2) (3) (4) (5) Operating free-air temperature mA TBD QCLKn, QCLKn QERR output TA 1/2PVDD TBD mA 90 °C 25 0 The RESET and DCn inputs of the device must be held at valid logic voltage levels (not floating) to ensure proper device operation. The differential inputs must not be floating unless RESET is low. See the TI application report, Implication of Slow or Floating CMOS Inputs (SCBA004). The PLL is turned off and bypassed for test purposes when AVDD is grounded. During this test mode, PVDD remains within the recommended operating condition and no timing parameters are ensured. Stable Vref needs to be applied whenever RESET is high The input voltage of each CLK, CLK, FBIN or FBIN pin must not exceed VIL(AC) minimum and VIH(AC) maximum. Measured with CMR default settings. Submit Documentation Feedback 5 PRODUCT PREVIEW over operating free-air temperature range (unless otherwise noted) PACKAGE OPTION ADDENDUM www.ti.com 7-Nov-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing SN74SSTE32882ZALR PREVIEW BGA ZAL Pins Package Eco Plan (2) Qty 176 1000 TBD Lead/Ball Finish Call TI MSL Peak Temp (3) Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. 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