TI TMS44400DJ

TMS44400, TMS44400P, TMS46400, TMS46400P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C – MAY 1995 – REVISED NOVEMBER 1996
D
D
D
D
D
D
D
D
Organization . . . 1 048 576 × 4
Single 5-V Power Supply for TMS44400 / P
(± 10% Tolerance)
Single 3.3-V Power Supply for TMS46400 / P
(± 10% Tolerance)
Low Power Dissipation ( TMS46400P only)
200-µA CMOS Standby
200-µA Self Refresh
300-µA Extended-Refresh Battery
Backup
Performance Ranges:
’4x400/P-60
’4x400/P-70
’4x400/P-80
ACCESS ACCESS ACCESS
READ
TIME
TIME
TIME OR WRITE
(tRAC) (tCAC)
(tAA)
CYCLE
(MAX)
(MAX)
(MAX)
(MIN)
60 ns
15 ns
30 ns
110 ns
70 ns
18 ns
35 ns
130 ns
80 ns
20 ns
40 ns
150 ns
Enhanced Page-Mode Operation for Faster
Memory Access
CAS-Before-RAS ( CBR) Refresh
Long Refresh Period
1024-Cycle Refresh in 16 ms
128 ms (MAX) for Low-Power,
Self-Refresh Version ( TMS4x400P)
3-State Unlatched Output
Texas Instruments EPIC CMOS Process
DGA PACKAGE
( TOP VIEW )
DQ1
DQ2
W
RAS
A9
A0
A1
A2
A3
VCC
DJ PACKAGE
( TOP VIEW )
1
2
3
4
5
26
25
24
23
22
VSS
DQ4
DQ3
CAS
OE
9
10
18
17
11
12
13
16
15
14
A8
A7
A6
A5
A4
DQ1
DQ2
W
RAS
A9
A0
A1
A2
A3
VCC
1
2
3
4
5
26
25
24
23
22
VSS
DQ4
DQ3
CAS
OE
9
10
18
17
11
12
13
16
15
14
A8
A7
A6
A5
A4
PIN NOMENCLATURE
A0 – A9
CAS
DQ1 – DQ4
OE
RAS
VCC
VSS
W
D
Address Inputs
Column-Address Strobe
Data In
Output Enable
Row-Address Strobe
5-V or 3.3-V Supply
Ground
Write Enable
Operating Free-Air Temperature Range
0°C to 70°C
description
AVAILABLE OPTIONS
The TMS4x400 series is a set of high-speed,
SELF-REFRESH
4 194 304-bit dynamic random-access memories
POWER
REFRESH
BATTERY
DEVICE
SUPPLY
CYCLES
(DRAMs), organized as 1 048 576 words of four
BACKUP
bits each. The TMS4x400P series is a set of
TMS44400
5V
—
1024 in 16 ms
high-speed,
low-power,
self-refresh
with
TMS44400P
5V
Yes
1024 in 128 ms
extended-refresh,
4 194 304-bit
DRAMs,
TMS46400
3.3 V
—
1024 in 16 ms
organized as 1 048 576 words of four bits each.
TMS46400P
3.3
V
Yes
1024 in 128 ms
Both series employ state-of-the-art enhanced
performance
implanted
CMOS
(EPIC)
technology for high performance, reliability, and
low power.
These devices feature maximum RAS access times of 60 ns, 70 ns, and 80 ns. All addresses and data-in lines
are latched on chip to simplify system design. Data out is unlatched to allow greater system flexibility.
The TMS4x400 and TMS4x400P are offered in a 20 / 26-lead plastic small-outline ( TSOP) package ( DGA suffix)
and a 300-mil 20 / 26-lead plastic surface-mount SOJ package ( DJ suffix). Both packages are characterized for
operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright  1996, Texas Instruments Incorporated
ADVANCE INFORMATION concerns new products in the sampling or
preproduction phase of development. Characteristic data and other
specifications are subject to change without notice.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
1
ADVANCE INFORMATION
D
D
TMS44400, TMS44400P, TMS46400, TMS46400P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C – MAY 1995 – REVISED NOVEMBER 1996
logic symbol†
RAM 1024K × 4
9
10
11
12
14
15
16
17
18
5
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
20D10/21D0
A
ADVANCE INFORMATION
20D19/21D9
C20 [ROW]
G23/[REFRESH ROW]
24 [PWR DWN]
C21[COLUMN]
G24
4
RAS
23
CAS
&
3
22
W
OE
DQ4
24,25 EN
A,22D
26
2
24
25
DQ2
DQ3
23C22
23,21D
G25
1
DQ1
0
1 048 575
A,Z26
† This symbol is in accordance with ANSI / IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DJ package.
functional block diagram
RAS
CAS
W
OE
Timing and Control
A0
A1
8
ColumnAddress
Buffers
Column Decode
Sense Amplifiers
2
128K Array
128K Array
A9
16
RowAddress
Buffers
10
16
128K Array
R
o
w
128K Array
D
e
c
o
d
128K Array e 128K Array
16
16
10
2
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I/O
Buffers
1 of 16
Selection
2
DataIn
Reg.
4
4
DataOut
Reg.
DQ1 – DQ4
TMS44400, TMS44400P, TMS46400, TMS46400P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C – MAY 1995 – REVISED NOVEMBER 1996
operation
enhanced page mode
Unlike conventional page-mode DRAMs, the column-address buffers in this device are activated on the falling
edge of RAS. The buffers act as transparent or flow-through latches while CAS is high. The falling edge of CAS
latches the column addresses. This feature allows the TMS4x400 to operate at a higher data bandwidth than
conventional page-mode parts because data retrieval begins as soon as the column address is valid rather than
when CAS transitions low. This performance improvement is referred to as enhanced page mode. A valid
column address can be presented immediately after row-address hold time has been satisfied, usually well in
advance of the falling edge of CAS. In this case, data is obtained after tCAC maximum (access time from CAS
low) if tAA maximum (access time from column address) has been satisfied. In the event that column addresses
for the next cycle are valid at the time CAS goes high, access time for the next cycle is determined by the later
occurrence of tCAC (acces time from CAS low) or tCPA (access time from column precharge).
address (A0 – A9)
Twenty address bits are required to decode any one of the 1 048 576 storage-cell locations. Ten row-address
bits are set up on inputs A0 through A9 and latched onto the chip by RAS. The ten column-address bits are set
up on A0 through A9 and latched onto the chip by CAS. All addresses must be stable on or before the falling
edges of RAS and CAS. RAS is similar to a chip enable because it activates the sense amplifiers as well as the
row decoder. CAS is used as a chip select, activating the output buffer, as well as latching the address bits into
the column-address buffer.
write enable (W)
The read or write mode is selected through W input. A logic high on W selects the read mode and a logic low
selects the write mode. W can be driven from standard TTL circuits ( TMS44400/ P) or low voltage TTL circuits
( TMS46400/ P) without a pullup resistor. The data input is disabled when the read mode is selected. When W
goes low prior to CAS (early write), data out remains in the high-impedance state for the entire cycle, permitting
a write operation independent of the state of OE. This permits early-write operation to complete with OE
grounded.
data in / out (DQ1 – DQ4)
Data out is the same polarity as data in. The output is in the high-impedance (floating) state until CAS and OE
are brought low. In a read cycle, the output becomes valid after all access times are satisfied. The output remains
valid while CAS and OE are low. CAS or OE going high returns the output to a high-impedance state. This is
accomplished by bringing OE high prior to applying data, satisfying the OE to data delay hold time (tOED).
output enable (OE)
OE controls the impedance of the output buffers. When OE is high, the buffers remain in the high-impedance
state. Bringing OE low during a normal cycle activates the output buffers, putting them in the low-impedance
state. It is necessary for both RAS and CAS to be brought low for the output buffers to go into the low-impedance
state. They remain in the low-impedance state until either OE or CAS is brought high.
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3
ADVANCE INFORMATION
Enhanced-page-mode operation allows faster memory access by keeping the same row address while
selecting random column addresses. The time for row-address setup and hold and address multiplex is
eliminated. The maximum number of columns that can be accessed is determined by the maximum RAS low
time and the CAS page cycle time used. With minimum CAS page cycle time, all 1024 columns specified by
column addresses A0 through A9 can be accessed without intervening RAS cycles.
TMS44400, TMS44400P, TMS46400, TMS46400P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C – MAY 1995 – REVISED NOVEMBER 1996
refresh
A refresh operation must be performed at least once every 16 ms (128 ms for TMS4x400P) to retain data. This
can be achieved by strobing each of the 1024 rows (A0 – A9). A normal read or write cycle refreshes all bits in
each row that is selected. A RAS-only operation can be used by holding CAS at the high (inactive) level,
conserving power as the output buffer remains in the high-impedance state. Externally generated addresses
must be used for a RAS-only refresh. Hidden refresh can be performed while maintaining valid data at the
output. This is accomplished by holding CAS at VIL after a read operation and cycling RAS after a specified
precharge period, similar to a RAS-only refresh cycle. The external address is ignored during the hidden-refresh
cycle.
CAS-before-RAS (CBR) refresh
CBR refresh is utilized by bringing CAS low earlier than RAS (see parameter tCSR) and holding it low after RAS
falls (see parameter tCHR). For successive CBR refresh cycles, CAS can remain low while cycling RAS. The
external address is ignored and the refresh address is generated internally.
ADVANCE INFORMATION
A low-power battery-backup refresh mode that requires less than 300-µA (TMS46400P) or 500-µA
(TMS44400P) refresh current is available on the low-power devices. Data integrity is maintained using CBR
refresh with a period of 125 µs while holding RAS low for less than 1 µs. To minimize current consumption, all
input levels need to be at CMOS levels ( VIL ≤ 0.2 V, VIH ≥ VCC – 0.2 V ).
self refresh
The self-refresh mode is entered by dropping CAS low prior to RAS going low. CAS and RAS are both held low
for a minimum of 100 µs. The chip is then refreshed by an on-board oscillator. No external address is required
since the CBR counter is used to keep track of the address. To exit the self-refresh mode, both RAS and CAS
are brought high to satisfy tCHS. Upon exiting the self-refresh mode, a burst refresh (refresh a full set of row
addresses) must be executed before continuing with normal operation, to ensure that the DRAM is fully
refreshed.
power up
To achieve proper device operation, an initial pause of 200 µs followed by a minimum of eight initialization cycles
is required after full VCC level is achieved. These eight initialization cycles must include at least one refresh
( RAS-only or CBR) cycle.
test mode
The test mode is initiated with a CBR refresh cycle while simultaneously holding W low (WCBR). The entry cycle
performs an internal refresh cycle while internally setting the device to perform parallel read or write on
subsequent cycles. While in test mode, any desired data sequence can be performed on the device. The device
exits test mode if a CBR refresh cycle with W held high or a RAS-only refresh (ROR) cycle is performed.
The TMS4x400 / P is configured as a 512K × 8 bit device in test mode, where each DQ pin has a separate 2-bit
parallel read- and write-data bus. During a read cycle, the two internal bits are compared for each DQ pin
separately. If the two bits agree, the DQ pin goes high; if not, the DQ pin goes low. The two bits are written to
reflect the state of their respective DQ pins during a parallel-write operation. Each DQ pin is independent of the
others, and any data pattern desired can be written on each DQ pin. Test time is reduced by a factor of 4 for
this series.
4
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TMS44400, TMS44400P, TMS46400, TMS46400P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C – MAY 1995 – REVISED NOVEMBER 1996
test mode (continued)
Exit Cycle
Entry Cycle
Normal
Mode
Test Mode Cycle
RAS
CAS
W
Figure 1. Test-Mode Cycle Timing†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage range, VCC:
TMS44400, TMS44400P . . . . . . . . . . . . . . . . . . . . . . . – 1.0 V to 7.0 V
TMS46400, TMS46400P . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
Voltage range on any pin (see Note 1) TMS44400, TMS44400P . . . . . . . . . . . . . . . . . . . . . . . – 1.0 V to 7.0 V
TMS46400, TMS46400P . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 150°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
TMS44400 / P
TMS46400 / P
MIN
NOM
MAX
MIN
NOM
5
3.3
VCC
VIH
Supply voltage
4.5
5.5
3
High-level input voltage
2.4
6.5
2
VIL
Low-level input voltage (see Note 2)
–1
0.8
– 0.3
MAX
3.6
VCC + 0.3
0.8
UNIT
V
V
V
TA
Operating free-air temperature
0
70
0
70
°C
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.
POST OFFICE BOX 1443
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5
ADVANCE INFORMATION
† The states of W, data in, and address are defined by the type of cycle used during test mode.
TMS44400, TMS44400P, TMS46400, TMS46400P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C – MAY 1995 – REVISED NOVEMBER 1996
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
VOH
VOL
High-level output voltage
Low-level output voltage
’44400 - 60
’44400P - 60
TEST
CONDITIONS
MIN
IOH = – 5 mA
IOL = 4.2 mA
’44400 - 70
’44400P - 70
MAX
2.4
MIN
MAX
2.4
’44400 - 80
’44400P - 80
MIN
UNIT
MAX
2.4
V
0.4
0.4
0.4
V
± 10
± 10
± 10
µA
ADVANCE INFORMATION
II
Input current (leakage)
VCC = 5.5 V,
VI = 0 V to 6.5 V,
All others = 0 V to VCC
IO
Output current (leakage)
VCC = 5.5 V,
CAS high
VO = 0 V to VCC,
± 10
± 10
± 10
µA
ICC1
Read- or write-cycle current
(see Note 3)
VCC = 5.5 V,
Minimum cycle
105
90
80
mA
2
2
2
mA
1
1
1
mA
500
500
500
µA
105
90
80
mA
90
80
70
mA
500
500
500
µA
5
5
5
mA
500
500
500
µA
After one memory cycle,
RAS and CAS high,
VIH = 2.4 V ( TTL)
ICC2
S db current
Standby
After one memory
cycle, RAS and CAS
high
high,
VIH = VCC – 0.2 V
(CMOS)
’44400
’44400P
ICC3
Average refresh current
(RAS only or CBR)
(see Note 4)
VCC = 5.5 V, Minimum cycle,
RAS cycling,
CAS high (RAS only);
RAS low after CAS low (CBR)
ICC4
Average page
current
(see Notes 3 and 5)
VCC = 5.5 V,
RAS low,
ICC6†
Self-refresh current
(see Note 3)
CAS ≤ 0.2 V,
RAS < 0.2 V,
tRAS and tCAS > 1000 ms
ICC7
Standby current, outputs
enabled (see Note 3)
RAS = VIH,
CAS = VIL,
Data out = enabled
Battery-backup current
(with CBR)
tRC = 125 µs, tRAS ≤ 1 ms,
VCC – 0.2 V ≤ VIH ≤ 6.5 V,
0 V ≤ VIL ≤ 0.2 V,
W and OE = VIH,
Address and data stable
ICC10†
tPC = MIN,
CAS cycling
† For TMS44400P only
NOTES: 3. ICC MAX is specified with no load connected.
4. Measured with a maximum of one address change while RAS = VIL
5. Measured with a maximum of one address change while CAS = VIH
6
POST OFFICE BOX 1443
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TMS44400, TMS44400P, TMS46400, TMS46400P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C – MAY 1995 – REVISED NOVEMBER 1996
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
TEST
CONDITIONS
VOH
High-level
High
level
output voltage
IOH = – 2 mA (LVTTL)
IOH = – 100 µA (LVCMOS)
VOL
Low level
Low-level
output voltage
IOL = 2 mA (LVTTL)
IOL = 100 µA (LVCMOS)
II
Input current
(leakage)
IO
ICC1
’46400 - 60
’46400P - 60
’46400 - 70
’46400P - 70
’46400 - 80
’46400P - 80
MIN
MIN
MIN
MAX
2.4
2.4
VCC – 0.2
UNIT
MAX
2.4
VCC – 0.2
V
VCC – 0.2
0.4
0.4
0.4
0.2
0.2
0.2
VI = 0 V to 3.9 V, VCC = 3.6 V,
All others = 0 V to VCC
± 10
± 10
± 10
µA
Output current
(leakage)
VO = 0 V to VCC, VCC = 3.6 V,
CAS high
± 10
± 10
± 10
µA
Read- or
write-cycle
current
(see Note 3)
Minimum cycle,
70
60
50
mA
2
2
2
mA
’46400
300
300
300
µA
’46400P
200
200
200
µA
VCC = 3.6 V
After one memory cycle,
RAS and CAS high,
VIH = 2 V (LVTTL)
ICC2
MAX
Standby
S
db
current
After one memory
cycle, RAS and CAS
high
high,
VIH = VCC – 0.2 V
(LVCMOS)
V
ICC3
Average
refresh current
(RAS only or
CBR)
(see Note 4)
Minimum cycle, VCC = 3.6 V,
RAS cycling,
CAS high (RAS only);
RAS low after CAS low (CBR)
70
60
50
mA
ICC4
Average page
current
(see Notes 3
and 5)
tPC = MIN,
RAS low,
VCC = 3.6 V,
CAS cycling
60
50
40
mA
ICC6†
Self-refresh
current
(see Note 3)
CAS ≤ 0.2 V,
RAS < 0.2 V,
tRAS and tCAS > 1000 ms
200
200
200
µA
ICC7
Standby
current,
outputs
enabled
(see Note 3)
RAS = VIH,
CAS = VIL,
Data out = enabled
5
5
5
mA
ICC10†
tRC = 125 µs,
tRAS ≤ 1 ms,
Battery-backup VCC – 0.2 V ≤ VIH ≤ 3.9 V,
current
0 V ≤ VIL ≤ 0.2 V,
(with CBR)
W and OE = VIH,
Address and data stable
300
300
300
µA
ADVANCE INFORMATION
PARAMETER
† For TMS46400P only
NOTES: 3. ICC MAX is specified with no load connected.
4. Measured with a maximum of one address change while RAS = VIL
5. Measured with a maximum of one address change while CAS = VIH
POST OFFICE BOX 1443
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7
TMS44400, TMS44400P, TMS46400, TMS46400P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C – MAY 1995 – REVISED NOVEMBER 1996
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 6)
PARAMETER
MIN
MAX
UNIT
Ci(A)
Input capacitance, A0 – A10
5
pF
Ci(RC)
Input capacitance, CAS and RAS
7
pF
Ci(OE)
Input capacitance, OE
7
pF
Ci(W)
Input capacitance, W
7
pF
Co
Output capacitance
7
pF
NOTE 6: VCC = 5 V ± .5 V for the TMS44400 devices, VCC = 3.3 V ± 0.3 V for the TMS46400 devices, and the bias on pins under test is 0 V.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER
’4x400 - 60
’4x400P - 60
’4x400 - 70
’4x400P - 70
’4x400 - 80
’4x400P - 80
MIN
MIN
MIN
MAX
MAX
UNIT
MAX
ADVANCE INFORMATION
tAA
tCAC
Access time from column address
30
35
40
ns
Access time from CAS low
15
18
20
ns
tCPA
tRAC
Access time from column precharge
35
40
45
ns
Access time from RAS low
60
70
80
ns
tOEA
tCLZ
Access time from OE low
15
18
20
ns
CAS to output in low impedance
0
tOFF
tOEZ
Output-disable time after CAS high (see Note 7)
0
15
0
18
0
20
ns
Output-disable time after OE high (see Note 7)
0
15
0
18
0
20
ns
NOTE 7: tOFF is specified when the output is no longer driven.
8
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
0
0
ns
TMS44400, TMS44400P, TMS46400, TMS46400P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C – MAY 1995 – REVISED NOVEMBER 1996
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
’4x400 - 60
’4x400P - 60
’4x400 - 70
’4x400P - 70
’4x6400 - 80
’4x400P - 80
MIN
MIN
MIN
MAX
UNIT
MAX
tRC
tRWC
Cycle time, random read or write (see Note 8)
110
130
150
ns
Cycle time, read-write
155
181
205
ns
tPC
tPRWC
Cycle time, page-mode read or write (see Note 9)
40
45
50
ns
Cycle time, page-mode read-write
85
96
105
ns
tRASP
tRAS
Pulse duration, RAS low, page mode (see Note 10)
60 100 000
70 100 000
80 100 000
Pulse duration, RAS low, nonpage mode (see Note 10)
60
70
80
tRASS
tCAS
Pulse duration, RAS low, self refresh
Pulse duration, CAS low (see Note 11)
10
tCP
tRP
Pulse duration, CAS high
10
tRPS
tWP
Precharge time after self refresh using RAS
tASC
tASR
10 000
100
Pulse duration, RAS high (precharge)
10 000
100
10 000
18
10
10 000
20
ns
µs
100
10 000
ns
10 000
ns
10
ns
40
50
60
ns
110
130
150
ns
10
10
10
ns
Setup time, column address before CAS low
0
0
0
ns
Setup time, row address before RAS low
0
0
0
ns
tDS
tRCS
Setup time, data (see Note 12)
0
0
0
ns
Setup time, W high before CAS low
0
0
0
ns
tCWL
tRWL
Setup time, W low before CAS high
15
18
20
ns
Setup time, W low before RAS high
15
18
20
ns
tWCS
tWSR
Setup time, W low before CAS low (early-write operation only)
0
0
0
ns
Setup time, W high (CBR refresh only)
10
10
10
ns
tWTS
tCAH
Setup time, W low (test mode only)
10
10
10
ns
Hold time, column address after CAS low
10
15
15
ns
tDHR
tDH
Hold time, data after RAS low (see Note 13)
50
55
60
ns
Hold time, data (see Note 12)
10
15
15
ns
tAR
tRAH
Hold time, column address after RAS low (see Note 13)
50
55
60
ns
Hold time, row address after RAS low
10
10
10
ns
tRCH
tRRH
Hold time, W high after CAS high (see Note 14)
0
0
0
ns
0
0
0
ns
tWCH
tWCR
Hold time, W low after CAS low (early-write operation only)
10
15
15
ns
Hold time, W low after RAS low (see Note 13)
50
55
60
ns
tWHR
tWTH
Hold time, W high (CBR refresh only)
10
10
10
ns
Hold time, W low (test mode only)
10
10
10
ns
tCHS
tOEH
Hold time, CAS low after RAS high (self refresh)
– 50
– 50
– 50
ns
15
18
20
ns
18
20
ns
Pulse duration, write
Hold time, W high after RAS high (see Note 14)
Hold time, OE command
tOED
Hold time, OE to data delay
15
NOTES: 8. All cycle times assume tT = 5 ns.
9. To ensure tPC min, tASC should be ≥ tCP .
10. In a read-write cycle, tRWD and tRWL must be observed.
11. In a read-write cycle, tCWD and tCWL must be observed.
12. Referenced to the later of CAS or W in write operations
13. The minimum value is measured when tRCD is set to tRCD min as a reference.
14. Either tRRH or tRCH must be satisfied for a read cycle.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
ADVANCE INFORMATION
MAX
9
TMS44400, TMS44400P, TMS46400, TMS46400P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C – MAY 1995 – REVISED NOVEMBER 1996
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued)
’4x400 - 60
’4x400P - 60
MIN
MAX
’4x400 - 70
’4x400P - 70
MIN
MAX
’4x400 - 80
’4x400P - 80
MIN
UNIT
MAX
ADVANCE INFORMATION
tROH
tAWD
Hold time, RAS referenced to OE
10
10
10
ns
Delay time, column address to W low (read-write operation only)
55
63
70
ns
tCHR
tCRP
Delay time, RAS low to CAS high (CBR refresh only)
10
10
10
ns
Delay time, CAS high to RAS low
0
0
0
ns
tCSH
tCSR
Delay time, RAS low to CAS high
60
70
80
ns
5
5
5
ns
tCWD
tRAD
Delay time, CAS low to W low (read-write operation only)
40
46
50
ns
Delay time, RAS low to column address (see Note 15)
15
tRAL
tCAL
Delay time, column address to RAS high
30
Delay time, column address to CAS high
30
tRCD
tRPC
Delay time, RAS low to CAS low (see Note 15)
20
Delay time, RAS high to CAS low
0
0
tRSH
tRWD
Delay time, CAS low to RAS high
15
Delay time, RAS low to W low (read-write operation only)
85
tTAA
tTCPA
Access time from address (test mode)
Access time from column precharge (test mode)
tTRAC
Access time from RAS (test mode)
tREF
Refresh time interval
Delay time, CAS low to RAS low (CBR refresh only)
15
35
35
20
40
40
35
45
15
ns
40
52
20
ns
60
18
20
ns
98
110
ns
35
40
45
ns
40
45
50
ns
65
75
85
ns
2
16
16
16
ms
128
128
128
ms
30
ns
30
2
30
2
PARAMETER MEASUREMENT INFORMATION
1.31 V
VCC = 5 V
RL = 218 Ω
R1 = 828 Ω
Output Under Test
CL = 100 pF
(see Note A)
CL = 100 pF
(see Note A)
(a) LOAD CIRCUIT
R2 = 295 Ω
(b) ALTERNATE LOAD CIRCUIT
NOTE A: CL includes probe and fixture capacitance.
Figure 2. Load Circuits for Timing Parameters
10
POST OFFICE BOX 1443
ns
ns
’4x400P
Output Under Test
ns
0
’4x400
tT
Transition time
NOTE 15: The maximum value is specified only to ensure access time.
30
• HOUSTON, TEXAS 77251–1443
TMS44400, TMS44400P, TMS46400, TMS46400P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C – MAY 1995 – REVISED NOVEMBER 1996
PARAMETER MEASUREMENT INFORMATION
1.4 V
VCC = 3.3 V
RL = 500 Ω
R1 = 1178 Ω
Output Under Test
Output Under Test
R2 = 868 Ω
CL = 100 pF
(see Note A)
CL = 100 pF
(see Note A)
(a) LOAD CIRCUIT
(b) ALTERNATE LOAD CIRCUIT
NOTE A: CL includes probe and fixture capacitance.
Figure 3. Low-Voltage Load Circuits for Timing Parameters
tRC
ADVANCE INFORMATION
tRAS
RAS
tRP
tCSH
tRCD
tCRP
tRSH
tT
tCAS
CAS
tRAD
tCP
tASC
tASR
tRAL
tRAH
A0 – A9
tCAL
Row
Don’t Care
Column
tRCS
tRRH
tAR
tRCH
tCAH
W
Don’t Care
Don’t Care
tCAC
tOFF
tAA
DQ1 – DQ4
Hi-Z
Valid Data Out
See Note A
tCLZ
tRAC
tOEZ
tOEA
OE
tROH
Don’t Care
Don’t Care
NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
Figure 4. Read-Cycle Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
11
TMS44400, TMS44400P, TMS46400, TMS46400P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C – MAY 1995 – REVISED NOVEMBER 1996
PARAMETER MEASUREMENT INFORMATION
tRC
tRAS
RAS
tT
tRSH
tRCD
tRP
tCAS
tCRP
tCSH
CAS
tASC
tCAH
tRAH
tRAL
tAR
ADVANCE INFORMATION
A0 – A9
tCP
tCAL
tASR
Row
Don’t Care
Column
tCWL
tRWL
tRAD
tWCH
tWCR
W
tWCS
Don’t Care
Don’t Care
tDH
tWP
tDS
DQ1 – DQ4
Valid Data
Don’t Care
tDHR
Don’t Care
OE
Figure 5. Early-Write-Cycle Timing
12
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS44400, TMS44400P, TMS46400, TMS46400P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C – MAY 1995 – REVISED NOVEMBER 1996
PARAMETER MEASUREMENT INFORMATION
tRC
tRAS
RAS
tT
tRP
tRSH
tRCD
tCRP
tCAS
tCSH
CAS
tASC
tCAL
tCAH
tRAH
tCP
tAR
A0 – A9
Row
ADVANCE INFORMATION
tRAL
tASR
Don’t Care
Column
tCWL
tRAD
tRWL
tDS
W
Don’t Care
Don’t Care
tWP
tWCR
tDH
tDHR
DQ1 – DQ4
Don’t Care
Valid Data
tOED
OE
Don’t Care
tOEH
Don’t Care
Don’t Care
Figure 6. Write-Cycle Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
13
TMS44400, TMS44400P, TMS46400, TMS46400P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C – MAY 1995 – REVISED NOVEMBER 1996
PARAMETER MEASUREMENT INFORMATION
tRWC
tRAS
RAS
tRP
tT
tCRP
tRCD
tCAS
tASR
CAS
tASC
tCP
tRAH
tT
tCAH
tRAD
tCWL
tAR
A0 – A9
Row
Don’t Care
Column
ADVANCE INFORMATION
tRWL
tWP
tRCS
tRWD
W
Don’t Care
tAWD
tCWD
tDS
tCAC
tAA
tDH
tCLZ
Data
Out
DQ1 – DQ4
See Note A
Data
In
Don’t Care
tOEH
tOEZ
tRAC
tOED
OE
Don’t Care
tOEH
Don’t Care
NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
Figure 7. Read-Write-Cycle Timing
14
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS44400, TMS44400P, TMS46400, TMS46400P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C – MAY 1995 – REVISED NOVEMBER 1996
PARAMETER MEASUREMENT INFORMATION
tRP
tRASP
RAS
tPC
tRCD
tCP
tCSH
tT
CAS
tCRP
tRSH
tCAS
tRAH
tCAH
A0 – A9
tRAL
tCAL
tASC
Row
Column
Don’t Care
Column
tAR
tAA
(see Note A)
tRRH
tRCH
tRCS
W
tRAD
tCPA
(see Note A)
tCAC
tAA
tOFF
tRAC
tCLZ
DQ1 – DQ4
Valid
Out
Valid
Out
See Note B
tOEZ
OE
Don’t Care
ADVANCE INFORMATION
tASR
tOEA
tOEZ
tOEA
NOTES: A. Access time is tCPA or tAA dependent.
B. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
Figure 8. Enhanced-Page-Mode Read-Cycle Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
15
TMS44400, TMS44400P, TMS46400, TMS46400P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C – MAY 1995 – REVISED NOVEMBER 1996
PARAMETER MEASUREMENT INFORMATION
tRP
tRASP
RAS
tCSH
tCRP
tPC
tRCD
tRSH
tCAS
CAS
tASR
tASC
tCP
tAR
tRAH
A0 – A9
tRAL
tCAL
tCAH
Row
Column
Don’t Care
Column
ADVANCE INFORMATION
tRAD
tCWL
tCWL
tWCR
tRWL
tWP
tDHR
W
Don’t Care
Don’t Care
See Note A
See Note A
tDH
tDS
tDS
DQ1 – DQ4
Don’t Care
tOEH
tDH
See Note A
Valid
In
Valid Data In
tOEH
OE
Don’t Care
tOED
Don’t Care
Don’t Care
NOTES: A. Referenced to CAS or W, whichever occurs last
B. A read cycle or a read-write cycle can be intermixed with write cycles as long as read and read-write timing specifications are not
violated.
Figure 9. Enhanced-Page-Mode Write-Cycle Timing
16
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS44400, TMS44400P, TMS46400, TMS46400P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C – MAY 1995 – REVISED NOVEMBER 1996
PARAMETER MEASUREMENT INFORMATION
tRP
tRASP
RAS
tCSH
tRSH
tPRWC
tRCD
tCP
tCRP
tCAS
CAS
tASR
tASC
tAR
tRAD
A0 – A9
Row
Column
tRAH
Column
tCWD
tAWD
ADVANCE INFORMATION
tCAH
Don’t Care
tCWL
tRWD
tRWL
tWP
W
tRCS
tOEH
tDS
tAA
tCPA
tRAC
tDH
tCAC
DQ1 – DQ4
Valid In
tCLZ
Valid Out
Valid Out
(see Note A)
Valid In
tOED
tOEH
tOEA
tOEZ
OE
NOTES: A. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
B. A read or write cycle can be intermixed with read-write cycles as long as the read and write timing specifications are not violated.
Figure 10. Enhanced-Page-Mode Read-Write-Cycle Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
17
TMS44400, TMS44400P, TMS46400, TMS46400P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C – MAY 1995 – REVISED NOVEMBER 1996
PARAMETER MEASUREMENT INFORMATION
tRC
tRAS
RAS
tRP
tCRP
tRPC
tT
CAS
Don’t Care
tRAH
tASR
A0 – A9
Don’t Care
Row
ADVANCE INFORMATION
W
Don’t Care
DQ1 – DQ4
Don’t Care
OE
Don’t Care
Don’t Care
Figure 11. RAS-Only Refresh-Cycle Timing
18
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
Row
TMS44400, TMS44400P, TMS46400, TMS46400P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C – MAY 1995 – REVISED NOVEMBER 1996
PARAMETER MEASUREMENT INFORMATION
tRC
tRP
tRAS
RAS
tCSR
tRPC
tCHR
tT
CAS
tWSR
tWHR
A0 – A9
Don’t Care
OE
Don’t Care
ADVANCE INFORMATION
W
Hi-Z
DQ1 – DQ4
Figure 12. Automatic-CBR-Refresh-Cycle Timing
tRP
tRPS
tRASS
RAS
tCSR
tRPC
tCHS
tT
CAS
tWSR
tWHR
W
A0 – A9
Don’t Care
OE
Don’t Care
Hi-Z
DQ1 – DQ4
Figure 13. Self-Refresh-Cycle Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
19
TMS44400, TMS44400P, TMS46400, TMS46400P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C – MAY 1995 – REVISED NOVEMBER 1996
PARAMETER MEASUREMENT INFORMATION
Refresh Cycle
Memory Cycle
Refresh Cycle
tRP
tRP
tRAS
tRAS
RAS
tCHR
tCAS
CAS
tAR
ADVANCE INFORMATION
tCAH
tASC
tRAH
tASR
A0 – A10
Row
Col
Don’t Care
tRRH
tRCS
W
tWSR
tWHR
tWHR
tWHR
tWSR
tWSR
tRAC
tAA
tCAC
tOFF
tCLZ
DQ1 – DQ4
Valid Data
tOEZ
tOEA
OE
Figure 14. Hidden-Refresh-Cycle (Read) Timing
20
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS44400, TMS44400P, TMS46400, TMS46400P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C – MAY 1995 – REVISED NOVEMBER 1996
PARAMETER MEASUREMENT INFORMATION
Refresh Cycle
Refresh Cycle
Memory Cycle
tRP
tRP
tRAS
tRAS
RAS
tCHR
tCAS
CAS
tCAH
tASC
tAR
tASR
A0 – A9
Row
ADVANCE INFORMATION
tRAH
Col
Don’t Care
tRRH
tWHR
tWCS
tWSR
tWCR
tWP
W
tWCH
tDH
tDHR
tDS
DQ1 – DQ4
Valid Data
Don’t Care
Don’t Care
OE
Figure 15. Hidden-Refresh-Cycle (Write) Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
21
TMS44400, TMS44400P, TMS46400, TMS46400P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C – MAY 1995 – REVISED NOVEMBER 1996
PARAMETER MEASUREMENT INFORMATION
tRC
tRP
tRAS
RAS
tCSR
tRPC
tCHR
tT
CAS
tWTH
tWTS
Don’t Care
W
ADVANCE INFORMATION
A0 – A9
Don’t Care
OE
Don’t Care
Hi-Z
DQ1 – DQ4
Figure 16. Test-Mode Entry-Cycle Timing
device symbolization (TMS44400 illustrated)
-SS
Speed ( - 60, - 70, - 80)
Low-Power / Self-Refresh Designator (Blank or P)
TMS44400
DJ
W
M LLL
Package Code
B
Y
P
Assembly Site Code
Lot Traceability Code
Month Code
Year Code
Die Revision Code
Wafer Fab Code
22
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS44400, TMS44400P, TMS46400, TMS46400P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C – MAY 1995 – REVISED NOVEMBER 1996
PARAMETER MEASUREMENT INFORMATION
DJ (R-PDSO-J20/26)
PLASTIC SMALL-OUTLINE J-LEAD PACKAGE
0.680 (17,27)
0.670 (17,02)
26
22
18
14
0.340 (8,64)
0.330 (8,38)
0.305 (7,75)
0.295 (7,49)
1
5
9
13
0.008 (0,20) NOM
0.106 (2,69) MAX
0.148 (3,76)
0.128 (3,25)
ADVANCE INFORMATION
0.032 (0,81)
0.026 (0,66)
Seating Plane
0.020 (0,51)
0.016 (0,41)
0.004 (0,10)
0.007 (0,18) M
0.275 (6,99)
0.260 (6,60)
0.050 (1,27)
4040092-2 / B 10/94
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Plastic body dimensions do not include mold protrusion. Maximum mold protrusion is 0.005 (0,125).
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
23
TMS44400, TMS44400P, TMS46400, TMS46400P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C – MAY 1995 – REVISED NOVEMBER 1996
MECHANICAL DATA
DGA (R-PDSO-G20/26)
PLASTIC SMALL-OUTLINE PACKAGE
0.020 (0,50)
0.012 (0,30)
0.050 (1,27)
26
0.008 (0,21) M
14
0.371 (9,42)
0.355 (9,02)
0.304 (7,72)
0.296 (7,52)
0.006 (0,15) NOM
1
13
ADVANCE INFORMATION
0.679 (17,24)
0.671 (17,04)
Gage Plane
0.010 (0,25)
0°– 5°
ā
0.024 (0,60)
0.016 (0,40)
Seating Plane
0.050 (1,27) MAX
0.004 (0,10)
0.004 (0,10) MIN
4040265-2 / B 10/94
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
24
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
IMPORTANT NOTICE
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Copyright  1996, Texas Instruments Incorporated