TI TPIC5303

SLIS039A − SEPTEMBER 1994 − REVISED SEPTEMBER 1995
•
•
•
•
•
Low rDS(on) . . . 0.4 Ω Typ
High Voltage Output . . . 60 V
Extended ESD Capability . . . 4000 V
Pulsed Current . . . 5 A Per Channel
Fast Commutation Speed
D PACKAGE
(TOP VIEW)
DRAIN2
DRAIN2
SOURCE2
SOURCE2
GATE2
DRAIN3
DRAIN3
GND
description
1
16
2
15
3
14
4
13
5
12
GATE1
SOURCE1
SOURCE1
DRAIN1
DRAIN1
SOURCE3
SOURCE3
GATE3
11
The TPIC5303 is a monolithic gate-protected
10
7
power DMOS array that consists of three
9
8
independent electrically isolated N-channel
enhancement-mode DMOS transistors. Each
transistor features integrated high-current zener
diodes (ZCXa and ZCXb) to prevent gate damage in the event that an overstress condition occurs. These zener
diodes also provide up to 4000 V of ESD protection when tested using the human-body model of a 100-pF
capacitor in series with a 1.5-kΩ resistor.
6
The TPIC5303 is offered in a standard 16-pin small-outline surface-mount (D) package and is characterized for
operation over the case temperature range of − 40°C to 125°C.
schematic
DRAIN1
GATE2
12, 13
Q1
GATE1
DRAIN2
5
DRAIN3
9
Q2
D1
Z1
16
GATE3
1, 2
6, 7
Q3
D2
Z2
Z3
ZC1b
ZC2b
ZC3b
ZC1a
ZC2a
ZC3a
14, 15
SOURCE1
8
GND
D3
3, 4
SOURCE2
10, 11
SOURCE3
NOTE A: For correct operation, no terminal pin may be taken below GND.
Copyright  1995, Texas Instruments Incorporated
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• DALLAS, TEXAS 75265
• HOUSTON, TEXAS 77251−1443
POST OFFICE BOX 655303
POST OFFICE BOX 1443
1
SLIS039A − SEPTEMBER 1994 − REVISED SEPTEMBER 1995
absolute maximum ratings over operating case temperature range (unless otherwise noted)†
Drain-to-source voltage, VDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 V
Source-to-GND voltage (Q1, Q2, and Q3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 V
Drain-to-GND voltage (Q1, Q2, and Q3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 V
Gate-to-source voltage range, VGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −9 V to 18 V
Continuous drain current, each output, TC = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 A
Continuous source-to-drain diode current, TC = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 A
Pulsed drain current, each output, Imax, TC = 25°C (see Note 1 and Figure 15) . . . . . . . . . . . . . . . . . . . . . 5 A
Continuous gate-to-source zener-diode current, TC = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Pulsed gate-to-source zener-diode current, TC = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 500 mA
Single-pulse avalanche energy, EAS, TC = 25°C (see Figures 4, 15, and 16) . . . . . . . . . . . . . . . . . . . 10.2 mJ
Continuous total power dissipation, TC = 25°C (see Figure 15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.08 W
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 150°C
Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: Pulse duration = 10 ms, duty cycle = 2%
2
•
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•
SLIS039A − SEPTEMBER 1994 − REVISED SEPTEMBER 1995
electrical characteristics, TC = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
V(BR)DSX
Drain-to-source breakdown voltage
VGS(th)
Gate-to-source threshold voltage
V(BR)GS
V(BR)SG
Gate-to-source breakdown voltage
ID = 250 µA,
ID = 1 mA,
See Figure 5
VGS = 0
VDS = VGS,
Source-to-gate breakdown voltage
IGS = 250 µA
ISG = 250 µA
V(BR)
Reverse drain-to-GND breakdown voltage (across
D1, D2, D3)
Drain-to-GND current = 250 µA
VDS(on)
Drain-to-source on-state voltage
ID = 1.4 A,
See Notes 2 and 3
VF(SD)
Forward on-state voltage, source-to-drain
IS = 1.4 A,
VGS = 0 (Z1, Z2, Z3),
See Notes 2 and 3 and Figure 12
VF
Forward on-state voltage, GND-to-drain
ID = 1.4 A (D1, D2, D3),
See Notes 2 and 3
IDSS
Zero-gate-voltage drain current
VDS = 48 V,
VGS = 0
TC = 25°C
TC = 125°C
IGSSF
Forward-gate current, drain short circuited to
source
VGS = 15 V,
IGSSR
Reverse-gate current, drain short circuited to
source
Ilkg
rDS(on)
MIN
TYP
MAX
60
1.5
UNIT
V
1.8
2.2
V
18
V
9
V
100
V
VGS = 10 V,
0.56
0.64
V
0.9
1.1
V
5
V
0.05
1
0.5
10
VDS = 0
20
200
nA
VSG = 5 V,
VDS = 0
10
100
nA
1
VDGND = 48 V
TC = 25°C
TC = 125°C
0.05
Leakage current, drain-to-GND
0.5
10
TC = 25°C
0.4
0.46
Static drain-to-source on-state resistance
VGS = 10 V,
ID = 1.4 A,
See Notes 2 and 3
and Figures 6 and 7
TC = 125°C
0.62
0.66
Forward transconductance
Ciss
Short-circuit input capacitance, common source
Coss
Short-circuit output capacitance, common source
Crss
Short-circuit reverse transfer capacitance, common
source
VDS = 25 V,
f = 1 MHz,
µA
A
Ω
VDS = 15 V,
ID = 0.7 A,
See Notes 2 and 3 and Figure 9
gfs
µA
A
1
VGS = 0,
See Figure 11
1.19
S
107
137
71
89
22
28
pF
NOTES: 2. Technique should limit TJ − TC to 10°C maximum.
3. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
source-to-drain and GND-to-drain diode characteristics, TC = 25°C
PARAMETER
trr
Reverse-recovery time
QRR
Total diode charge
TEST CONDITIONS
IS = 0.7 A,
VGS = 0,
See Figures 1 and 14
VDS = 48 V,
A/ s,
di/dt = 100 A/µs,
•
MIN
92
D1, D2, and D3
244
Z1, Z2, and Z3
0.1
D1, D2, and D3
1.3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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•
TYP
Z1, Z2, and Z3
MAX
UNIT
ns
µC
3
SLIS039A − SEPTEMBER 1994 − REVISED SEPTEMBER 1995
resistive-load switching characteristics, TC = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
25
40
27
40
15
25
td(on)
td(off)
Turn-on delay time
tr2
tf2
Rise time
Qg
Total gate charge
Qgs(th)
Threshold gate-to-source charge
Qgd
Gate-to-drain charge
LD
Internal drain inductance
5
LS
Internal source inductance
5
Rg
Internal gate resistance
Turn-off delay time
RL = 36 Ω,
See Figure 2
VDD = 25 V,
tf1 = 10 ns,
tr1 = 10 ns,
Fall time
VDS = 48 V,
See Figure 3
ID = 0.7 A,
VGS = 10 V,
7
14
2.1
2.6
0.3
0.38
1.2
1.5
UNIT
ns
nC
nH
Ω
0.25
thermal resistance
PARAMETER
TEST CONDITIONS
MIN
TYP
RθJA
Junction-to-ambient thermal resistance
See Notes 4 and 7
115
RθJB
Junction-to-board thermal resistance
See Notes 5 and 7
64
RθJP Junction-to-pin thermal resistance
See Notes 6 and 7
NOTES: 4. Package mounted on an FR4 printed-circuit board with no heatsink.
5. Package mounted on a 24 inch2, 4-layer FR4 printed-circuit board.
6. Package mounted in intimate contact with infinite heatsink.
7. All outputs with equal power
33
4
•
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•
MAX
UNIT
°C/W
C/W
SLIS039A − SEPTEMBER 1994 − REVISED SEPTEMBER 1995
PARAMETER MEASUREMENT INFORMATION
1
Reverse di/dt = 100 A/µs
I S − Source-to-Drain Diode Current − A
0.5
0
− 0.5
25% of IRM†
−1
Shaded Area = QRR
− 1.5
−2
− 2.5
IRM†
trr(SD)
−3
0
100
200
300
400
500
600
VDS = 48 V
VGS = 0
TJ = 25°C
Z1, Z2, and Z3‡
700
800
900 1000
Time − ns
† IRM = maximum recovery current
‡ The above waveform is representative of D1, D2, and D3 in shape only.
Figure 1. Reverse-Recovery-Current Waveform of Source-to-Drain Diode
•
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•
5
SLIS039A − SEPTEMBER 1994 − REVISED SEPTEMBER 1995
PARAMETER MEASUREMENT INFORMATION
VDD = 25 V
tr1
RL
Pulse Generator
10 V
VDS
VGS
0V
VGS
50 Ω
tr2
tf2
CL 30 pF
(see Note A)
50 Ω
td(off)
td(on)
DUT
Rgen
tf1
VDD
VDS
VDS(on)
VOLTAGE WAVEFORMS
TEST CIRCUIT
NOTE A: CL includes probe and jig capacitance.
Figure 2. Resistive-Switching Test Circuit and Voltage Waveforms
Current
Regulator
12-V
Battery
0.2 µF
50 kΩ
10 V
0.3 µF
VDS
0V
Qg
Same Type
as DUT
Qgs(th)
VDD
Qgd
VGS
DUT
IG = 100 µA
Gate Voltage
Time
IG CurrentSampling Resistor
ID CurrentSampling Resistor
TEST CIRCUIT
Figure 3. Gate-Charge Test Circuit and Waveform
6
•
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•
VOLTAGE WAVEFORM
SLIS039A − SEPTEMBER 1994 − REVISED SEPTEMBER 1995
PARAMETER MEASUREMENT INFORMATION
VDD = 25 V
476 µH
Pulse Generator
(see Note A)
ID
VDS
tav
tw
15 V
VGS
0V
IAS
(see Note B)
VGS
50 Ω
ID
DUT
0V
Rgen
50 Ω
V(BR)DSX = 60 V Min
VDS
0V
VOLTAGE AND CURRENT WAVEFORMS
TEST CIRCUIT
NOTES: A. The pulse generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, ZO = 50 Ω.
B. Input pulse duration (tw) is increased until peak current IAS = 5 A.
I
V
t av
AS
(BR)DSX
Energy test level is defined as E
+
+ 10.2 mJ, where
AS
2
tav = avalanche time.
Figure 4. Single-Pulse Avalanche Energy Test Circuit and Waveforms
TYPICAL CHARACTERISTICS
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
0.8
2.5
VDS = VGS
2
ID = 1 mA
1.5
ID = 100 µA
1
0.5
0
−40 −20
On-State Resistance − Ω
ID = 1.4 A
r DS(on) − Static Drain-to-Source
VGS(th) − Gate-to-Source Threshold Voltage − V
GATE-TO-SOURCE THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
0.6
VGS = 10 V
0.4
VGS = 15 V
0.2
0
−40 −20
0
20 40 60 80 100 120 140 160
TJ − Junction Temperature − °C
0
20 40 60 80 100 120 140 160
TJ − Junction Temperature − °C
Figure 5
Figure 6
•
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•
7
SLIS039A − SEPTEMBER 1994 − REVISED SEPTEMBER 1995
TYPICAL CHARACTERISTICS
1
0.9
0.8
0.7
DRAIN CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
5
VGS = 15 V
TJ = 25°C
VGS = 5.6 V
4.5
nVGS = 0.4 V
TJ = 25°C
(unless otherwise
noted
4
0.6
0.5
I D − Drain Current − A
On-State Resistance − Ω
r DS(on) − Static Drain-to-Source
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
DRAIN CURRENT
VGS = 10 V
0.4
0.3
VGS = 15 V
0.2
3.5
3
VGS = 10 V
2.5
VGS = 4 V
2
1.5
1
VGS = 2.8 V
0.5
0.1
0.1
1
ID − Drain Current − A
0
10
0
2
Figure 7
6
8
Figure 8
DRAIN CURRENT
vs
GATE-TO-SOURCE VOLTAGE
DISTRIBUTION OF
FORWARD TRANSCONDUCTANCE
5
75
Total Number of
Units = 2064
VDS = 15 V
ID = 0.7 A
TJ = 25°C
65
60
55
50
TJ = − 40°C
TJ = 25°C
4
I D − Drain Current − A
70
Percentage of Units − %
4
VDS − Drain-to-Source Voltage − V
45
40
35
30
25
20
15
TJ = 75°C
TJ = 125°C
3
TJ = 150°C
2
1
10
0
1.40
1.37
1.34
1.31
1.28
1.25
1.22
1.19
1.16
1.13
1.10
1.07
1.04
5
0
0
1
2
3
4
5
6
7
VGS − Gate-to-Source Voltage − V
gfs − Forward Transconductance − S
Figure 9
8
Figure 10
•
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•
8
SLIS039A − SEPTEMBER 1994 − REVISED SEPTEMBER 1995
TYPICAL CHARACTERISTICS
SOURCE-TO-DRAIN DIODE CURRENT
vs
SOURCE-TO-DRAIN VOLTAGE
CAPACITANCE
vs
DRAIN-TO-SOURCE VOLTAGE
10
250
C − Capacitance − pF
200
175
I SD− Source-to-Drain Diode Current − A
VGS = 0
f = 1 MHz
TJ = 25°C
Ciss @ 0 V = 160 pF
Coss @ 0 V = 216 pF
Crss @ 0 V = 78 pF
225
150
125
Ciss
100
Coss
75
ÁÁ
ÁÁ
ÁÁ
50
Crss
25
0
0
4
8
12 16 20 24 28 32 36
VDS − Drain-to-Source Voltage − V
40
VGS = 0
1
TJ = 75°C
TJ = 125°C
TJ = 25°C
TJ = 150°C
TJ = − 40°C
0.1
0.1
1
VSD − Source-to-Drain Voltage − V
Figure 11
Figure 12
DRAIN-TO-SOURCE VOLTAGE AND
GATE-TO-SOURCE VOLTAGE
vs
GATE CHARGE
REVERSE-RECOVERY TIME
vs
REVERSE di/dt
10
VDD = 20 V
40
8
VDD = 30 V
30
6
20
4
VDD = 48 V
10
2
VDD = 20 V
0
0
0.5
1
VDS = 48 V
VGS = 0
IS = 0.7 A
TJ = 25°C
See Figure 1
260
1.5
2
t rr − Reverse-Recovery Time − ns
50
280
12
ID = 0.7 A
TJ = 25°C
See Figure 3
VGS − Gate-to-Source Voltage − V
VDS − Drain-to-Source Voltage − V
60
10
240
220
200
180
160
D1, D2, and D3
140
120
100
80
60
Z1, Z2, and Z3
40
20
2.5
3
3.5
4
0
0
0
100
200
300
400
500
600
Reverse di/dt − A/µs
Qg − Gate Charge − nC
Figure 13
Figure 14
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•
9
SLIS039A − SEPTEMBER 1994 − REVISED SEPTEMBER 1995
THERMAL INFORMATION
MAXIMUM DRAIN CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
10
TC = 25°C
I D − Maximum Drain Current − A
1 µs†
10 ms†
1 ms†
1
500 µs†
ÁÁ
ÁÁ
RθJP§
RθJA‡
DC Conditions
0.1
0.1
1
10
100
VDS − Drain-to-Source Voltage − V
† Less than 2% duty cycle
‡ Device mounted on FR4 printed-circuit board with no heatsink.
§ Device mounted in intimate contact with infinite heatsink.
Figure 15
MAXIMUM PEAK AVALANCHE CURRENT
vs
TIME DURATION OF AVALANCHE
I AS − Maximum Peak Avalanche Current − A
10
See Figure 4
TC = 25°C
TC = 125°C
1
0.01
0.1
1
tav − Time Duration of Avalanche − ms
Figure 16
10
•
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•
10
SLIS039A − SEPTEMBER 1994 − REVISED SEPTEMBER 1995
THERMAL INFORMATION
D PACKAGE†
JUNCTION-TO-BOARD THERMAL RESISTANCE
vs
PULSE DURATION
100
DC Conditions
RθJB − Junction-to-Board Thermal Resistance −°C/W
d = 0.5
d = 0.2
10
d = 0.1
d = 0.05
d = 0.02
d = 0.01
1
Single Pulse
tc
tw
ID
0
0.1
0.0001
0.001
0.01
0.1
1
10
100
tw − Pulse Duration − s
† Device mounted on 24 in2, 4-layer FR4 printed-circuit board with no heatsink
NOTE A: Z θJB(t) = r(t) RθJB
tw = pulse duration
tc = cycle time
d = duty cycle = tw/tc
Figure 17
•
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•
11
PACKAGE OPTION ADDENDUM
www.ti.com
8-Apr-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
TPIC5303D
OBSOLETE
SOIC
D
Pins Package Eco Plan (2)
Qty
16
TBD
Lead/Ball Finish
Call TI
MSL Peak Temp (3)
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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microcontroller.ti.com
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