TPS7A1601-Q1 TPS7A1633-Q1 TPS7A1650-Q1 www.ti.com SBVS188B – MARCH 2012 – REVISED MAY 2012 60-V, 5-µA IQ, 100-mA, Low-Dropout VOLTAGE REGULATOR With Enable and Power-Good Check for Samples: TPS7A1601-Q1 , TPS7A1633-Q1, TPS7A1650-Q1 FEATURES 1 • • 23 • • • • • • • • • • Qualified for Automotive Applications AEC-Q100 Qualified With the Following Results: – Device Temperature Grade 1: –40°C to 125°C Ambient Operating Temperature Range – Device HBM ESD Classification Level H2 – Device CDM ESD Classification Level C3B Wide Input Voltage Range: 3 V to 60 V Ultralow Quiescent Current: 5 µA Quiescent Current at Shutdown: 1 µA Output Current: 100 mA Low Dropout Voltage: 60 mV at 20 mA Accuracy: 2% Available in: – Fixed Output Voltage: 3.3 V, 5.0 V – Adjustable Version From Approx. 1.2 V to 18.5 V Power-Good With Programable Delay Current-Limit and Thermal Shutdown Protections Stable With Ceramic Output Capactors: • ≥ 2.2 µF Package: High-Thermal-Performance MSOP-8 PowerPAD™ Package APPLICATIONS • • • • High Cell-Count Battery Packs for Power Tools and Other Battery-Powered Microprocessor and Microcontroller Systems Car Audio, Navigation, Infotainment, and Other Automotive Systems Power Supplies for Notebook PCs, Digital TVs, and Private LAN Systems Smoke/CO2 Detectors and Battery-Powered Alarm/Security Systems DGN Package 3-mm ´ 5-mm MSOP-8 PowerPAD Package (Top View) OUT FB/DNC PG GND 1 2 3 4 8 7 6 5 IN DELAY NC EN DESCRIPTION The TPS7A1633-Q1, TPS7A1601-Q1, and TPS7A1650-Q1 ultralow-power, low-dropout (LDO) voltage regulators offer the benefits of ultralow quiescent current, high input voltage, and miniaturized, high-thermal-performance packaging. The TPS7A1633-Q1, TPS7A1601-Q1, and TPS7A1650-Q1 are designed for continuous or sporadic (power backup) battery-powered applications where ultralow quiescent current is critical to extending system battery life. The TPS7A1633-Q1, TPS7A1601-Q1, and TPS7A1650-Q1 offer an enable pin (EN) compatible with standard CMOS logic and an integrated open-drain active-high power-good output (PG) with a user-programmable delay. These pins are intended for use in microcontroller-based, battery-powered applications where power-rail sequencing is required. In addition, the TPS7A1633-Q1, TPS7A1601-Q1, and TPS7A1650-Q1 are ideal for generating a low-voltage supply from multicell solutions ranging from high-cell-count power-tool packs to automotive applications; not only can these devices supply a well-regulated voltage rail, but they can also withstand and maintain regulation during voltage transients. These features translate to simpler and more cost-effective, electrical surge-protection circuitry. 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012, Texas Instruments Incorporated TPS7A1601-Q1 TPS7A1633-Q1 TPS7A1650-Q1 SBVS188B – MARCH 2012 – REVISED MAY 2012 www.ti.com VIN 60 V 12 V t VOUT VIN OUT IN VCC mC2 CIN VEN COUT EN DELAY CDELAY GND EN RPG TPS7A16XX-Q1 PG IO1 VPG mC1 IO3 IO2 Low-Power Microcontroller Rail Sequencing in Automotive Applications Subject to Load-Dump Transient 2 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS7A1601-Q1 TPS7A1633-Q1 TPS7A1650-Q1 TPS7A1601-Q1 TPS7A1633-Q1 TPS7A1650-Q1 www.ti.com SBVS188B – MARCH 2012 – REVISED MAY 2012 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) ORDERABLE PART NUMBER TPS7A1633QDGNRQ1 TPS7A1601QDGNRQ1 TPS7A1650QDGNRQ1 (1) TA –40°C to 125°C PACKAGE VSSOP DGN TOP SIDE SYMBOL STATUS PXYQ PXZQ PYAQ Active Active Active Reel of 2500 For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the device product folder on www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range –40°C ≤ TJ ≤ +125°C (unless otherwise noted). VALUE Voltage Current –0.3 62 V OUT pin to GND pin –0.3 20 V OUT pin to IN pin –62 0.3 V FB pin to GND pin –0.3 3 V FB pin to IN pin –62 0.3 V EN pin to IN pin –62 0.3 V EN pin to GND pin –0.3 62 V PG pin to GND pin –0.3 5.5 V DELAY pin to GND pin –0.3 5.5 UNIT V Internally limited Operating virtual junction, TJ, absolute maximum range (2) –40 150 Storage, Tstg –65 150 °C 2 kV 750 V Human Body Model (HBM) AEC-Q100 Classification Level H2 Electrostatic discharge rating (2) MAX IN pin to GND pin Peak output Temperature (1) MIN Charged Device Model (CDM) AEC-Q100 Classification Level C3B °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolutemaximum rated conditions for extended periods may affect device reliability. Permanent damage does not occur to the part operating within this range, though electrical performance is not guaranteed outside the operating free-air temperature range. THERMAL INFORMATION TPS7A16xxQDGNRQ1 THERMAL METRIC (1) DGN UNIT 8 PINS θJA Junction-to-ambient thermal resistance 66.2 °C/W θJC(top) Junction-to-case(top) thermal resistance 45.9 °C/W θJB Junction-to-board thermal resistance 34.6 °C/W ψJT Junction-to-top characterization parameter 1.9 °C/W ψJB Junction-to-board characterization parameter 34.3 °C/W θJC(bottom) Junction-to-case(bottom) thermal resistance 14.9 °C/W (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS7A1601-Q1 TPS7A1633-Q1 TPS7A1650-Q1 3 TPS7A1601-Q1 TPS7A1633-Q1 TPS7A1650-Q1 SBVS188B – MARCH 2012 – REVISED MAY 2012 www.ti.com ELECTRICAL CHARACTERISTICS At TA= –40°C to 125°C, VIN = VOUT(NOM) + 0.5 V or VIN = 3 V (whichever is greater), VEN = VIN, IOUT = 10 µA, CIN = 1 μF, COUT = 2.2 μF, and FB tied to OUT, unless otherwise noted. TPS7A16xx-Q1 PARAMETER TEST CONDITIONS VIN Input voltage range VREF Internal reference VUVLO Undervoltage lockout threshold MIN TYP 3 TA = 25°C, VFB = VREF, VIN = 3 V, IOUT = 10 μA 1.169 1.193 MAX UNIT 60 V 1.217 V 2.7 V Output voltage range VIN ≥ VOUT(NOM) + 0.5 V VREF 18.5 V Nominal accuracy TA = 25°C, VIN = 3 V, IOUT = 10 μA –2% 2% VOUT Overall accuracy VOUT(NOM) + 0.5 V ≤ VIN ≤ 60 V (1) 10 µA ≤ IOUT ≤ 100 mA –2% 2% VOUT ΔVO(ΔVI) Line regulation 3 V ≤ VIN ≤ 60 V ±1% VOUT ΔVO(ΔIO) Load regulation 10 µA ≤ IOUT ≤ 100 mA ±1% VOUT VDO Dropout voltage ILIM Current limit IGND Ground current ISHDN Shutdown supply current VOUT Feedback current Enable current VEN_HI Enable high-level voltage VEN_LO Enable low- level voltage VIT PG trip threshold VHYS PG trip hysteresis LO LKG 400 mA 3 V ≤ VIN ≤ 60 V, IOUT = 10 µA 5 15 μA IOUT = 100 mA 5 μA –1 0.0 1 µA –1 0.01 1 μA V 0.3 85% 95% VOUT OUT pin floating, VFB decreasing, VIN ≥ VIN_MIN 83% 93% VOUT 4% VOUT VPG= VOUT(NOM) Thermal shutdown temperature TA Operating junction temperature range V OUT pin floating, VFB increasing, VIN ≥ VIN_MIN OUT pin floating, VFB = 80% VREF, IPG= 1mA TSD μA 5.0 1.2 PG leakage current Power-supply rejection ratio mV 0.59 VEN = 0.4 V PG output low voltage PSRR 4 mV 225 101 2.3% DELAY pin current (2) 500 3 V ≤ VIN ≤ 12 V, VIN = VEN IDELAY (1) 265 (2) IEN IPG, 60 VIN = 4.5 V, VOUT(NOM) = 5 V, IOUT = 100 mA VOUT = 90% VOUT(NOM), VIN = 3.0 V I FB VPG, VIN = 4.5 V, VOUT(NOM) = 5 V, IOUT = 20 mA –1 1 VIN = 3 V, VOUT(NOM) = VREF, COUT = 10 μF, f = 100 Hz 0.4 V 1 μA 2 μA 50 dB Shutdown, temperature increasing 170 °C Reset, temperature decreasing 150 °C –40 125 °C Maximum input voltage is limited to 24 V because of the package power dissipation limitations at full load (P ≈ (VIN – VOUT) × IOUT = (24 V – VREF) × 50 mA ≈ 1.14 W). The device is capable of sourcing a maximum current of 50 mA at higher input voltages as long as the power dissipated is within the thermal limits of the package plus any external heatsinking. IFB > 0 flows out of the device. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS7A1601-Q1 TPS7A1633-Q1 TPS7A1650-Q1 TPS7A1601-Q1 TPS7A1633-Q1 TPS7A1650-Q1 www.ti.com SBVS188B – MARCH 2012 – REVISED MAY 2012 DEVICE INFORMATION FUNCTIONAL BLOCK DIAGRAM IN OUT UVLO Pass Device Thermal Shutdown Current Limit Error Amp Enable FB EN PG Power Good Control DELAY TYPICAL APPLICATION CIRCUIT VIN VOUT OUT IN CIN CFF R1 TPS7A1601-Q1 VEN EN COUT RPG FB Where: R1 = R2 VOUT -1 VREF R2 DELAY GND PG VPG CDELAY TPS7A1601-Q1 Circuit as an Adjustable Regulator Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS7A1601-Q1 TPS7A1633-Q1 TPS7A1650-Q1 5 TPS7A1601-Q1 TPS7A1633-Q1 TPS7A1650-Q1 SBVS188B – MARCH 2012 – REVISED MAY 2012 www.ti.com PIN CONFIGURATION DGN PACKAGE MSOP-8 (TOP VIEW) OUT FB/DNC PG GND 1 2 3 4 8 7 6 5 IN DELAY NC EN PIN DESCRIPTIONS TPS7A16xx-Q1 6 NAME NO. DELAY 7 Delay pin. Connect a capacitor to GND to adjust the PG delay time; leave open if the reset function is not needed. DESCRIPTION EN 5 Enable pin. This pin turns the regulator on or off. If VEN ≥ VEN_HI, the regulator is enabled. If VEN ≤ VEN_LO, the regulator is disabled. If not used, the EN pin can be connected to IN. Make sure that VEN ≤ VIN at all times. FB/DNC 2 For the adjustable version (TPS7A1601-Q1), the feedback pin is the input to the control-loop error amplifier. This pin is used to set the output voltage of the device when the regulator output voltage is set by external resistors. For the fixed voltage versions: DO NOT CONNECT to this pin. Do not route this pin to any electrical net, not even GND or IN. GND 4 Ground pin IN 8 Regulator input supply pin. A capacitor > 0.1 µF must be tied from this pin to ground to assure stability. It is recommended to connect a 10-µF ceramic capacitor from IN to GND (as close to the device as possible) to reduce circuit sensitivity to printed-circuit-board (PCB) layout, especially when long input tracer or high source impedances are encountered. NC 6 This pin can be left open or tied to any voltage between GND and IN. OUT 1 Regulator output pin. A capacitor > 2.2 µF must be tied from this pin to ground to assure stability. It is recommended to connect a 10-µF ceramic capacitor from OUT to GND (as close to the device as possible) to maximize ac performance. PG 3 Power-good pin. Open-collector output; leave open or connect to GND if the power-good function is not needed. Thermal pad Solder to printed circuit board (PCB) to enhance thermal performance. Although it can be left floating, it is highly recommended to connect the thermal pad to the GND plane. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS7A1601-Q1 TPS7A1633-Q1 TPS7A1650-Q1 TPS7A1601-Q1 TPS7A1633-Q1 TPS7A1650-Q1 www.ti.com SBVS188B – MARCH 2012 – REVISED MAY 2012 TYPICAL CHARACTERISTICS At TA = –40°C to 125°C, VIN = VOUT(NOM) + 0.5 V or VIN = 3 V (whichever is greater), VEN = VIN, IOUT = 10 µA, CIN = 1 μF, COUT = 2.2 μF, and FB tied to OUT, unless otherwise noted. QUIESCENT CURRENT vs INPUT VOLTAGE SHUTDOWN CURRENT vs INPUT VOLTAGE 50 10 IOUT = 0mA − 40°C + 25°C + 85°C + 105°C + 125°C 30 − 40°C + 25°C + 85°C + 105°C + 125°C 8 7 IQ (µA) IQ (µA) 40 VEN = 0.4V 9 20 6 5 4 3 10 2 1 0 0 10 20 30 40 Input Voltage (V) 50 0 60 0 10 20 Figure 1. GROUND CURRENT vs OUTPUT CURRENT DROPOUT VOLTAGE vs OUTPUT CURRENT − 40°C + 25°C + 85°C + 105°C + 125°C 80 70 800 50 40 600 500 400 30 300 20 200 10 100 10 20 + 105°C + 125°C 700 60 0 − 40°C + 25°C + 85°C 900 VDROP (V) IGND (µA) 60 1000 90 30 40 50 60 70 Output Current (mA) 80 90 0 100 0 20 40 60 Output Current (mA) Figure 3. Figure 4. FEEDBACK VOLTAGE vs INPUT VOLTAGE LINE REGULATION 1.294 80 100 10 − 40°C + 25°C + 85°C + 105°C + 125°C − 40°C + 25°C + 85°C 7.5 + 105°C + 125°C 5 VOUT(NOM) (%) 1.244 VFB (V) 50 Figure 2. 100 0 30 40 Input Voltage (V) 1.194 2.5 0 −2.5 1.144 −5 −7.5 1.094 0 10 20 30 40 Input Voltage (V) Figure 5. Copyright © 2012, Texas Instruments Incorporated 50 60 −10 0 10 20 30 40 Input Voltage (V) 50 60 Figure 6. Submit Documentation Feedback Product Folder Link(s): TPS7A1601-Q1 TPS7A1633-Q1 TPS7A1650-Q1 7 TPS7A1601-Q1 TPS7A1633-Q1 TPS7A1650-Q1 SBVS188B – MARCH 2012 – REVISED MAY 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = –40°C to 125°C, VIN = VOUT(NOM) + 0.5 V or VIN = 3 V (whichever is greater), VEN = VIN, IOUT = 10 µA, CIN = 1 μF, COUT = 2.2 μF, and FB tied to OUT, unless otherwise noted. LOAD REGULATION CURRENT LIMIT vs INPUT VOLTAGE 10 300 − 40°C + 25°C + 85°C 7.5 + 105°C + 125°C 250 200 2.5 ICL (mA) VOUT(NOM) (%) 5 0 −2.5 150 100 − 40°C + 25°C + 85°C + 105°C + 125°C −5 50 −7.5 −10 0 10 20 30 40 50 60 70 Output Current (mA) 80 90 0 100 0 2 4 Figure 7. 10 12 Figure 8. POWER-GOOD THRESHOLD VOLTAGE vs TEMPERATURE ENABLE THRESHOLD VOLTAGE vs TEMPERATURE 95 2.5 93 2 PG Rising 91 VEN (V) VOUTNOM (%) 6 8 Input Voltage (V) 89 87 5 20 35 50 65 Temperature (°C) OFF−TO−ON 1 0.5 PG Falling 85 −40 −25 −10 1.5 80 95 ON−TO−OFF 0 −40 −25 −10 110 125 5 20 35 50 65 Temperature (°C) Figure 9. 80 95 110 125 Figure 10. POWER-SUPPLY REJECTION RATIO OUTPUT SPECTRAL NOISE DENSITY 100 10 90 80 1 Noise (µV/ Hz) PSRR (dB) 70 60 50 40 0.1 30 0.01 20 VIN = 3V VOUT = ~1.2V COUT = 10µF 10 0 10 100 VIN = 3V VOUT = 1.2V COUT = 2.2µF 1k Frequency (Hz) Figure 11. 8 Submit Documentation Feedback 10k 100k 0.001 10 100 1k 10k 100k Frequency (Hz) 1M 10M Figure 12. Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS7A1601-Q1 TPS7A1633-Q1 TPS7A1650-Q1 TPS7A1601-Q1 TPS7A1633-Q1 TPS7A1650-Q1 www.ti.com SBVS188B – MARCH 2012 – REVISED MAY 2012 TYPICAL CHARACTERISTICS (continued) At TA = –40°C to 125°C, VIN = VOUT(NOM) + 0.5 V or VIN = 3 V (whichever is greater), VEN = VIN, IOUT = 10 µA, CIN = 1 μF, COUT = 2.2 μF, and FB tied to OUT, unless otherwise noted. POWER GOOD DELAY VIN (2 V/div) VPG (2 V/div) VIN = 1 V ® 6.5 V IOUT = 1 mA COUT = 10 mF CFF = 0 nF VOUT (1 V/div) Time (5 ms/div) Figure 13. Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS7A1601-Q1 TPS7A1633-Q1 TPS7A1650-Q1 9 TPS7A1601-Q1 TPS7A1633-Q1 TPS7A1650-Q1 SBVS188B – MARCH 2012 – REVISED MAY 2012 www.ti.com THEORY OF OPERATION GENERAL DESCRIPTION The TPS7A16xx-Q1 family of ultralow-power voltage regulators offers the benefit of ultralow quiescent current, high input voltage, and miniaturized, high-thermal-performance packaging. The TPS7A16xx-Q1 are designed for continuous or sporadic (power backup) battery-operated applications where ultralow quiescent current is critical to extending system battery life. ADJUSTABLE VOLTAGE OPERATION The TPS7A1601-Q1 has an output voltage range from 1.194 V to 20 V. The nominal output of the device is set by two external resistors, as shown in Figure 14: VIN IN PG CIN 0.1 mF RPG 1 MW EN CDELAY 0.1 mF OUT R1 3.4 MW DELAY COUT 2.2 mF VOUT 5V FB GND R2 1.07 MW Figure 14. Adjustable Operation R1 and R2 can be calculated for any output voltage range using the formula shown in Equation 1: VOUT R1 = R2 -1 VREF (1) Resistor Selection It is recommended to use resistors in the order of MΩ to keep the overall quiescent current of the system as low as possible (by making the current used by the resistor divider negligible compared to the quiescent current of the device). If greater voltage accuracy is required, take into account the voltage offset contributions as a result of feedback current and use 0.1% tolerance resistors. Table 1 shows the resistor combination to achieve an output for a few of the most common rails using commercially available 0.1% tolerance resistors to maximize nominal voltage accuracy, while adhering to the formula shown in Equation 1. 10 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS7A1601-Q1 TPS7A1633-Q1 TPS7A1650-Q1 TPS7A1601-Q1 TPS7A1633-Q1 TPS7A1650-Q1 www.ti.com SBVS188B – MARCH 2012 – REVISED MAY 2012 Table 1. Selected Resistor Combinations VOUT R1 R2 VOUT/(R1 + R2) « IQ NOMINAL ACCURACY 1.194 V 0Ω ∞ 0 µA ±2% 1.8 V 1.18 MΩ 2.32 MΩ 514 nA ±(2% + 0.14%) 2..5 V 1.5 MΩ 1.37 MΩ 871 nA ±(2% + 0.16%) 3.3 V 2 MΩ 1.13 MΩ 1056 nA ±(2% + 0.35%) 5V 3.4 MΩ 1.07 MΩ 1115 nA ±(2% + 0.39%) 10 V 7.87 MΩ 1.07 MΩ 1115 nA ±(2% + 0.42%) 12 V 14.3 MΩ 1.58 MΩ 755 nA ±(2% + 0.18%) 15 V 42.2 MΩ 3.65 MΩ 327 nA ±(2% + 0.19%) 18 V 16.2 MΩ 1.15 MΩ 1038 nA ±(2% + 0.26%) Close attention must be paid to board contamination when using high-value resistors; board contaminants may significantly impact voltage accuracy. If board cleaning measures cannot be ensured, consider using a fixedvoltage version of the TPS7A16 or using resistors in the order of hundreds or tens of kΩ. CAPACITOR RECOMMENDATIONS Low equivalent-series-resistance (ESR) capacitors should be used for the input, output, and feed-forward capacitors. Ceramic capacitors with X7R and X5R dielectrics are preferred. These dielectrics offer more stable characteristics. Ceramic X7R capacitors offer improved overtemperature performance, while ceramic X5R capacitors are the most cost-effective and are available in higher values. Note that high-ESR capacitors may degrade PSRR. INPUT AND OUTPUT CAPACITOR REQUIREMENTS The TPS7A16xx-Q1 ultralow-power, high-voltage linear regulators achieve stability with a minimum input capacitance of 0.1 µF and output capacitance of 2.2 µF; however, it is recommended to use a 10-µF ceramic capacitor to maximize ac performance. POWER-GOOD The power-good (PG) pin is an open-drain output and can be connected to any 5.5-V or lower rail through an external pullup resistor. When no CDELAY is used, the PG output is high-impedance when VOUT is greater than the PG trip threshold (VIT). If VOUT drops below VIT, the open-drain output turns on and pulls the PG output low. If output voltage monitoring is not needed, the PG pin can be left floating or connected to GND. To ensure proper operation of the power-good feature, maintain VIN ≥ 3 V (VIN_MIN). Power-Good Delay and Delay Capacitor The power-good delay time (tDELAY) is defined as the time period from when VOUT exceeds the PG trip threshold voltage (VIT) to when the PG output is high. This power-good delay time is set by an external capacitor (CDELAY) connected from the DELAY pin to GND; this capacitor is charged from 0 V to ap 1.8 V by the DELAY pin current (IDELAY) once VOUT exceeds the PG trip threshold (VIT). When CDELAY is used, the PG output is high-impedance when VOUT exceeds VIT, and VDELAY exceeds VREF. The power-good delay time can be calculated using: tDELAY = (CDELAY × VREF)/IDELAY. For example, when CDELAY = 10 nF, the PG delay time is approximately 12 ms; that is, (10 nF × 1.193 V)/1 µA = 11.93 ms. FEED-FORWARD CAPACITOR Although a feed-forward capacitor (CFF) from OUT to FB is not needed to achieve stability, it is recommended to use a 0.01-µF feed-forward capacitor to maximize ac performance. TRANSIENT RESPONSE As with any regulator, increasing the size of the output capacitor reduces over/undershoot magnitude but increases the duration of the transient response. Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS7A1601-Q1 TPS7A1633-Q1 TPS7A1650-Q1 11 TPS7A1601-Q1 TPS7A1633-Q1 TPS7A1650-Q1 SBVS188B – MARCH 2012 – REVISED MAY 2012 www.ti.com APPLICATION INFORMATION AUTOMOTIVE APPLICATIONS The TPS7A16xx-Q1 maximum input voltage of 60 V makes it ideal for use in automotive applications where highvoltage transients are present. Events such as load-dump overvoltage (where the battery is disconnected while the alternator is providing current to a load) may cause voltage spikes from 25 V to 60 V. In order to prevent any damage to sensitive circuitry, local transient voltage suppressors can be used to cap voltage spikes to lower, more manageable voltages. The TPS7A16xx-Q1 can be used to simplify and lower costs in such cases. The very high voltage range allows this regulator not only to withstand the voltages coming out of these local transient voltage suppressors, but even replace them, thus lowering system cost and complexity. VIN 60 V 12 V t VOUT VIN OUT IN VCC mC2 CIN VEN COUT EN DELAY CDELAY GND EN RPG TPS7A16XX-Q1 PG IO1 VPG mC1 IO3 IO2 Figure 15. Low-Power Microcontroller Rail Sequencing in Automotive Applications Subjected to LoadDump Transients MULTICELL BATTERY PACKS Currently, battery packs can employ up to a dozen cells in series that, when fully charged, may have voltages of up to 55 V. Internal circuitry in these battery packs is used to prevent overcurrent and overvoltage conditions that may degrade battery life or even pose a safety risk; this internal circuitry is often managed by a low-power microcontroller, such as TI’s MSP430. The microcontroller continuously monitors the battery itself, whether the battery is in use or not. Although this microcontroller could be powered by an intermediate voltage taken from the multicell array, this approach unbalances the battery pack itself, degrading its life or adding cost to implement more complex cell balancing topologies. The best approach to power this microcontroller is to regulate down the voltage from the entire array to discharge every cell equally and prevent any balancing issues. This approach reduces system complexity and cost. TPS7A16xx-Q1 is the ideal regulator for this application because it can handle very high voltages (from the entire multicell array) and has very low quiescent current (to maximize battery life). 12 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS7A1601-Q1 TPS7A1633-Q1 TPS7A1650-Q1 TPS7A1601-Q1 TPS7A1633-Q1 TPS7A1650-Q1 www.ti.com SBVS188B – MARCH 2012 – REVISED MAY 2012 Sensing Up To 42 V + Comparator Cell Balance TPS7A16XX-Q1 Voltage Sensing Microcontroller UART - Figure 16. Protection Based on Low-Power Microcontroller Power From Multicell Battery Packs BATTERY-OPERATED POWER TOOLS High-voltage multicell battery packs support high-power applications, such as power tools, with high current drain when in use, highly intermittent use cycles, and physical separation between battery and motor. In these applications, a microcontroller or microprocessor controls the motor. This microcontroller must be powered with a low-voltage rail coming from the high-voltage, multicell battery pack; as mentioned previously, powering this microcontroller or microprocessor from an intermediate voltage from the multicell array causes battery-pack life degradation or added system complexity because of cell balancing issues. In addition, this microcontroller or microprocessor must be protected from the high-voltage transients because of the motor inductance. The TPS7A16xx-Q1 can be used to power the motor-controlled microcontroller or microprocessor; its low quiescent current maximizes battery shelf life, and its very high-voltage capabilities simplify system complexity by replacing voltage suppression filters, thus lowering system cost. 100 W Transient LDO First Cell Second Cell Last Cell Optional Filter M 0.47 mF MSP430 Microcontroller PWM Figure 17. Low Power Microcontroller Power From Multi-Cell Battery Packs In Power Tools Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS7A1601-Q1 TPS7A1633-Q1 TPS7A1650-Q1 13 TPS7A1601-Q1 TPS7A1633-Q1 TPS7A1650-Q1 SBVS188B – MARCH 2012 – REVISED MAY 2012 www.ti.com LAYOUT PACKAGE MOUNTING Solder pad footprint recommendations for the TPS7A16xx-Q1 are available at the end of this product data sheet and at www.ti.com. BOARD LAYOUT RECOMMENDATIONS TO IMPROVE PSRR AND NOISE PERFORMANCE To improve ac performance such as PSRR, output noise, and transient response, it is recommended that the board be designed with separate ground planes for IN and OUT, with each ground plane connected only at the GND pin of the device. In addition, the ground connection for the output capacitor should connect directly to the GND pin of the device. Equivalent series inductance (ESL) and ESR must be minimized in order to maximize performance and ensure stability. Every capacitor must be placed as close as possible to the device and on the same side of the PCB as the regulator itself. Do not place any of the capacitors on the opposite side of the PCB from where the regulator is installed. The use of vias and long traces is strongly discouraged because they may impact system performance negatively and even cause instability. If possible, and to ensure the maximum performance denoted in this product data sheet, use the same layout pattern used for TPS7A16xx-Q1 evaluation board, available at www.ti.com. Additional Layout Considerations The high impedance of the FB pin makes the regulator sensitive to parasitic capacitances that may couple undesirable signals from nearby components (especially from logic and digital ICs, such as microcontrollers and microprocessors); these capacitively-coupled signals may produce undesirable output voltage transients. In these cases, it is recommended to use a fixed-voltage version of the TPS7A16xx-Q1, or to isolate the FB node by flooding the local PCB area with ground-plane copper to minimize any undesirable signal coupling. THERMAL PROTECTION Thermal protection disables the output when the junction temperature rises to approximately 170°C, allowing the device to cool. When the junction temperature cools to approximately 150°C, the output circuitry is enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage as a result of overheating. Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate heat-spreading area. For reliable operation, junction temperature should be limited to a maximum of 125°C at the worst case ambient temperature for a given application. To estimate the margin of safety in a complete design (including the copper heat-spreading area), increase the ambient temperature until the thermal protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should trigger at least 45°C above the maximum expected ambient condition of the particular application. This configuration produces a worst-case junction temperature of 125°C at the highest expected ambient temperature and worstcase load. The internal protection circuitry of the TPS7A16xx-Q1 has been designed to protect against overload conditions. It was not intended to replace proper heatsinking. Continuously running the TPS7A16xx-Q1 into thermal shutdown degrades device reliability. POWER DISSIPATION The ability to remove heat from the die is different for each package type, presenting different considerations in the PCB layout. The PCB area around the device that is free of other components moves the heat from the device to the ambient air. Using heavier copper increases the effectiveness of removing heat from the device. The addition of plated through-holes to heat dissipating layers also improves the heatsink effectiveness. Power dissipation depends on input voltage and load conditions. Power dissipation (PD) is equal to the product of the output current times the voltage drop across the output pass element, as shown in Equation 2: PD = (VIN - VOUT) IOUT (2) 14 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS7A1601-Q1 TPS7A1633-Q1 TPS7A1650-Q1 TPS7A1601-Q1 TPS7A1633-Q1 TPS7A1650-Q1 www.ti.com SBVS188B – MARCH 2012 – REVISED MAY 2012 SUGGESTED LAYOUT AND SCHEMATIC Layout is a critical part of good power-supply design. There are several signal paths that conduct fast-changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power-supply performance. To help eliminate these problems, the IN pin should be bypassed to ground with a low-ESR ceramic bypass capacitor with X5R or X7R dielectric. It may be possible to obtain acceptable performance with alternative PCB layouts; however, the layout and the schematic have been shown to produce good results and are meant as a guideline. Figure 18 shows the schematic for the suggested layout.Figure 19 and Figure 20 show the top and bottom printed circuit board (PCB) layers for the suggested layout. Figure 18. Schematic for Suggested Layout 1300 mil 2200 mil Figure 19. Suggested Layout: Top Layer Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS7A1601-Q1 TPS7A1633-Q1 TPS7A1650-Q1 15 TPS7A1601-Q1 TPS7A1633-Q1 TPS7A1650-Q1 SBVS188B – MARCH 2012 – REVISED MAY 2012 www.ti.com 1300 mil 2200 mil Figure 20. Suggested Layout: Bottom Layer 16 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS7A1601-Q1 TPS7A1633-Q1 TPS7A1650-Q1 TPS7A1601-Q1 TPS7A1633-Q1 TPS7A1650-Q1 www.ti.com SBVS188B – MARCH 2012 – REVISED MAY 2012 REVISION HISTORY Changes from Revision A (March 2012) to Revision B Page • Changed to AEC-Q100 Qualified With the Following Results .............................................................................................. 1 • Changed 2 orderable part numbers from Preview to Active ................................................................................................. 3 Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS7A1601-Q1 TPS7A1633-Q1 TPS7A1650-Q1 17 PACKAGE OPTION ADDENDUM www.ti.com 29-Jun-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) TPS7A1601QDGNRQ1 ACTIVE MSOPPowerPAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS7A1633QDGNRQ1 ACTIVE MSOPPowerPAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS7A1650QDGNRQ1 ACTIVE MSOPPowerPAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TPS7A1601-Q1, TPS7A1633-Q1, TPS7A1650-Q1 : • Catalog: TPS7A1601, TPS7A1633, TPS7A1650 Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 29-Jun-2012 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 29-Jun-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS7A1601QDGNRQ1 MSOPPower PAD DGN 8 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1 TPS7A1633QDGNRQ1 MSOPPower PAD DGN 8 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1 TPS7A1650QDGNRQ1 MSOPPower PAD DGN 8 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 29-Jun-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS7A1601QDGNRQ1 MSOP-PowerPAD DGN 8 2500 370.0 355.0 55.0 TPS7A1633QDGNRQ1 MSOP-PowerPAD DGN 8 2500 370.0 355.0 55.0 TPS7A1650QDGNRQ1 MSOP-PowerPAD DGN 8 2500 370.0 355.0 55.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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