DATA SHEET MOS INTEGRATED CIRCUIT µPD160061 384-OUTPUT TFT-LCD SOURCE DRIVER (COMPATIBLE WITH 64-GRAY SCALES) DESCRIPTION The µPD160061 is a source driver for TFT-LCD’s capable of dealing with displays with 64-gray scales. Data input is based on digital input configured as 6 bits by 6 dots (2 pixels), which can realize a full-color display of 260,000 colors by output of 64 values γ -corrected by an internal D/A converter and 5-by-2 external power modules. Because the output dynamic range is as large as VSS2 + 0.2 V to VDD2 – 0.2 V, level inversion operation of the LCD’s common electrode is rendered unnecessary. Also, to be able to deal with dot-line inversion, n-line inversion and column line inversion when mounted on a single side, this source driver is equipped with a built-in 6-bit D/A converter circuit whose odd output pins and even output pins respectively output gray scale voltages of differing polarity. Assuring a maximum clock frequency of 65 MHz when driving at 2.7 V, this driver is applicable to XGA-standard TFT-LCD panels and SXGA TFT-LCD panels. FEATURES • • • • • • • • • • • • • CMOS level input (2.3 to 3.6 V) 384 outputs Input of 6 bits (gray-scale data) by 6 dots Capable of outputting 64 values by means of 5-by-2 external power modules (10 units) and a D/A converter (R-DAC) Logic power supply voltage (VDD1): 2.3 to 3.6 V Driver power supply voltage (VDD2): 7.5 to 9.5 V High-speed data transfer: fCLK = 65 MHz MAX. (internal data transfer speed when operating at VDD1 = 2.7 V) 40 MHz MAX. (internal data transfer speed when operating at VDD1 = 2.3 V) Output dynamic range: VSS2 + 0.2 V to VDD2 – 0.2 V Apply for dot-line inversion, n-line inversion and column line inversion Output voltage polarity inversion function (POL) Input data inversion function (capable of controlling by each input port) (POL21, POL22) Apply for heavy load, light load Semi slim-chip shaped ORDERING INFORMATION Part Number Package µPD160061N-xxx TCP (TAB package) µPD160061NL-xxx COF (COF package) Remark The TCP’s/COF’s external shape are customized. To order the required shape, so please contact one of our sales representatives. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. S15843EJ3V0DS00 (3rd edition) Date Published June 2004 NS CP (K) Printed in Japan The mark ★ shows major revised points. 2002 µPD160061 1. BLOCK DIAGRAM STHR R,/L CLK STB STHL VDD1 VSS1 64-bit bidirectional shift register C1 C 2 C 3 - - - - - - - - - - - - - - - - - - - - - - C63 C64 D00 to D05 D10 to D15 D20 to D25 D30 to D35 D40 to D45 D50 to D55 POL21 POL22 SRC LPC HPC Data register POL Latch VDD2 Level shifter VSS2 V0 to V9 D/A converter Voltage follower output -------------------------------S1 S2 S3 S384 Remark /xxx indicates active low signal. 2. RELATIONSHIP BETWEEN OUTPUT CIRCUIT AND D/A CONVERTER S1 V0 : V4 V5 : V9 S2 S383 5 MultiPlexer 6-bit D/A converter 5 POL 2 Data Sheet S15843EJ3V0DS S384 µPD160061 3. PIN CONFIGURATION (Copper foil surface) (µPD160061N-xxx: TCP (TAB package): Face-up/ µPD160061NL-xxx: COF (COF package): Face-down) STHL D55 D54 D53 D52 D51 D50 D45 D44 D43 D42 D41 D40 D35 D34 D33 D32 D31 D30 VDD1 LPC R,/L V9 V8 V7 V6 V5 VDD2 VSS2 V4 V3 V2 V1 V0 HPC VSS1 SRC CLK STB POL POL21 POL22 D25 D24 D23 D22 D21 D20 D15 D14 D13 D12 D11 D10 D05 D04 D03 D02 D01 D00 STHR S384 S383 S382 S381 IC Pad Surface S4 S3 S2 S1 Remark This figure does not specify the TCP or COF package. Data Sheet S15843EJ3V0DS 3 µPD160061 4. PIN FUNCTIONS (1/2) Pin Symbol Pin Name S1 to S384 Driver output D00 to D05 Display data input I/O Description Output The D/A converted 64-gray-scale analog voltage is output. Input The display data is input with a width of 36 bits, viz., the gray scale data (6 bits) by 6 dots (2 D10 to D15 pixels). D20 to D25 DX0: LSB, DX5: MSB D30 to D35 D40 to D45 D50 to D55 R,/L Shift direction control Input These refer to the start pulse I/O pins when driver ICs are connected in cascade. Fetching of display data starts when H is read at the rising edge of CLK. R,/L = H (right shift): STHR input, S1→S384, STHL output R,/L = L (left shift): STHL input, S384→S1, STHR output STHR Right shift start pulse I/O input/output These refer to the start pulse I/O pins when driver ICs are connected in cascade. Fetching of display data starts when H is read at the rising edge of CLK. When right shift: STHR input, STHL output STHL Left shift start pulse When left shift: STHL input, STHR output input/output A high level should be input as the pulse of one cycle of the clock signal. If the start pulse input is more than 2CLK, the first 1CLK of the high-level input is valid. CLK Shift clock input Input Refers to the shift register’s shift clock input. The display data is incorporated into the data register at the rising edge. At the rising edge of the 64th after the start pulse input, the start pulse output reaches the high level, thus becoming the start pulse of the next-level driver. If 66th clock pulses are input after input of the start pulse, input of display data is halted automatically. The contents of the shift register are cleared at the STB’s rising edge. STB Latch input Input The contents of the data register are transferred to the latch circuit at the rising edge. And, at the falling edge of the STB, the gray scale voltage is supplied to the driver. When STB = H period, driver output level is Hi-Z (High impedance). It is necessary to ensure input of one pulse per horizontal period. POL Polarity input Input POL = L: The S2n–1 output uses V0 to V4 as the reference supply. The S2n output uses V5 to V9 as the reference supply. POL = H: The S2n–1 output uses V5 to V9 as the reference supply. The S2n output uses V0 to V4 as the reference supply. S2n-1 indicates the odd output, and S2n indicates the even output. Input of the POL signal is allowed the setup time (tPOL-STB) with respect to STB’s rising edge. POL21, Data inversion input Input Data inversion can invert when display data is loaded. POL21: D00 to D05, D10 to D15, D20 to D25, data inversion can invert display data POL22 POL22: D30 to D35, D40 to D45, D50 to D55, data inversion can invert display data POL21, POL22 = H: Data inversion loads display data after inverting it. POL21, POL22 = L: Data inversion does not invert input data. LPC, Bias current control HPC input Input Please refer to panel loads and driver power supply voltage (VDD2), when set up these pins. Refer to 10. BIAS CURRENT CONTROL BY LPC AND HPC. LPC pin is pulled down to the VSS1 inside the IC, HPC pin is pulled up to the VDD1 inside the IC. 4 Data Sheet S15843EJ3V0DS µPD160061 (2/2) Pin Symbol SRC Pin Name High driving time I/O Description Input This pin is set up to high drive time of the output amplifier. Please decide the pin setting refer to panel loads and one horizontal period. SRC pin is pulled up to the VDD1 inside the IC. control SRC = H or open: High drive time 64 CLK (Normally period mode) SRC = L: High drive time 128 CLK (Long time mode) Refer to 9. SRC AND HIGH DRIVE TIME. V0 to V9 γ -corrected power − supplies Input the γ -corrected power supplies from outside by using operational amplifier. Make sure to maintain the following relationships. During the gray scale voltage output, be sure to keep the gray scale level power supply at a constant level. VDD2 − 0.2 V ≥ V0 > V1 > V2 > V3 > V4 ≥ 0.5 VDD2 VDD2 − 0.3 V ≥ > V5 > V6 > V7 > V8 > V9 ≥ VSS2 + 0.2 V VDD1 Logic power supply − 2.3 to 3.6 V VDD2 Driver power supply − 7.5 to 9.5 V VSS1 Logic ground − Grounding VSS2 Driver ground − Grounding Cautions 1. The power start sequence must be VDD1, logic input, and VDD2 & V0 to V9 in that order. Reverse this sequence to shut down. 2. To stabilize the supply voltage, please be sure to insert a 0.1 µF bypass capacitor between VDD1 to VSS1 and VDD2 to VSS2. Furthermore, for increased precision of the D/A converter, insertion of a bypass capacitor of about 0.01 µF is also recommended between the γ -corrected power supply terminals (V0, V1, V2,....., V9) and VSS. Data Sheet S15843EJ3V0DS 5 µPD160061 5. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE The µPD160061 incorporates a 6-bit D/A converter whose odd output pins and even output pins output respectively gray scale voltages of differing polarity with respect to the LCD’s counter electrode voltage. The D/A converter consists of ladder resistors and switches. The ladder resistors (r0 to r62) are designed so that the ratio of LCD panel γ-compensated voltages to V0’ to V63’ and V0” to V63” is almost equivalent, resistor ratio is shown in Figure 5−2. For the 2 sets of five γ-compensated power supplies, V0 to V4 and V5 to V9, respectively, input gray scale voltages of the same polarity with respect to the common voltage. When fine-gray scale voltage precision is not necessary, there is no need to connect a voltage follower circuit to the γcompensated power supplies V1 to V3 and V6 to V8. Figure 5–1 shows the relationship between the driving voltages such as liquid-crystal driving voltages VDD2 and VSS2, common electrode potential VCOM, and γ -corrected voltages V0 to V9 and the input data. Be sure to maintain the voltage relationships of below. VDD2 – 0.2 V ≥ V0 > V1 > V2 > V3 > V4 ≥ 0.5 VDD2 0.5 VDD2 – 0.3 V ≥ V5 > V6 > V7 > V8 > V9 > VSS2 + 0.2 V Figures 5–2 indicates γ -corrected voltages and ladder resistors ratio. Figures 5–3 indicates the relationship between the input data and output voltage. Figure 5–1. Relationship between Input Data and γ -corrected Power Supplies VDD2 0.2 V V0 16 V1 16 V2 16 V3 15 V4 0.5 V DD2 Split interval 0.3 V V5 15 V6 16 V7 16 V8 16 V9 0.2 V VSS2 00 6 10 20 Input data (HEX.) Data Sheet S15843EJ3V0DS 30 3F µPD160061 Figure 5–2. γ -corrected Voltages and Ladder Resistors Ratio V0 V0’ V5 r0 V63’’ r62 V1’ V62’’ r61 r1 V61’’ V2’ r60 r2 V60’’ V3’ r59 r3 r49 r14 V49’’ V15’ r48 r15 V16’ V1 V48’’ V6 r47 r16 V17’ V47’’ r46 r17 r46 r17 V47’ V17’’ r47 r16 V48’ V3 V16’’ V8 r48 r15 V49’ V15’’ r49 r14 r2 r60 V2’’ V61’ r1 r61 V62’ V1’’ r0 r62 V4 V63’ V9 V0’’ rn r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 r32 r33 r34 r35 r36 r37 r38 r39 r40 r41 r42 r43 r44 r45 r46 r47 r48 r49 r50 r51 r52 r53 r54 r55 r56 r57 r58 r59 r60 r61 r62 Ratio 8.5 7.5 7.0 6.5 6.0 5.5 5.5 5.0 5.0 4.0 4.0 3.5 3.5 3.5 3.0 3.0 3.0 2.5 2.5 2.5 2.0 2.0 2.0 1.5 1.5 1.5 1.5 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.5 1.5 1.5 2.0 2.0 2.5 2.5 3.0 5.0 8.0 Value (TYP.) 800 750 700 650 600 550 550 500 500 400 400 350 350 350 300 300 300 250 250 250 200 200 200 150 150 150 150 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 150 150 150 200 200 250 250 300 500 800 Cautions 1. There is no connection between V4 and V5 terminal in the IC. 2. The resistance ratio is a relative ratio in the case of setting the resistance minimum value to 1. Data Sheet S15843EJ3V0DS 7 µPD160061 Figure 5–3. Relationship between Input Data and Output Voltage (POL21, POL22 = L) Output Voltage 1: VDD2 – 0.2 V ≥ V0 > V1 > V2 > V3 > V4 ≥ 0.5 VDD2 Output Voltage 2: 0.5 VDD2 – 0.3 V ≥ V5 > V6 > V7 > V8 > V9 ≥ VSS2 + 0.2 V 8 Input Data 00H 01H V0' V1' Output Voltage 1 V0 V1+(V0-V1)× 7250 / 8050 V0'' V1'' Output Voltage 2 V9 V9+(V8-V9)× 800 / 8050 02H V2' V1+(V0-V1)× 6500 / 8050 V2'' V9+(V8-V9)× 1550 / 8050 03H V3' V1+(V0-V1)× 5800 / 8050 V3'' V9+(V8-V9)× 2250 / 8050 04H V4' V1+(V0-V1)× 5150 / 8050 V4'' V9+(V8-V9)× 2900 / 8050 05H V5' V1+(V0-V1)× 4550 / 8050 V5'' V9+(V8-V9)× 3500 / 8050 06H V6' V1+(V0-V1)× 4000 / 8050 V6'' V9+(V8-V9)× 4050 / 8050 07H V7' V1+(V0-V1)× 3450 / 8050 V7'' V9+(V8-V9)× 4600 / 8050 08H V8' V1+(V0-V1)× 2950 / 8050 V8'' V9+(V8-V9)× 5100 / 8050 09H V9' V1+(V0-V1)× 2450 / 8050 V9'' V9+(V8-V9)× 5600 / 8050 0AH V10' V1+(V0-V1)× 2050 / 8050 V10'' V9+(V8-V9)× 6000 / 8050 0BH V11' V1+(V0-V1)× 1650 / 8050 V11'' V9+(V8-V9)× 6400 / 8050 0CH V12' V1+(V0-V1)× 1300 / 8050 V12'' V9+(V8-V9)× 6750 / 8050 0DH V13' V1+(V0-V1)× 950 / 8050 V13'' V9+(V8-V9)× 7100 / 8050 0EH V14' V1+(V0-V1)× 600 / 8050 V14'' V9+(V8-V9)× 7450 / 8050 0FH V15' V1+(V0-V1)× 300 / 8050 V15'' V9+(V8-V9)× 7750 / 8050 10H V16' V1 V16'' V8 11H V17' V2+(V1-V2)× 2450 / 2750 V17'' V8+(V7-V8)× 300 / 2750 12H V18' V2+(V1-V2)× 2200 / 2750 V18'' V8+(V7-V8)× 550 / 2750 13H V19' V2+(V1-V2)× 1950 / 2750 V19'' V8+(V7-V8)× 800 / 2750 14H V20' V2+(V1-V2)× 1700 / 2750 V20'' V8+(V7-V8)× 1050 / 2750 15H V21' V2+(V1-V2)× 1500 / 2750 V21'' V8+(V7-V8)× 1250 / 2750 16H V22' V2+(V1-V2)× 1300 / 2750 V22'' V8+(V7-V8)× 1450 / 2750 17H V23' V2+(V1-V2)× 1100 / 2750 V23'' V8+(V7-V8)× 1650 / 2750 18H V24' V2+(V1-V2)× 950 / 2750 V24'' V8+(V7-V8)× 1800 / 2750 19H V25' V2+(V1-V2)× 800 / 2750 V25'' V8+(V7-V8)× 1950 / 2750 1AH V26' V2+(V1-V2)× 650 / 2750 V26'' V8+(V7-V8)× 2100 / 2750 1BH V27' V2+(V1-V2)× 500 / 2750 V27'' V8+(V7-V8)× 2250 / 2750 1CH V28' V2+(V1-V2)× 400 / 2750 V28'' V8+(V7-V8)× 2350 / 2750 1DH V29' V2+(V1-V2)× 300 / 2750 V29'' V8+(V7-V8)× 2450 / 2750 1EH V30' V2+(V1-V2)× 200 / 2750 V30'' V8+(V7-V8)× 2550 / 2750 1FH V31' V2+(V1-V2)× 100 / 2750 V31'' V8+(V7-V8)× 2650 / 2750 20H V32' V2 V32'' V7 21H V33' V3+(V2-V3)× 1500 / 1600 V33'' V7+(V6-V7)× 100 / 1600 22H V34' V3+(V2-V3)× 1400 / 1600 V34'' V7+(V6-V7)× 200 / 1600 23H V35' V3+(V2-V3)× 1300 / 1600 V35'' V7+(V6-V7)× 300 / 1600 24H V36' V3+(V2-V3)× 1200 / 1600 V36'' V7+(V6-V7)× 400 / 1600 25H V37' V3+(V2-V3)× 1100 / 1600 V37'' V7+(V6-V7)× 500 / 1600 26H V38' V3+(V2-V3)× 1000 / 1600 V38'' V7+(V6-V7)× 600 / 1600 27H V39' V3+(V2-V3)× 900 / 1600 V39'' V7+(V6-V7)× 700 / 1600 28H V40' V3+(V2-V3)× 800 / 1600 V40'' V7+(V6-V7)× 800 / 1600 29H V41' V3+(V2-V3)× 700 / 1600 V41'' V7+(V6-V7)× 900 / 1600 2AH V42' V3+(V2-V3)× 600 / 1600 V42'' V7+(V6-V7)× 1000 / 1600 2BH V43' V3+(V2-V3)× 500 / 1600 V43'' V7+(V6-V7)× 1100 / 1600 2CH V44' V3+(V2-V3)× 400 / 1600 V44'' V7+(V6-V7)× 1200 / 1600 2DH V45' V3+(V2-V3)× 300 / 1600 V45'' V7+(V6-V7)× 1300 / 1600 2EH V46' V3+(V2-V3)× 200 / 1600 V46'' V7+(V6-V7)× 1400 / 1600 2FH V47' V3+(V2-V3)× 100 / 1600 V47'' V7+(V6-V7)× 1500 / 1600 30H V48' V3 V48'' V6 31H V49' V4+(V3-V4)× 3350 / 3450 V49'' V6+(V5-V6)× 100 / 3450 32H V50' V4+(V3-V4)× 3250 / 3450 V50'' V6+(V5-V6)× 200 / 3450 33H V51' V4+(V3-V4)× 3150 / 3450 V51'' V6+(V5-V6)× 300 / 3450 34H V52' V4+(V3-V4)× 3050 / 3450 V52'' V6+(V5-V6)× 400 / 3450 35H V53' V4+(V3-V4)× 2950 / 3450 V53'' V6+(V5-V6)× 500 / 3450 36H V54' V4+(V3-V4)× 2800 / 3450 V54'' V6+(V5-V6)× 650 / 3450 37H V55' V4+(V3-V4)× 2650 / 3450 V55'' V6+(V5-V6)× 800 / 3450 38H V56' V4+(V3-V4)× 2500 / 3450 V56'' V6+(V5-V6)× 950 / 3450 39H V57' V4+(V3-V4)× 2300 / 3450 V57'' V6+(V5-V6)× 1150 / 3450 3AH V58' V4+(V3-V4)× 2100 / 3450 V58'' V6+(V5-V6)× 1350 / 3450 3BH V59' V4+(V3-V4)× 1850 / 3450 V59'' V6+(V5-V6)× 1600 / 3450 3CH V60' V4+(V3-V4)× 1600 / 3450 V60'' V6+(V5-V6)× 1850 / 3450 3DH 3EH V61' V62' V4+(V3-V4)× V4+(V3-V4)× 1300 / 800 / 3450 3450 V61'' V62'' V6+(V5-V6)× V6+(V5-V6)× 2150 2650 / / 3450 3450 3FH V63' V4 V63'' V5 Data Sheet S15843EJ3V0DS µPD160061 6. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT PIN Data format : 6 bits x 2 RGBs (6 dots) Input width : 36 bits (2-pixel data) (1) R,/L = H (Right shift) Output S1 S2 S3 S4 ... S383 S384 Data D00 to D05 D10 to D15 D20 to D25 D30 to D35 ... D40 to D45 D50 to D55 (2) R,/L = L (Left shift) Output S1 S2 S3 S4 ... S383 S384 Data D00 to D05 D10 to D15 D20 to D25 D30 to D35 ... D40 to D45 D50 to D55 Note Note S2n–1 S2n L V0 to V4 V5 to V9 H V5 to V9 V0 to V4 POL Note S2n–1 (Odd output), S2n (Even output) Data Sheet S15843EJ3V0DS 9 µPD160061 7. RELATIONSHIP BETWEEN STB CLK AND OUTPUT WAVEFORM Figure 7–1. Input Circuit Block Diagram Output AMP. - DAC + SW1 Sn (VX) VAMP(IN) Figure 7–2. Output Circuit Timing Waveform [1] [1'] CLK tSTB-CLK STB SW1: OFF VAMP(IN) Sn(VX) Hi-Z STB = H is loaded with the rising edge of CLK[1]. However, when not satisfying the specification of fSTB-CLK, STB = H is loaded with the rising edge of the next CLK[1′]. Latch operation of display data is completed with the falling edge of the next CLK which loaded STB = H. Therefore, in order to complete latch operation of display data, it is necessary to input at least 2 CLK in STB = H period. Besides, after loading STB=H to the timing of [1], it is necessary to continue inputting CLK. 10 Data Sheet S15843EJ3V0DS µPD160061 8. RELATIONSHIP BETWEEN STB, POL AND OUTPUT WAVEFORM When the STB is high level, all outputs became Hi-Z and the gray-scale voltage is output to the LCD in synchronization with the falling edge of STB. Therefore, high drive time of the output amplifier as below is determined by the CLK number of the required SRC pin setting. Be sure to avoid using such as extremely changing the CLK frequency (ex. CLK stop). STB High drive time Inside bias current High drive time High drive time POL V0 - V4 V5 - V9 V5 - V9 V5 - V9 V0 - V4 V0 - V4 Vx (odd output) Vx (even output) Hi-Z Hi-Z Hi-Z 9. SRC AND HIGH DRIVE TIME The µPD160061 can control high drive time of the output amplifier by SRC pin logic (refer to below figure). SRC = H or open (high drive time: standard mode): High drive time (PWhp) of the output amplifier is in 64 CLK period from falling edge of the STB. SRC = L (high drive time: long-term mode): High drive time (PWhp) of the output amplifier is in 128 CLK period from falling edge of the STB. STB CLK PWhp Inside bias current We recommend a thorough simulation of the output amplifier in advance when set the SRC pin. Data Sheet S15843EJ3V0DS 11 µPD160061 10. BIAS CURRENT CONTROL BY LPC AND HPC The µPD160061 can control the bias current of the output amplifier in high drive period and low drive period. Bias Current ★ LPC HPC High H L Middle L or open L Normal L or open H or open Low H H or open Panel Load Heavy Light We recommend a thorough simulation of the output amplifier in advance, when set the LPC and HPC pins. Refer to the table below for the example of the combination of setting level and panel load, with driver part supply voltage. Example of Condition Example 1 Example 2 Example 3 12 LPC HPC Load: RL = 5 kΩ, CL = 75 pF L or open L Driver part supply voltage: VDD2 = 7.5 V Bias current mode: Middle Load: RL = 5 kΩ, CL = 75 pF L or open Driver part supply voltage: VDD2 = 9.0 V Bias current mode: Normal H or open Load: RL = 40 kΩ, CL = 80 pF H Driver part supply voltage: VDD2 = 9.0 V Bias current mode: High Data Sheet S15843EJ3V0DS L SRC H or open H or open L µPD160061 11. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25°C, VSS1 = VSS2 = 0 V) Parameter Symbol Rating Unit Logic Part Supply Voltage VDD1 –0.5 to +4.0 V Driver Part Supply Voltage VDD2 –0.5 to +10.0 V Logic Part Input Voltage VI1 –0.5 to VDD1 + 0.5 V Driver Part Input Voltage VI2 –0.5 to VDD2 + 0.5 V Logic Part Output Voltage VO1 –0.5 to VDD1 + 0.5 V Driver Part Output Voltage VO2 –0.5 to VDD2 + 0.5 V Operating Ambient Temperature TA –10 to +75 °C Storage Temperature Tstg –55 to +125 °C Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Recommended Operating Range (TA = –10 to +75°C, VSS1 = VSS2 = 0 V) Parameter Symbol Condition MIN. TYP. MAX. Unit 3.6 V 9.5 V Logic Part Supply Voltage VDD1 2.3 Driver Part Supply Voltage VDD2 7.5 High-Level Input Voltage VIH 0.7 VDD1 VDD1 V Low-Level Input Voltage VIL 0 0.3 VDD1 V γ -Corrected Voltage V0 to V4 7.5 V ≤ VDD1 ≤ 9.5 V 0.5 VDD2 VDD2 – 0.2 V V5 to V9 7.5 V ≤ VDD1 < 8.5 V 0.2 0.5 VDD2 – 0.3 V 8.5 V ≤ VDD1 ≤ 9.5 V 0.2 0.5 VDD2 V 0.2 VDD2 – 0.2 V 2.3 V ≤ VDD1 < 2.7 V 40 MHz 2.7 V ≤ VDD1 ≤ 3.6 V 65 MHz Driver Part Output Voltage VO Clock Frequency fCLK Data Sheet S15843EJ3V0DS 8.5 13 µPD160061 Electrical Characteristics (TA = –10 to +75°C, VDD1 = 2.3 to 3.6 V, VDD2 = 7.5 to 9.5 V, VSS1 = VSS2 = 0 V) Parameter Symbol Input Leak Current IIL MAX. Unit Except LPC, HPC, SRC Condition MIN. ±1.0 µA LPC, HPC, SRC ±150 µA 0.1 V High-Level Output Voltage VOH STHR (STHL), IOH = 0 mA Low-Level Output Voltage VOL STHR (STHL), IOL = 0 mA γ -Corrected Resistance Rγ V0 to V4 = V5 to V9 = 4.0 V, VDD2 = 8.5 V Driver Output Current IVOH VDD2 = 8.0 V, VX = 7.0 V, VOUT = 6.5 V Note1 Note1 TYP. VDD1 – 0.1 7.9 V 15.8 23.7 kΩ – 20 µA µA IVOL VDD2 = 8.0 V, VX = 1.0 V, VOUT = 1.5 V Output Voltage Deviation ∆VO TA = 25°C, ±10 ±20 mV Output Swing Difference ∆VP–P VDD1 = 3.3 V, VDD2 = 8.5 V, ±3 ±15 mV IDD1 VDD1 4 12 mA IDD22 VDD2, with no load 3.5 8 mA Deviation Logic Part Dynamic Current Consumption VOUT = 2.0 V, 4.25 V, 6.5 V Note2, 3, 4 Driver Part Dynamic Current Consumption 20 Note2, 4 Notes 1. VX refers to the output voltage of analog output pins S1 to S384. VOUT refers to the voltage applied to analog output pins S1 to S384. 2. Specified at fSTB = 65 kHz and fCLK = 54 MHz. 3. The TYP. values refer to an all black or all white input pattern. The MAX. value refers to the measured values in the dot checkerboard input pattern. 4. Refers to the current consumption per driver when cascades are connected under the assumption of XGA single-sided mounting (8 units). Switching Characteristics (TA = –10 to +75°C, VDD1 = 2.3 to 3.6 V, VDD2 = 7.5 to 9.5 V, VSS1 = VSS2 = 0 V) Parameter Symbol Start Pulse Delay Time tPLH1 tPLH1 Driver Output Delay Time ★ Input Capacitance Condition MIN. TYP. MAX. Unit ns CL = 15 pF, 2.3 V ≤ VDD1 < 2.7 V 20 CL = 10 pF, 2.7 V ≤ VDD1 ≤ 3.6 V 10.5 ns CL = 10 pF, 2.3 V ≤ VDD1 < 2.7 V 20 ns CL = 10 pF, 2.7 V ≤ VDD1 ≤ 3.6 V 10.5 ns tPLH2 CL = 75 pF, RL = 5 kΩ, 5 µs tPLH3 LPC = L or open, 8 µs tPHL2 HPC = H or open, 5 µs tPHL3 SRC = H or open 8 µs CI1 Logic input of exclude STHR (STHL), 10 pF 5 pF TA = 25°C STHR (STHL), TA = 25°C CI2 <Measurement condition> RLn = 1 kΩ, CLn = 15 pF The measurement point RL1 RL2 RL3 RL4 RL5 Output CL1 CL2 CL3 GND 14 Data Sheet S15843EJ3V0DS CL4 CL5 µPD160061 Timing Requirements (TA = –10 to +75°C, VDD1 = 2.3 to 3.6 V, VSS1 = 0 V, tr = tf = 5.0 ns) Parameter Clock Pulse Width Clock Pulse High Period Clock Pulse Low Period Symbol PWCLK PWCLK(H) PWCLK(L) Condition MIN. TYP. MAX. Unit 2.3 V ≤ VDD1 < 2.7 V 25 ns 2.7 V ≤ VDD1 ≤ 3.6 V 15 ns 2.3 V ≤ VDD1 < 2.7 V 6 ns 2.7 V ≤ VDD1 ≤ 3.6 V 4 ns 2.3 V ≤ VDD1 < 2.7 V 6 ns 2.7 V ≤ VDD1 ≤ 3.6 V 4 ns Data Setup Time tSETUP1 4 ns Data Hold Time tHOLD1 0 ns Start Pulse Setup Time tSETUP2 4 ns Start Pulse Hold Time tHOLD2 0 ns POL21, POL22 Setup Time tSETUP3 4 ns POL21, POL22 Hold Time tHOLD3 0 ns STB Pulse Width PWSTB 2 CLK Last Data Timing tLDT 2 CLK STB-CLK Time tSTB -CLK 9 ns Time Between STB and Start Pulse tSTB-STH STB ↑ → STHR(STHL) ↑ 2 CLK POL-STB Time tPOL-STB POL ↑ or ↓ → STB ↑ –5 ns STB-POL Time tSTB-POL STB ↓ → POL ↓ or ↑ 6 ns STB ↑→ CLK ↑ Remark Unless otherwise specified, the input level is defined to be VIH = 0.7 VDD1, VIL = 0.3 VDD1. Data Sheet S15843EJ3V0DS 15 PW CLK(H) 1 tr 2 tf V DD1 90% 2 1 CLK 3 64 65 66 10% t SETUP2 t HOLD2 V DD1 STHR (1st Dr.) V SS1 t SETUP1 D n0 to D n5 INVALID t HOLD1 D1 to D6 D7 to D12 t SETUP3 Data Sheet S15843EJ3V0DS POL21, POL22 V SS1 t STB-CLK t STB-STH D373 to D378 D 379 to D384 D385 to D390 V DD1 Last Data INVALID D1 to D6 D 7 to D12 V SS1 t HOLD3 V DD1 INVALID INVALID V SS1 tPLH1 V DD1 STHL (1st Dr.) V SS1 t LDT PW STB V DD1 STB V SS1 t STB-POL t POL-STB V DD1 POL V SS1 t PLH3 Hi-Z t PLH2 SWITCHING CHARACTERISTICS WAVEFORM (R,/L = H) PWCLK Unless otherwise specified, the input level is defined to be VIH = 0.7 VDD1, VIL = 0.3 VDD1. 16 PW CLK(L) Target Voltage: + − 10% Sn (VX) Target Voltage: + − 2% t PHL3 µPD160061 t PHL2 µPD160061 12. RECOMMENDED MOUNTING CONDITIONS The following conditions must be met for mounting conditions of the µPD160061. For more details, refer to the Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html). Please consult with our sales offices in case other mounting process is used, or in case the mounting is done under different conditions. µ PD160061N - ×××: TCP (TAB package) Mounting Condition Thermocompression Mounting Method Soldering Condition Heating tool 300 to 350°C, heating for 2 to 3 seconds, pressure 100 g (per solder) 2 ACF Temporary bonding 70 to 100°C, pressure 3 to 8 kg/cm , time 3 to 5 (Adhesive Conductive seconds. Film) Real bonding 165 to 180°C, pressure 25 to 45 kg/cm , time 30 to 40 2 seconds. (When using the anisotropy conductive film SUMIZAC1003 of Sumitomo Bakelite, Ltd.) Caution To find out the detailed conditions for mounting the ACF part, please contact the ACF manufacturing company. Be sure to avoid using two or more mounting methods at a time. Data Sheet S15843EJ3V0DS 17 µPD160061 NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. 18 Data Sheet S15843EJ3V0DS