NEC UPD160061AN

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD160061A
384-OUTPUT TFT-LCD SOURCE DRIVER
(COMPATIBLE WITH 64-GRAY SCALES)
DESCRIPTION
The µPD160061A is a source driver for TFT-LCDs capable of dealing with displays with 64-gray scales. Data input is
based on digital input configured as 6 bits by 6 dots (2 pixels), which can realize a full-color display of 260,000 colors by
output of 64 values γ -corrected by an internal D/A converter and 5-by-2 external power modules. Because the output
dynamic range is as large as VSS2 + 0.2 V to VDD2 – 0.2 V, level inversion operation of the LCD’s common electrode is
rendered unnecessary. Also, to be able to deal with dot-line inversion, n-line inversion and column line inversion when
mounted on a single side, this source driver is equipped with a built-in 6-bit D/A converter circuit whose odd output pins
and even output pins respectively output gray scale voltages of differing polarity. Assuring a maximum clock frequency of
65 MHz when driving at 2.7 V, this driver is applicable to XGA-standard TFT-LCD panels and SXGA TFT-LCD panels.
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
CMOS level input (2.3 to 3.6 V)
384 outputs
Input of 6 bits (gray-scale data) by 6 dots
Capable of outputting 64 values by means of 5-by-2 external power modules (10 units) and a D/A converter (R-DAC)
Logic power supply voltage (VDD1): 2.3 to 3.6 V
Driver power supply voltage (VDD2): 7.5 to 9.5 V
High-speed data transfer: fCLK = 65 MHz MAX. (internal data transfer speed when operating at VDD1 = 2.7 V)
40 MHz MAX. (internal data transfer speed when operating at VDD1 = 2.3 V)
Output dynamic range: VSS2 + 0.2 V to VDD2 – 0.2 V
Apply for dot-line inversion, n-line inversion and column line inversion
Output voltage polarity inversion function (POL)
Input data inversion function (capable of controlling by each input port) (POL21, POL22)
Apply for heavy load, light load
Semi slim-chip shaped
ORDERING INFORMATION
Part Number
Package
µPD160061AN-xxx
TCP (TAB package)
µPD160061ANL-xxx
COF (COF package)
Remark
The TCP’s external shape is customized. To order the required shape, so please contact one of our sales
representatives.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. S16041EJ2V0DS00 (2nd edition)
Date Published July 2003 NS CP (K)
Printed in Japan
The mark ★ shows major revised points.
2003
µPD160061A
1. BLOCK DIAGRAM
STHR
R,/L
CLK
STB
STHL
VDD1
VSS1
64-bit bidirectional shift register
C1 C 2 C 3
- - - - - - - - - - - - - - - - - - - - - - C63 C64
D00 to D05
D10 to D15
D20 to D25
D30 to D35
D40 to D45
D50 to D55
POL21
POL22
SRC
LPC
HPC
Data register
POL
Latch
VDD2
Level shifter
VSS2
V0 to V9
D/A converter
Voltage follower output
-------------------------------S1
S2
S3
S384
Remark /xxx indicates active low signal.
2. RELATIONSHIP BETWEEN OUTPUT CIRCUIT AND D/A CONVERTER
S1
V0
:
V4
V5
:
V9
S2
S383
5
MultiPlexer
6-bit D/A converter
5
POL
2
Data Sheet S16041EJ2V0DS
S384
µPD160061A
3. PIN CONFIGURATION (Copper foil surface: Face-up)
(µPD160061AN-xxx: TCP (TAB package) / µPD160061ANL-xxx: COF (COF package))
STHL
D55
D54
D53
D52
D51
D50
D45
D44
D43
D42
D41
D40
D35
D34
D33
D32
D31
D30
VDD1
LPC
R,/L
V9
V8
V7
V6
V5
VDD2
VSS2
V4
V3
V2
V1
V0
HPC
VSS1
SRC
CLK
STB
POL
POL21
POL22
D25
D24
D23
D22
D21
D20
D15
D14
D13
D12
D11
D10
D05
D04
D03
D02
D01
D00
STHR
S384
S383
S382
S381
IC Pad Surface
S4
S3
S2
S1
Remark This figure does not specify the TCP or COF package.
Data Sheet S16041EJ2V0DS
3
µPD160061A
4. PIN FUNCTIONS
(1/2)
Pin Symbol
Pin Name
S1 to S384
Driver output
D00 to D05
Display data input
I/O
Description
Output The D/A converted 64-gray-scale analog voltage is output.
Input
The display data is input with a width of 36 bits, viz., the gray scale data (6 bits) by 6 dots (2
D10 to D15
pixels).
D20 to D25
DX0: LSB, DX5: MSB
D30 to D35
D40 to D45
D50 to D55
R,/L
Shift direction control
Input
These refer to the start pulse I/O pins when driver ICs are connected in cascade.
Fetching of display data starts when H is read at the rising edge of CLK.
R,/L = H (right shift): STHR input, S1→S384, STHL output
R,/L = L (left shift): STHL input, S384→S1, STHR output
STHR
Right shift start pulse
I/O
input/output
These refer to the start pulse I/O pins when driver ICs are connected in cascade.
Fetching of display data starts when H is read at the rising edge of CLK.
When right shift: STHR input, STHL output
STHL
Left shift start pulse
When left shift: STHL input, STHR output
input/output
A high level should be input as the pulse of one cycle of the clock signal.
If the start pulse input is more than 2CLK, the first 1CLK of the high-level input is valid.
CLK
Shift clock input
Input
Refers to the shift register’s shift clock input. The display data is incorporated into the data
register at the rising edge. At the rising edge of the 64th after the start pulse input, the start
pulse output reaches the high level, thus becoming the start pulse of the next-level driver. If
66th clock pulses are input after input of the start pulse, input of display data is halted
automatically. The contents of the shift register are cleared at the STB’s rising edge.
STB
Latch input
Input
The contents of the data register are transferred to the latch circuit at the rising edge. And, at
the falling edge of the STB, the gray scale voltage is supplied to the driver. When STB = H
period, driver output level is Hi-Z (High impedance).
It is necessary to ensure input of one pulse per horizontal period.
POL
Polarity input
Input
POL = L: The S2n–1 output uses V0 to V4 as the reference supply. The S2n output uses V5 to
V9 as the reference supply.
POL = H: The S2n–1 output uses V5 to V9 as the reference supply. The S2n output uses V0 to
V4 as the reference supply.
S2n−1 indicates the odd output, and S2n indicates the even output. Input of the POL signal is
allowed the setup time (tPOL-STB) with respect to STB’s rising edge.
POL21,
Data inversion input
Input
Data inversion can invert when display data is loaded.
POL21: D00 to D05, D10 to D15, D20 to D25, data inversion can invert display data
POL22
POL22: D30 to D35, D40 to D45, D50 to D55, data inversion can invert display data
POL21, POL22 = H: Data inversion loads display data after inverting it.
POL21, POL22 = L: Data inversion does not invert input data.
LPC,
Bias current control
HPC
input
Input
Please refer to panel loads and driver power supply voltage (VDD2), when set up these pins.
Refer to 10. BIAS CURRENT CONTROL BY LPC AND HPC. LPC pin is pulled down to the
VSS1 inside the IC, HPC pin is pulled up to the VDD1 inside the IC.
4
Data Sheet S16041EJ2V0DS
µPD160061A
(2/2)
Pin Symbol
SRC
Pin Name
High driving time
I/O
Description
Input
This pin is set up to high drive time of the output amplifier. Please decide the pin setting refer
to panel loads and one horizontal period. SRC pin is pulled up to the VDD1 inside the IC.
control
SRC = H or open: High drive time 64 CLK (Normally period mode)
SRC = L: High drive time 128 CLK (Long time mode)
Refer to 9. SRC AND HIGH DRIVE TIME.
V0 to V9
γ -corrected power
−
supplies
Input the γ -corrected power supplies from outside by using operational amplifier.
Make sure to maintain the following relationships. During the gray scale voltage output, be
sure to keep the gray scale level power supply at a constant level.
VDD2 − 0.2 V ≥ V0 > V1 > V2 > V3 > V4 ≥ 0.5 VDD2
VDD2 − 0.3 V ≥ > V5 > V6 > V7 > V8 > V9 ≥ VSS2 + 0.2 V
VDD1
Logic power supply
−
2.3 to 3.6 V
VDD2
Driver power supply
−
7.5 to 9.5 V
VSS1
Logic ground
−
Grounding
VSS2
Driver ground
−
Grounding
Cautions 1. The power start sequence must be VDD1, logic input, and VDD2 & V0 to V9 in that order.
Reverse this sequence to shut down.
2. To stabilize the supply voltage, please be sure to insert a 0.1 µF bypass capacitor between
VDD1 to VSS1 and VDD2 to VSS2. Furthermore, for increased precision of the D/A converter, insertion
of a bypass capacitor of about 0.01 µF is also recommended between the γ -corrected power
supply terminals (V0, V1, V2,....., V9) and VSS.
Data Sheet S16041EJ2V0DS
5
µPD160061A
5. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE
The µPD160061A incorporates a 6-bit D/A converter whose odd output pins and even output pins output respectively
gray scale voltages of differing polarity with respect to the LCD’s counter electrode voltage. The D/A converter consists of
ladder resistors and switches.
The ladder resistors (r0 to r62) are designed so that the ratio of LCD panel γ-compensated voltages to V0’ to V63’ and V0”
to V63” is almost equivalent, resistor ratio is shown in Figure 5−2. For the 2 sets of five γ-compensated power supplies, V0
to V4 and V5 to V9, respectively, input gray scale voltages of the same polarity with respect to the common voltage. When
fine-gray scale voltage precision is not necessary, there is no need to connect a voltage follower circuit to the γcompensated power supplies V1 to V3 and V6 to V8.
Figure 5–1 shows the relationship between the driving voltages such as liquid-crystal driving voltages VDD2 and VSS2,
common electrode potential VCOM, and γ -corrected voltages V0 to V9 and the input data. Be sure to maintain the voltage
relationships of below.
VDD2 – 0.2 V ≥ V0 > V1 > V2 > V3 > V4 ≥ 0.5 VDD2
0.5 VDD2 – 0.3 V ≥ V5 > V6 > V7 > V8 > V9 > VSS2 + 0.2 V
Figures 5–2 indicates γ -corrected voltages and ladder resistors ratio. Figures 5–3 indicates the relationship between the
input data and output voltage.
Figure 5–1. Relationship between Input Data and γ - corrected Power Supplies
VDD2
0.2 V
V0
16
V1
16
V2
16
V3
16
V4
0.5 VDD2
Split interval
0.3 V
V5
16
V6
16
V7
16
V8
16
V9
0.2 V
VSS2
00
6
10
20
Input data (HEX.)
Data Sheet S16041EJ2V0DS
30
3F
µPD160061A
Figure 5–2. γ - corrected Voltages and Ladder Resistors Ratio
V0
V0’
V5
r0
V63’’
r62
V1’
V62’’
r61
r1
V61’’
V2’
r60
r2
V60’’
V3’
r59
r3
r49
r14
V15’
V49’’
r48
r15
V16’
V1
V48’’
V6
r47
r16
V17’
V47’’
r46
r17
r46
r17
V47’
V17’’
r47
r16
V48’
V3
V16’’
V8
r48
r15
V49’
V15’’
r49
r14
r2
r60
V2’’
V61’
r1
r61
V62’
V1’’
r0
r62
V4
V63’
V9
rn
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r13
r14
r15
r16
r17
r18
r19
r20
r21
r22
r23
r24
r25
r26
r27
r28
r29
r30
r31
r32
r33
r34
r35
r36
r37
r38
r39
r40
r41
r42
r43
r44
r45
r46
r47
r48
r49
r50
r51
r52
r53
r54
r55
r56
r57
r58
r59
r60
r61
r62
Ratio
11.77
4.91
3.77
3.39
2.64
2.27
1.89
1.89
1.51
1.51
1.13
1.13
1.13
1.13
1.13
1.13
1.01
1.01
1.01
1.01
1.02
1.01
1.01
1.00
1.00
1.00
1.00
1.01
1.01
1.01
1.01
1.01
1.04
1.04
1.04
1.04
1.04
1.04
1.04
1.04
1.04
1.04
1.04
1.05
1.05
1.05
1.05
1.04
1.17
1.17
1.17
1.17
1.17
1.55
1.55
1.55
1.55
1.93
2.30
2.68
2.68
3.06
5.81
Value (TYP.)
1766
736
566
509
396
340
283
283
226
226
170
170
170
170
170
170
152
152
152
152
153
152
152
150
150
150
150
152
152
152
152
152
156
156
156
156
156
156
156
156
156
156
156
157
157
157
157
156
175
175
175
175
176
232
232
232
232
289
345
402
402
459
872
V0’’
Cautions1. There is no connection between V4 and V5 terminal in the IC.
2. The resistance ratio is a relative ratio in the case of setting the resistance minimum value to 1.
Data Sheet S16041EJ2V0DS
7
µPD160061A
Figure 5–3. Relationship between Input Data and Output Voltage (POL21, POL22 = L)
Output Voltage 1: VDD2 – 0.2 V ≥ V0 > V1 > V2 > V3 > V4 ≥ 0.5 VDD2
Output Voltage 2: 0.5 VDD2 – 0.3 V ≥ V5 > V6 > V7 > V8 > V9 ≥ VSS2 + 0.2 V
Input
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
8
V0'
V1'
V2'
V3'
V4'
V5'
V6'
V7'
V8'
V9'
V10'
V11'
V12'
V13'
V14'
V15'
V16'
V17'
V18'
V19'
V20'
V21'
V22'
V23'
V24'
V25'
V26'
V27'
V28'
V29'
V30'
V31'
V32'
V33'
V34'
V35'
V36'
V37'
V38'
V39'
V40'
V41'
V42'
V43'
V44'
V45'
V46'
V47'
V48'
V49'
V50'
V51'
V52'
V53'
V54'
V55'
V56'
V57'
V58'
V59'
V60'
V61'
V62'
V63'
Output Voltage 1
V0
V1+(V0-V1)×
4585
V1+(V0-V1)×
3849
V1+(V0-V1)×
3283
V1+(V0-V1)×
2774
V1+(V0-V1)×
2378
V1+(V0-V1)×
2038
V1+(V0-V1)×
1755
V1+(V0-V1)×
1472
V1+(V0-V1)×
1246
V1+(V0-V1)×
1020
V1+(V0-V1)×
850
V1+(V0-V1)×
680
V1+(V0-V1)×
510
V1+(V0-V1)×
340
V1+(V0-V1)×
170
V1
V2+(V1-V2)×
2273
V2+(V1-V2)×
2121
V2+(V1-V2)×
1969
V2+(V1-V2)×
1817
V2+(V1-V2)×
1664
V2+(V1-V2)×
1512
V2+(V1-V2)×
1360
V2+(V1-V2)×
1210
V2+(V1-V2)×
1060
V2+(V1-V2)×
910
V2+(V1-V2)×
760
V2+(V1-V2)×
608
V2+(V1-V2)×
456
V2+(V1-V2)×
304
V2+(V1-V2)×
152
V2
V3+(V2-V3)×
2344
V3+(V2-V3)×
2188
V3+(V2-V3)×
2032
V3+(V2-V3)×
1876
V3+(V2-V3)×
1720
V3+(V2-V3)×
1564
V3+(V2-V3)×
1408
V3+(V2-V3)×
1252
V3+(V2-V3)×
1096
V3+(V2-V3)×
940
V3+(V2-V3)×
784
V3+(V2-V3)×
627
V3+(V2-V3)×
470
V3+(V2-V3)×
313
V3+(V2-V3)×
156
V3
V4+(V3-V4)×
4398
V4+(V3-V4)×
4223
V4+(V3-V4)×
4048
V4+(V3-V4)×
3873
V4+(V3-V4)×
3697
V4+(V3-V4)×
3465
V4+(V3-V4)×
3233
V4+(V3-V4)×
3001
V4+(V3-V4)×
2769
V4+(V3-V4)×
2480
V4+(V3-V4)×
2135
V4+(V3-V4)×
1733
V4+(V3-V4)×
1331
V4+(V3-V4)×
872
V4
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
6351
6351
6351
6351
6351
6351
6351
6351
6351
6351
6351
6351
6351
6351
6351
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
2500
2500
2500
2500
2500
2500
2500
2500
2500
2500
2500
2500
2500
2500
2500
/
/
/
/
/
/
/
/
/
/
/
/
/
/
4573
4573
4573
4573
4573
4573
4573
4573
4573
4573
4573
4573
4573
4573
V0''
V1''
V2''
V3''
V4''
V5''
V6''
V7''
V8''
V9''
V10''
V11''
V12''
V13''
V14''
V15''
V16''
V17''
V18''
V19''
V20''
V21''
V22''
V23''
V24''
V25''
V26''
V27''
V28''
V29''
V30''
V31''
V32''
V33''
V34''
V35''
V36''
V37''
V38''
V39''
V40''
V41''
V42''
V43''
V44''
V45''
V46''
V47''
V48''
V49''
V50''
V51''
V52''
V53''
V54''
V55''
V56''
V57''
V58''
V59''
V60''
V61''
V62''
V63''
Data Sheet S16041EJ2V0DS
Output Voltage 2
V9
V9+(V8-V9)×
1766
V9+(V8-V9)×
2502
V9+(V8-V9)×
3068
V9+(V8-V9)×
3577
V9+(V8-V9)×
3973
V9+(V8-V9)×
4313
V9+(V8-V9)×
4596
V9+(V8-V9)×
4879
V9+(V8-V9)×
5105
V9+(V8-V9)×
5331
V9+(V8-V9)×
5501
V9+(V8-V9)×
5671
V9+(V8-V9)×
5841
V9+(V8-V9)×
6011
V9+(V8-V9)×
6181
V8
V8+(V7-V8)×
152
V8+(V7-V8)×
304
V8+(V7-V8)×
456
V8+(V7-V8)×
608
V8+(V7-V8)×
761
V8+(V7-V8)×
913
V8+(V7-V8)×
1065
V8+(V7-V8)×
1215
V8+(V7-V8)×
1365
V8+(V7-V8)×
1515
V8+(V7-V8)×
1665
V8+(V7-V8)×
1817
V8+(V7-V8)×
1969
V8+(V7-V8)×
2121
V8+(V7-V8)×
2273
V7
V7+(V6-V7)×
156
V7+(V6-V7)×
312
V7+(V6-V7)×
468
V7+(V6-V7)×
624
V7+(V6-V7)×
780
V7+(V6-V7)×
936
V7+(V6-V7)×
1092
V7+(V6-V7)×
1248
V7+(V6-V7)×
1404
V7+(V6-V7)×
1560
V7+(V6-V7)×
1716
V7+(V6-V7)×
1873
V7+(V6-V7)×
2030
V7+(V6-V7)×
2187
V7+(V6-V7)×
2344
V6
V6+(V5-V6)×
175
V6+(V5-V6)×
350
V6+(V5-V6)×
525
V6+(V5-V6)×
700
V6+(V5-V6)×
876
V6+(V5-V6)×
1108
V6+(V5-V6)×
1340
V6+(V5-V6)×
1572
V6+(V5-V6)×
1804
V6+(V5-V6)×
2093
V6+(V5-V6)×
2438
V6+(V5-V6)×
2840
V6+(V5-V6)×
3242
V6+(V5-V6)×
3701
V5
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
6351
6351
6351
6351
6351
6351
6351
6351
6351
6351
6351
6351
6351
6351
6351
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
2500
2500
2500
2500
2500
2500
2500
2500
2500
2500
2500
2500
2500
2500
2500
/
/
/
/
/
/
/
/
/
/
/
/
/
/
4573
4573
4573
4573
4573
4573
4573
4573
4573
4573
4573
4573
4573
4573
µPD160061A
6. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT PIN
Data format : 6 bits x 2 RGBs (6 dots)
Input width : 36 bits (2-pixel data)
(1) R,/L = H (Right shift)
Output
S1
S2
S3
S4
...
S527
S384
Data
D00 to D05
D10 to D15
D20 to D25
D30 to D35
...
D40 to D45
D50 to D55
(2) R,/L = L (Left shift)
Output
S1
S2
S3
S4
...
S527
S384
Data
D00 to D05
D10 to D15
D20 to D25
D30 to D35
...
D40 to D45
D50 to D55
Note
Note
S2n–1
S2n
L
V0 to V4
V5 to V9
H
V5 to V9
V0 to V4
POL
Note S2n–1 (Odd output), S2n (Even output)
Data Sheet S16041EJ2V0DS
9
µPD160061A
7. RELATIONSHIP BETWEEN STB CLK AND OUTPUT WAVEFORM
Figure 7–1. Input Circuit Block Diagram
Output AMP.
-
DAC
+
SW1
Sn
(VX)
VAMP(IN)
Figure 7–2. Output Circuit Timing Waveform
[1]
[1']
CLK
tSTB-CLK
STB
SW1: OFF
VAMP(IN)
Sn(VX)
Hi-Z
STB = H is loaded with the rising edge of CLK[1]. However, when not satisfying the specification of fSTB-CLK, STB = H is
loaded with the rising edge of the next CLK[1′]. Latch operation of display data is completed with the falling edge of the
next CLK which loaded STB = H. Therefore, in order to complete latch operation of display data, it is necessary to input
at least 2 CLK in STB = H period. Besides, after loading STB=H to the timing of [1], it is necessary to continue inputting
CLK.
10
Data Sheet S16041EJ2V0DS
µPD160061A
8. RELATIONSHIP BETWEEN STB, POL AND OUTPUT WAVEFORM
When the STB is high level, all outputs became Hi-Z and the gray-scale voltage is output to the LCD in synchronization
with the falling edge of STB.
Therefore, high drive time of the output amplifier as below is determined by the CLK number of the required SRC pin
setting. Be sure to avoid using such as extremely changing the CLK frequency (ex. CLK stop).
STB
High drive time
Inside bias current
High drive time
High drive time
POL
V0 - V 4
V5 - V 9
V5 - V9
V5 - V 9
V0 - V 4
V0 - V4
Vx (odd output)
Vx (even output)
Hi-Z
Hi-Z
Hi-Z
9. SRC AND HIGH DRIVE TIME
The µPD160061A can control high drive time of the output amplifier by SRC pin logic (refer to below figure).
SRC = H or open (high drive time: standard mode): High drive time (PWhp) of the output amplifier is in 64 CLK
period from falling edge of the STB.
SRC = L (high drive time: long-term mode): High drive time (PWhp) of the output amplifier is in 128 CLK period
from falling edge of the STB.
STB
CLK
PWhp
Inside bias current
We recommend a thorough simulation of the output amplifier in advance when set the SRC pin.
Data Sheet S16041EJ2V0DS
11
µPD160061A
10. BIAS CURRENT CONTROL BY LPC AND HPC
The µPD160061A can control the bias current of the output amplifier in high drive period and low drive period.
Bias Current
LPC
HPC
High
H
L
Middle
H or open
L
Normal
L or open
H or open
Low
H
H or open
Panel Load
Heavy
Light
We recommend a thorough simulation of the output amplifier in advance, when set the LPC and HPC pins.
Refer to the table below for the example of the combination of setting level and panel load, with driver part supply voltage.
Example of Condition
Example 1
Example 2
Example 3
12
LPC
HPC
Load: RL = 5 kΩ, CL = 75 pF
L or open
L
Driver part supply voltage: VDD2 = 7.5 V
Bias current mode: Middle
Load: RL = 5 kΩ, CL = 75 pF
L or open
Driver part supply voltage: VDD2 = 9.0 V
Bias current mode: Normal
H or open
Load: RL = 40 kΩ, CL = 80 pF
H
Driver part supply voltage: VDD2 = 9.0 V
Bias current mode: High
Data Sheet S16041EJ2V0DS
L
SRC
H or open
H or open
L
µPD160061A
11. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°C, VSS1 = VSS2 = 0 V)
Parameter
Symbol
Rating
Unit
Logic Part Supply Voltage
VDD1
–0.5 to +4.0
V
Driver Part Supply Voltage
VDD2
–0.5 to +10.0
V
Logic Part Input Voltage
VI1
–0.5 to VDD1 + 0.5
V
Driver Part Input Voltage
VI2
–0.5 to VDD2 + 0.5
V
Logic Part Output Voltage
VO1
–0.5 to VDD1 + 0.5
V
Driver Part Output Voltage
VO2
–0.5 to VDD2 + 0.5
V
Operating Ambient Temperature
TA
–10 to +75
°C
Storage Temperature
Tstg
–55 to +125
°C
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge
of suffering physical damage, and therefore the product must be used under conditions that ensure that
the absolute maximum ratings are not exceeded.
Recommended Operating Range (TA = –10 to +75°C, VSS1 = VSS2 = 0 V)
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
3.6
V
9.5
V
Logic Part Supply Voltage
VDD1
2.3
Driver Part Supply Voltage
VDD2
7.5
High-Level Input Voltage
VIH
0.7 VDD1
VDD1
V
Low-Level Input Voltage
VIL
0
0.3 VDD1
V
γ -Corrected Voltage
V0 to V4
7.5 V ≤ VDD1 ≤ 9.5 V
0.5 VDD2
VDD2 – 0.2
V
V5 to V9
7.5 V ≤ VDD1 < 8.5 V
0.2
0.5 VDD2 – 0.3
V
8.5 V ≤ VDD1 ≤ 9.5 V
0.2
0.5 VDD2
V
0.2
VDD2 – 0.2
V
2.3 V ≤ VDD1 < 2.7 V
40
MHz
2.7 V ≤ VDD1 ≤ 3.6 V
65
MHz
Driver Part Output Voltage
VO
Clock Frequency
fCLK
Data Sheet S16041EJ2V0DS
8.5
13
µPD160061A
★ Electrical Characteristics (TA = –10 to +75°C, VDD1 = 2.3 to 3.6 V, VDD2 = 7.5 to 9.5 V, VSS1 = VSS2 = 0 V)
Parameter
Symbol
Input Leak Current
IIL
MAX.
Unit
Except LPC, HPC, SRC
Condition
MIN.
±1.0
µA
LPC, HPC, SRC
±150
µA
0.1
V
High-Level Output Voltage
VOH
STHR (STHL), IOH = 0 mA
Low-Level Output Voltage
VOL
STHR (STHL), IOL = 0 mA
γ -Corrected Resistance
Rγ
V0 to V4 = V5 to V9 = 4.0 V, VDD2 = 8.5 V
Driver Output Current
IVOH
VDD2 = 8.0 V, VX = 7.0 V, VOUT = 6.5 V
Note1
Note1
TYP.
VDD1 – 0.1
7.9
V
15.8
23.7
kΩ
– 20
µA
µA
IVOL
VDD2 = 8.0 V, VX = 1.0 V, VOUT = 1.5 V
Output Voltage Deviation
∆VO
TA = 25°C,
±10
±20
mV
Output Swing Difference
∆VP–P
VDD1 = 3.3 V, VDD2 = 8.5 V,
±3
±15
mV
IDD1
VDD1
4
12
mA
IDD22
VDD2, with no load
3.5
8
mA
Deviation
Logic Part Dynamic Current
Consumption
VOUT = 2.0 V, 4.25 V, 6.5 V
Note2, 3, 4
Driver Part Dynamic Current
Consumption
20
Note2, 4
Notes1. VX refers to the output voltage of analog output pins S1 to S384. VOUT refers to the voltage applied to analog output
pins S1 to S384.
2. Specified at fSTB = 65 kHz and fCLK = 54 MHz.
3. The TYP. values refer to an all black or all white input pattern. The MAX. value refers to the measured values in
the dot checkerboard input pattern.
4. Refers to the current consumption per driver when cascades are connected under the assumption of XGA
single-sided mounting (8 units).
Switching Characteristics (TA = –10 to +75°C, VDD1 = 2.3 to 3.6 V, VDD2 = 7.5 to 9.5 V, VSS1 = VSS2 = 0 V)
Parameter
Symbol
Start Pulse Delay Time
tPLH1
tPLH1
Driver Output Delay Time
Input Capacitance
Condition
MIN.
TYP.
MAX.
Unit
ns
CL = 15 pF, 2.3 V ≤ VDD1 < 2.7 V
20
CL = 10 pF, 2.7 V ≤ VDD1 ≤ 3.6 V
10.5
ns
CL = 10 pF, 2.3 V ≤ VDD1 < 2.7 V
20
ns
CL = 10 pF, 2.7 V ≤ VDD1 ≤ 3.6 V
10.5
ns
tPLH2
CL = 75 pF, RL = 5 kΩ,
5
µs
tPLH3
LPC = L or open,
8
µs
tPHL2
HPC = H or open,
5
µs
tPHL3
SRC = H or open
8
µs
CI1
Logic input of exclude STHR (STHL),
10
pF
5
pF
TA = 25°C
STHR (STHL), TA = 25°C
CI2
<Measurement condition>
RLn = 1 kΩ, CLn = 15 pF
The measurement point
RL1
RL2
RL3
RL4
RL5
Output
CL1
CL2
CL3
GND
14
Data Sheet S16041EJ2V0DS
CL4
CL5
µPD160061A
Timing Requirements (TA = –10 to +75°C, VDD1 = 2.3 to 3.6 V, VSS1 = 0 V, tr = tf = 5.0 ns)
Parameter
Clock Pulse Width
Clock Pulse High Period
Clock Pulse Low Period
Symbol
PWCLK
PWCLK(H)
PWCLK(L)
Condition
MIN.
TYP.
MAX.
Unit
2.3 V ≤ VDD1 < 2.7 V
25
ns
2.7 V ≤ VDD1 ≤ 3.6 V
15
ns
2.3 V ≤ VDD1 < 2.7 V
6
ns
2.7 V ≤ VDD1 ≤ 3.6 V
4
ns
2.3 V ≤ VDD1 < 2.7 V
6
ns
2.7 V ≤ VDD1 ≤ 3.6 V
4
ns
Data Setup Time
tSETUP1
4
ns
Data Hold Time
tHOLD1
0
ns
Start Pulse Setup Time
tSETUP2
4
ns
Start Pulse Hold Time
tHOLD2
0
ns
POL21, POL22 Setup Time
tSETUP3
4
ns
POL21, POL22 Hold Time
tHOLD3
0
ns
STB Pulse Width
PWSTB
2
CLK
Last Data Timing
tLDT
2
CLK
STB-CLK Time
tSTB -CLK
9
ns
Time Between STB and Start Pulse
tSTB-STH
STB ↑ → STHR(STHL) ↑
2
CLK
POL-STB Time
tPOL-STB
POL ↑ or ↓ → STB ↑
–5
ns
STB-POL Time
tSTB-POL
STB ↓ → POL ↓ or ↑
6
ns
STB ↑→ CLK ↑
Remark Unless otherwise specified, the input level is defined to be VIH = 0.7 VDD1, VIL = 0.3 VDD1.
Data Sheet S16041EJ2V0DS
15
16
INVALID
POL21/22
Data Sheet S16041EJ2V0DS
Sn
(VX)
POL
STB
STHL
(1st Dr.)
INVALID
t SETUP2
D n0 to D n5
STHR
(1st Dr.)
CLK
t SETUP1
2
PWCLK
t HOLD1
3
PW CLK(H)
t SETUP3
t HOLD3
D1 to D6 D7 to D12
t HOLD2
1
PW CLK(L)
tPLH1
D373 to
D378
64
D 379 to
D384
65
D385 to
D390
66
Last
Data
t POL-STB
t LDT
Hi-Z
PW STB
t STB-CLK
t PHL3
t PHL2
t PLH2
t PLH3
t STB-POL
INVALID
INVALID
t STB-STH
90%
10%
tr
tf
D1 to D6 D 7 to D12
2
V SS1
V DD1
V SS1
V DD1
V SS1
V DD1
V SS1
V DD1
V SS1
V DD1
V SS1
V DD1
V SS1
V DD1
Target Voltage: +
− 2%
Target Voltage: +
− 10%
1
µPD160061A
SWITCHING CHARACTERISTICS WAVEFORM (R,/L= H)
Unless otherwise specified, the input level is defined to be VIH = 0.7 VDD1, VIL = 0.3 VDD1.
µPD160061A
12. RECOMMENDED MOUNTING CONDITIONS
The following conditions must be met for mounting conditions of the µPD160061A.
For more details, refer to the Semiconductor Device Mount Manual
(http://www.necel.com/pkg/en/mount/index.html).
Please consult with our sales offices in case other mounting process is used, or in case the mounting is done under
different conditions.
µ PD160061AN - ×××: TCP (TAB package)
Mounting Condition
Thermocompression
Mounting Method
Soldering
Condition
Heating tool 300 to 350°C, heating for 2 to 3 seconds, pressure 100 g (per
solder)
2
ACF
Temporary bonding 70 to 100°C, pressure 3 to 8 kg/cm , time 3 to 5
(Adhesive Conductive
seconds.
Film)
Real bonding 165 to 180°C, pressure 25 to 45 kg/cm , time 30 to 40
2
seconds. (When using the anisotropy conductive film SUMIZAC1003 of
Sumitomo Bakelite, Ltd.)
Caution To find out the detailed conditions for mounting the ACF part, please contact the ACF manufacturing
company. Be sure to avoid using two or more mounting methods at a time.
Data Sheet S16041EJ2V0DS
17
µPD160061A
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
18
Data Sheet S16041EJ2V0DS