DATA SHEET MOS INTEGRATED CIRCUIT µ PD3768 7500 PIXELS × 3 COLOR CCD LINEAR IMAGE SENSOR DESCRIPTION The µ PD3768 is a high-speed and high sensitive color CCD (Charge Coupled Device) linear image sensor which changes optical images to electrical signal and has the function of color separation. The µ PD3768 has 3 rows of 7500 pixels, and it is a 2-output/color type CCD sensor with 2 rows/color of charge transfer register, which transfers the photo signal electrons of 7500 pixels separately in odd and even pixels. Therefore, it is suitable for 600 dpi/A3 high-speed color digital copiers, color scanners and so on. FEATURES • Valid photocell : 7500 pixels × 3 • Photocell pitch : 9.325 µ m • Line spacing : 37.3 µ m (4 lines) Red line - Green line, Green line - Blue line • Color filter : Primary colors (red, green and blue), pigment filter (with light resistance 10 lx•hour) • Resolution : 24 dot/mm A3 (297 × 420 mm) size (shorter side) 7 • Drive clock level : CMOS output under 5 V operation • Data rate : 44 MHz MAX. (22 MHz/1 output) • Output type : 2 outputs in phase/color • Power supply : +10 V • On-chip circuits : Reset feed-through level clamp circuits Voltage amplifiers ORDERING INFORMATION Part Number Package µ PD3768D CCD linear image sensor 36-pin ceramic DIP (CERDIP) (15.24 mm (600)) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S15418EJ2V0DS00 (2nd edition) Date Published September 2002 NS CP (K) Printed in Japan The mark shows major revised points. 2001 µ PD3768 BLOCK DIAGRAM VOD 31 VOUT2 (Blue, even) 32 GND 33 VOUT1 (Blue, odd) 34 GND 35 φ CP φ 2L φ 20 GND φ 1B φ 2A 30 29 28 16 23 24 CCD analog shift register 2 D140 S7499 S7500 ..... φ TG1 (Blue) D140 5 ..... 22 21 φ TG2 (Green) D140 VOUT5 (Red, odd) D129 4 D129 GND ..... D129 3 Photocell (Green) S7499 S7500 S1 S2 ..... D128 D27 VOUT6 (Red, even) (Blue) 15 φ TG3 (Red) CCD analog shift register Transfer gate Transfer gate CCD analog shift register VOUT4 1 (Green, even) 2 Photocell Transfer gate CCD analog shift register VOUT3 36 (Green, odd) GND S1 S2 ..... D128 D27 Transfer gate CCD analog shift register Photocell (Red) S7499 S7500 S1 S2 ..... D128 D27 Transfer gate Transfer gate CCD analog shift register 6 7 8 9 13 14 VOD φR φ 2L φ 10 φ 1A φ 2B Data Sheet S15418EJ2V0DS µ PD3768 PIN CONFIGURATION (Top View) CCD linear image sensor 36-pin ceramic DIP (CERDIP) (15.24 mm (600)) • µ PD3768D Output signal 4 (Green, even) VOUT4 1 Ground 1 Output signal 6 (Red, even) VOUT6 3 1 GND 2 1 Ground GND 4 Output signal 5 (Red, odd) VOUT5 5 36 VOUT3 Output signal 3 (Green, odd) 35 GND Ground 34 VOUT1 Output signal 1 (Blue, odd) 33 GND Ground 32 VOUT2 Output signal 2 (Blue, even) Output unit drain voltage Reset gate clock φR 7 30 φ CP Reset feed-through level clamp clock Last stage shift register clock φ 2L 8 29 φ 2L Last stage shift register clock Shift register clock 10 φ 10 9 28 φ 20 Shift register clock 20 No connection NC 10 27 NC No connection No connection NC 11 26 NC No connection No connection NC 12 25 NC No connection Shift register clock 1A φ 1A 13 24 φ 2A Shift register clock 2A Shift register clock 2B φ 2B 14 23 φ 1B Shift register clock 1B 22 φ TG1 Transfer gate clock 1 (for Blue) 21 φ TG2 Transfer gate clock 2 (for Green) Blue 31 VOD Red VOD 6 Green Output unit drain voltage Caution 7500 7500 7500 Transfer gate clock 3 (for Red) φ TG3 15 Ground GND 16 No connection NC 17 20 NC No connection No connection NC 18 19 NC No connection Connect the No connection pins (NC) to GND. PHOTOCELL STRUCTURE DIAGRAM PHOTOCELL ARRAY STRUCTURE DIAGRAM (Line spacing) 9.325 µ m 9.325 µ m 6.325 µm Aluminum shield Blue photocell array 4 lines (37.3 µm) 3 µm Channel stopper 9.325 µ m Green photocell array 4 lines (37.3 µm) 9.325 µ m Data Sheet S15418EJ2V0DS Red photocell array 3 µ PD3768 ABSOLUTE MAXIMUM RATINGS (TA = +25°°C) Parameter Symbol Ratings Unit Output drain voltage VOD −0.3 to +12 V Shift register clock voltage Vφ 1, Vφ 2 −0.3 to +8 V Last gate shift register clock voltage Vφ 2L −0.3 to +8 V Reset gate clock voltage Vφ R −0.3 to +8 V Clamp clock voltage Vφ CP −0.3 to +8 V Transfer gate clock voltage Vφ TG1 to Vφ TG3 −0.3 to +8 V Operating ambient temperature Note TA −25 to +60 °C Storage temperature Tstg −40 to +100 °C Note Use at the condition without dew condensation. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. RECOMMENDED OPERATING CONDITIONS (TA = +25°°C) Parameter Symbol Min. Typ. Max. Unit 9.5 10.0 10.5 V Output drain voltage VOD Shift register clock high level Vφ 1H, Vφ 2H 4.5 5.0 5.5 V Shift register clock low level Vφ 1L, Vφ 2L −0.3 0 +0.5 V Last gate shift register clock high level Vφ 2LH 4.5 5.0 5.5 V Last gate shift register clock low level Vφ 2LL −0.3 0 +0.5 V Reset gate clock high level Vφ RH 4.5 5.0 5.5 V Reset gate clock low level Vφ RL −0.3 0 +0.5 V Clamp clock high level Vφ CPH 4.5 5.0 5.5 V Clamp clock low level Vφ CPL −0.3 0 +0.5 V Note Vφ 1H V Transfer gate clock high level Vφ TG1H to Vφ TG3H 4.5 Note Vφ 1H Transfer gate clock low level Vφ TG1L to Vφ TG3L −0.3 0 +0.5 V Data rate 2fφ R 1 2 44 MHz Note When Transfer gate clock high level (Vφ TG1H to Vφ TG3H) is higher than Shift register clock high level (Vφ 1H), Image lag can increase. 4 Data Sheet S15418EJ2V0DS µ PD3768 ELECTRICAL CHARACTERISTICS TA = +25°C, VOD = 10 V, fφ R = 1 MHz, data rate = 2 MHz, storage time = 10 ms, input signal clock = 5 Vp-p, light source (except Response1) : 2950 K halogen lamp + CM-500S (infrared cut filter, t = 1 mm) Parameter Symbol Saturation voltage Test Conditions Vsat Saturation exposure 2950 K halogen lamp + CM-500S Min. Typ. Max. Unit 1.5 2.0 − V Red SER − 0.14 − lx•s Green SEG − 0.13 − lx•s Blue SEB − 0.26 − lx•s Photo response non-uniformity PRNU VOUT = 1.0 V − 6.0 18.0 % Photo response non-uniformity PRNU2 VOUT = 0.1 V − 6.0 18.0 % Light shielding, data rate = 2 MHz, − 1.0 5.0 mV − 3.0 12.0 mV at low illumination Average dark signal ADS storage time = 10 ms Dark signal non-uniformity DSNU Light shielding, data rate = 2 MHz, storage time = 10 ms Power consumption PW − 700 900 mW Output impedance ZO − 0.2 0.4 kΩ Response1 Response2 Red RR 3200 K halogen lamp + C-500S 15.4 22.0 28.6 V/lx•s Green RG + HA-50 12.6 18.0 23.4 V/lx•s 5.6 8.0 10.4 V/lx•s 9.8 14.0 18.2 V/lx•s Blue RB Red RR Green RG 10.7 15.3 19.9 V/lx•s Blue RB 5.3 7.6 9.9 V/lx•s 2950 K halogen lamp + CM-500S Image lag IL VOUT = 500 mV − 40 80 mV Image lag color difference IL-DIF VOUT = 500 mV − 5 20 mV Image lag O/E IL-O/E VOUT = 500 mV − 10 30 mV 3.8 4.5 5.2 V Offset level Note 1 VOS Note 2 − 14 − ns Register imbalance RI VOUT = 1.0 V − 0 5 % Total transfer efficiency TTE VOUT = 1.0 V, fφ R = 22 MHz 94 98 − % − 630 − nm Output fall delay time Response peak td Red Green − 540 − nm Blue − 445 − nm Dynamic range DR1 Vsat/DSNU − 666 − times DR2 Vsat/σ dark − 870 − times −1000 −200 +500 mV − 2.3 − mV Reset feed-through noise RFTN Light shielding Light shielding random noise σ dark Bit clamp, t17 = 10 ns Notes 1. Refer to TIMING CHART 2 and TIMING CHART 4. 2. td is defined as periods from 10% of φ 2L to 10% of VOUT1 to VOUT6 (refer to APPLICATION CURCUIT EXAMPLE). Data Sheet S15418EJ2V0DS 5 µ PD3768 INPUT PIN CAPACITANCE (TA = +25°°C, VOD = 10 V) Parameter Shift register clock pin capacitance Symbol Cφ 1 Cφ 2 Last stage shift register clock pin capacitance Cφ L Pin Pin No. Min. Typ. Max. Unit φ 10 9 − 330 450 pF φ 1A 13 − 330 450 pF φ 1B 23 − 330 450 pF φ 2B 14 − 330 450 pF φ 2A 24 − 330 450 pF φ 20 28 − 330 450 pF φ 2L 8 − 10 20 pF 29 − 10 20 pF 7 − 10 20 pF Cφ R φR Clamp clock pin capacitance Cφ CP φ CP 30 − 10 20 pF Transfer gate clock pin capacitance Cφ TG φ TG1 22 − 100 150 pF φ TG2 21 − 100 150 pF φ TG3 15 − 100 150 pF Reset gate clock pin capacitance 6 Data Sheet S15418EJ2V0DS TIMING CHART 1 (Bit clamp mode, for each color) φ TG1 to φ TG3 φ 10, φ 1A, φ 1B φ 20, φ 2A, φ 2B φ 2L φR 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 119 121 123 125 127 129 131 7625 7627 7629 7631 7633 7635 7637 120 122 124 126 128 130 132 7626 7628 7630 7632 7634 7636 7638 Note 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Data Sheet S15418EJ2V0DS φ CP Note VOUT1, 3, 5 VOUT2, 4, 6 Optical black (96 pixels) Invalid photocell (6 pixels) Invalid photocell (6 pixels) 7 µ PD3768 Note Set the φ R and φ CP pulse to low level during this period. Valid photocell (7500 pixels) µ PD3768 TIMING CHART 2 (Bit clamp mode, for each color) t6 φ 10, φ 1A, φ 1B 90% 10% φ 20, φ 2A, φ 2B 90% 10% t7L 90% 10% t8 φ 2L t6L t9 t10 t17 t15 90% 10% φR t16 t12 t13 t14 90% 10% φ CP td + VOUT1 to VOUT6 RFTN − 10% Symbol 8 t7 Min. Typ. Max. Unit t6, t7 0 50 − ns t6L, t7L 0 5 − ns t8, t10 0 5 − ns t9 10 125 − ns t12, t14 0 5 − ns t13 10 125 − ns t15 0 250 − ns t16 8 125 − ns t17 8 125 − ns Data Sheet S15418EJ2V0DS VOS TIMING CHART 3 (Line clamp mode, for each color) φ TG1 to φ TG3 φ 10, φ 1A, φ 1B φ 20, φ 2A, φ 2B φ 2L φR 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 119 121 123 125 127 129 131 7625 7627 7629 7631 7633 7635 7637 120 122 124 126 128 130 132 7626 7628 7630 7632 7634 7636 7638 Note 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Data Sheet S15418EJ2V0DS φ CP Note VOUT1, 3, 5 VOUT2, 4, 6 Optical black (96 pixels) Invalid photocell (6 pixels) Invalid photocell (6 pixcels) 9 µ PD3768 Note Set the φ R and φ CP pulse to low level during this period. Valid photocell (7500 pixels) µ PD3768 TIMING CHART 4 (Line clamp mode, for each color) t6 φ 10, φ 1A, φ 1B 90% 10% φ 20, φ 2A, φ 2B 90% 10% t7L 90% 10% t8 φ 2L t6L t9 t10 t20 90% 10% φR φ CP 'L' td + VOUT1 to VOUT6 RFTN − 10% Symbol 10 t7 Min. Typ. Max. Unit t6, t7 0 50 − ns t6L, t7L 0 5 − ns t8, t10 0 5 − ns t9 10 125 − ns t20 5 250 − ns Data Sheet S15418EJ2V0DS VOS µ PD3768 TIMING CHART 5 (Bit clamp mode, line clamp mode, for each color) t2 90% 10% t1 φ TG1 to φ TG3 φ 10, φ 1A, φ 1B t4 t3 90% φ 20, φ 2A, φ 2B φ 2L Note t5 t8 t9 t10 t17 t15 90% 10% φR t16 t12 t13 t14 90% 10% φ CP Symbol Min. Typ. Max. Unit t1, t5 200 300 − ns t2, t4 0 50 − ns 3000 5000 − ns t8, t10 0 5 − ns t9 10 125 − ns t12, t14 0 5 − ns t13 10 125 − ns t15 0 250 − ns t16 8 125 − ns t17 8 125 − ns t3 Note Set the φ R and φ CP pulse to low level during this period. Data Sheet S15418EJ2V0DS 11 µ PD3768 φ 10, φ 20 cross points φ 10 φ 20 2.0 V or more 2.0 V or more 2.0 V or more 2.0 V or more 2.0 V or more 2.0 V or more φ 1A, φ 2A cross points φ 1A φ 2A φ 1B, φ 2B cross points φ 1B φ 2B φ 10, φ 2L cross points φ 10 φ 2L 2.0 V or more 0.5 V or more Remark Adjust cross points (φ 10, φ 20), (φ 1A, φ 2A), (φ 1B, φ 2B) and (φ 10, φ 2L) with input resistance of each pin. 12 Data Sheet S15418EJ2V0DS µ PD3768 DEFINITIONS OF CHARACTERISTIC ITEMS 1. Saturation voltage : Vsat Output signal voltage at which the response linearity is lost. 2. Saturation exposure : SE Product of intensity of illumination (lx) and storage time (s) when saturation of output voltage occurs. 3. Photo response non-uniformity : PRNU The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light of uniform illumination. This is calculated by the following formula, and it is defined by each six of them. PRNU (%) = ∆x x × 100 ∆ x : maximum of xj − x 7500 Σx j x= j=1 7500 xj : Output voltage of valid pixel number j VOUT x Register Dark DC level ∆x 4. Average dark signal : ADS Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following formula, and it is defined by each six of them. 7500 Σd ADS (mV) = j j=1 7500 dj : Dark signal of valid pixel number j Data Sheet S15418EJ2V0DS 13 µ PD3768 5. Dark signal non-uniformity : DSNU Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid pixels at light shielding. This is calculated by the following formula, and it is defined by each six of them. DSNU (mV) : maximum of dj − ADS j = 1 to 7500 dj : Dark signal of valid pixel number j VOUT ADS Register Dark DC level DSNU 6. Output impedance : ZO Impedance of the output pins viewed from outside. 7. Response : R Output voltage divided by exposure (lx•s). Note that the response varies with a light source (spectral characteristic). 8. Image lag : IL The rate between the last output voltage and the next one after read out the data of a line. φ TG Light ON OFF VOUT V1 VOUT IL (mV) = V1 (VOUT = 500 mV) 9. Image lag color difference : IL-DIF It is defined as a difference between colors of the average of image lag. It is expressed with the next expression to be concrete. | (average of image lag of blue output) − (average of image lag of green output) | | (average of image lag of green output) − (average of image lag of red output) | | (average of image lag of red output) − (average of image lag of blue output) | 14 Data Sheet S15418EJ2V0DS µ PD3768 10. Image lag O/E : IL-O/E It is defined as a difference of the average of image lag of odd and even pixels for each color. 11. Register imbalance : RI The rate of the difference between the averages of the output voltage of Odd and Even pixels, against the average output voltage of all the valid pixels. n 2 ∑ (V2j –1 – V2j) 2 n j=1 RI (%) = × 100 n 1 n ∑ Vj j=1 n : Number of valid pixels Vj : Output voltage of each pixel 12. Total transfer efficiency : TTE The total transfer rate of CCD analog shift register. This is calculated by the following formula, it is difined by each output. TTE (%) = (1 − Vb / average output of all the valid pixels) × 100 Vb Va−1 : The last pixel output − 1 (Odd pixel: 7631th pixel) Va : The last pixel output (Odd pixel: 7633th pixel) Vb : The spilt pixel output (Odd pixel: 7635th pixel) Va−1 Va 13. Light shielding random noise : σ dark Light shielding random noise σ dark is defined as the standard deviation of a valid pixel output signal with 100 times (=100 lines) data sampling at dark (light shielding). 100 σ dark (mV) = Σ (V – V) 2 i i=1 100 , V= 1 100 ΣV i 100 i = 1 Vi : A valid pixel output signal among all of the valid pixels for each color VOUT V1 line 1 V2 line 2 … … V100 line 100 This is measured by the DC level sampling of only the signal level, not by CDS (Correlated Double Sampling). Data Sheet S15418EJ2V0DS 15 µ PD3768 STANDARD CHARACTERISTIC CURVES (Reference Value) DARK OUTPUT TEMPERATURE CHARACTERISTIC STORAGE TIME OUTPUT VOLTAGE CHARACTERISTIC (TA = +25°C) 8 2 2 1 0.5 0.2 0.25 0.1 0 1 Relative Output Voltage Relative Output Voltage 4 10 20 30 40 0.1 50 1 5 Operating Ambient Temperature TA (°C) Storage Time (ms) TOTAL SPECTRAL RESPONSE CHARACTERISTICS (without infrared cut filter and heat absorbing filter) (TA = +25°C) 100 R 80 Response Ratio (%) G 60 B 40 20 B G 0 400 500 600 Wavelength (nm) 16 Data Sheet S15418EJ2V0DS 700 10 µ PD3768 APPLICATION CIRCUIT EXAMPLE +5 V +10 V 10 Ω + + µ PD3768 1 B4 10 µ F/16 V 0.1 µ F 2 3 B6 4 5 B5 6 φR φ 2L φ 10 GND VOUT6 VOUT1 GND GND VOUT5 VOUT2 B3 34 B1 + 33 32 0.1 µ F 10 µ F/16 V B2 31 φ CP 30 47 Ω φ 2L 29 47 Ω φ 10 φ 20 28 2Ω NC NC NC NC NC NC 13 φ 1A 24 2Ω φ 2A 14 φ1B 23 2Ω 2Ω φ 2B 15 φ TG1 22 2Ω φ TG2 21 2Ω 7 47 Ω 8 2Ω 9 12 16 17 18 φ 2L φ TG3 GND NC NC NC NC +5 V 0.1 µ F 47 µ F/25 V 35 φR 47 Ω 2Ω φ TG3 GND 36 VOD 11 φ 2B VOUT3 VOD 10 φ 1A VOUT4 φ CP φ 2L φ 20 27 26 2Ω 25 φ 2A φ 1B φ TG1 φ TG2 20 19 Caution Connect the No connection pins (NC) to GND. Remarks 1. Connect two inverters (74AC04) to each φ 10, φ 1A, φ 1B, φ 20, φ 2A, φ 2B pin. 2. Inverters shown in the above application circuit example are the 74AC04. 3. B1 to B6 in the application circuit example are shown in the figure below. B1-B6 equivalent curcuit +10 V 47 µ F/25 V + 4.7 kΩ 110 Ω CCD VOUT 47 Ω 2SC945 2SA1005 1 kΩ Data Sheet S15418EJ2V0DS 17 µ PD3768 PACKAGE DRAWING CCD LINEAR IMAGE SENSOR 36-PIN CERAMIC DIP (15.24 mm (600)) 94.0±0.7 3.0±0.1 3.00±0.08 1.0±0.08 14.66 4 1.28±0.1 26.0±0.2 33.3±0.6 7.33±0.3 1 The 1st valid pixel (5.0) 1.27 24.13±0.20 20.32±0.13 48.26±0.40 3.85±0.38 (2.6) 3 (1.8) 0.46 (17.09 MAX.) 20.32±0.13 (15.24 MIN.) 2.54±0.13 2.0±0.2 2.4±0.3 5.0±0.2 2 0.25±0.05 Name Dimension Refractive index Glass cap 91.0×9.0×1.1 1.5 1 1st valid pixel Center of package 2 The bottom of package The surface of the chip 3 The surface of the chip The surface of the glass cap 4 The tolerance of packge dimension ±0.25 : less than 10 mm from W/F edge ±0.50 : equal or more than 10 mm from W/F edge 36D-1CCD-PKG3-1 18 Data Sheet S15418EJ2V0DS µ PD3768 RECOMMENDED SOLDERING CONDITIONS When soldering this product, it is highly recommended to observe the conditions as shown below. If other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices. Type of Through-hole Device µ PD3768D : CCD linear image sensor 36-pin ceramic DIP (CERDIP) (15.24 mm (600)) Process Partial heating method Conditions Pin temperature : 300 °C or below, Heat time : 3 seconds or less (per pin) Cautions 1. During assembly care should be taken to prevent solder or flux from contacting the glass cap. The optical characteristics could be degraded by such contact. 2. Soldering by the solder flow method may have deleterious effects on prevention of glass cap soiling and heat resistance. So the method cannot be guaranteed. Data Sheet S15418EJ2V0DS 19 µ PD3768 NOTES ON HANDLING THE PACKAGES 1 MOUNTING OF THE PACKAGE The application of an excessive load to the package may cause the package to warp or break, or cause chips to come off internally. Particular care should be taken when mounting the package on the circuit board. Don't have any object come in contact with glass cap. You should not reform the lead frame. We recommended to use a IC-inserter when you assemble to PCB. Also, be care that the any of the following can cause the package to crack or dust to be generated. 1. Applying heat to the external leads for an extended period of time with soldering iron. 2. Applying repetitive bending stress to the external leads. 3. Rapid cooling or heating For this product, the reference value for the three-point bending strength Note is 180 [N] (at distance between supports: 70 mm), is 500 [N] (at distance between supports: 26 mm). Avoid imposing a load, however, on the inside portion as viewed from the face on which the window (glass) is bonded to the package body (ceramic). Note Three-point bending strength test Distance between supports: 70 mm or 26 mm, Support R: R 2 mm, Loading rate: 0.5 mm/min. Load Load 70 mm 70 mm Load Load 26 mm 26 mm 2 GLASS CAP Don’t either touch glass cap surface by hand or have any object come in contact with glass cap surface. Care should be taken to avoid mechanical or thermal shock because the glass cap is easily to damage. For dirt stuck through electricity ionized air is recommended. 20 Data Sheet S15418EJ2V0DS µ PD3768 NOTES ON HANDLING THE PACKAGES 3 OPERATE AND STORAGE ENVIRONMENTS Operate in clean environments. CCD image sensors are precise optical equipment that should not be subject to mechanical shocks. Exposure to high temperatures or humidity will affect the characteristics. So avoid storage or usage in such conditions. Keep in a case to protect from dust and dirt. Dew condensation may occur on CCD image sensors when the devices are transported from a low-temperature environment to a high-temperature environment. Avoid such rapid temperature changes. For more details, refer to our document "Review of Quality and Reliability Handbook" (C12769E) 4 ELECTROSTATIC BREAKDOWN CCD image sensor is protected against static electricity, but destruction due to static electricity is sometimes detected. Before handling be sure to take the following protective measures. 1. 2. 3. 4. 5. Ground the tools such as soldering iron, radio cutting pliers of or pincer. Install a conductive mat or on the floor or working table to prevent the generation of static electricity. Either handle bare handed or use non-chargeable gloves, clothes or material. Ionized air is recommended for discharge when handling CCD image sensor. For the shipment of mounted substrates, use box treated for prevention of static charges. 6. Anyone who is handling CCD image sensors, mounting them on PCBs or testing or inspecting PCBs on which CCD image sensors have been mounted must wear anti-static bands such as wrist straps and ankle straps which are grounded via a series resistance connection of about 1 MΩ. Data Sheet S15418EJ2V0DS 21 µ PD3768 [ M E MO ] 22 Data Sheet S15418EJ2V0DS µ PD3768 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet S15418EJ2V0DS 23 µ PD3768 • The information in this document is current as of September, 2002. The information is subject to change without notice. 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