DATA SHEET MOS INTEGRATED CIRCUIT µPD75P238 4-BIT SINGLE CHIP MICROCOMPUTER DESCRIPTION The µPD75P238 is a version of the µPD75238 in which the on-chip mask ROM is replaced by one-time PROM or EPROM. The one-time PROM version can be written to once only, and is useful for short-run and multiple deviceproduction of sets and early start-up. Also, the EPROM version allows programs to be written and rewritten, and is thus ideal for system evaluation. Functions are described in detail in the following User's Manual, which should be read when carrying out design work. µPD75238 User's Manual : IEU-731 The µPD75P238 EPROM product does not provide a level of reliability suitable for use as a volume production product for users' devices. The EPROM product should be used solely for function evaluation in experiments of preproduction. FEATURES o µPD75238 pin compatible o On-chip PROM: 32640 × 8 o On-chip RAM: 1024 × 4 o High-voltage display outputs . S0 to S8 & T0 to T9 : Internal pull-down resistors . S9, S16 to S23 & T10 to T15: Open-drain o Drive capability in same supply voltage range as mask version µPD75238 (2.7 to 6.0 V) o Ports 4 & 5: No pull-up resistor o Port 7: No pull-down resistor Note No internal pull-up and pull-down resistor function by mask option. USE VCR, Audio-visual, ECR, Microwave oven ORDERING INFORMATION Ordering Code µ PD75P238GJ-5BG µ PD75P238KF Package 94-pin plastic QFP(■ ■ 20 mm) 94-pin ceramic WQFN On-Chip ROM Quality Grade One-time PROM EPROM Standard Standard Please refer to “Quality grade on NEC Semiconductor Devices” (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. This manual describes common parts of One-time PROM and EPROM products as PROM. The information in this document is subject to change without notice. Document No. IC-2596A (O.D. No. IC-8014A) Date Published February 1994 P Printed in Japan The mark ★ shows major revised points. © NEC Corporation 1992 µPD75P238 94 93 92919089 S18/P102 S19/P103 S20/P110 S21/P111 S22/P112 S23/P113 S0/P120 S1/P121 S2/P122 Note P22/PCL P23/BUZ P30/MD0 P31/MD1 P43 VSS 64 63 62 61 60 59 P50 P51 P52 P53 P60 P61 58 57 56 55 54 53 52 51 50 P62 P63 P70 P71 P72 P73 P80/PPO P81/SCK1 P82/SO1 49 48 44 45 46 47 Ensure that power is supplied to the VDD and VSS pins (pins 4, 11, 30, 48, and 65). Remarks 2 P10 /INT0 P11/INT1 P12/INT2 P13/TI0 P20/PTO0 P21 21 22 23 24 25262728 293031 3233 343536373839404142 43 S4/P130 S3/P123 19 20 71 70 69 68 67 66 65 PH3/T10/S15/P153 T9 T8 T7 T6 T5 T4 T3 T2 T1 T0 S16/P100 S17/P101 10 11 12 13 14 15 16 17 18 µPD75P238GJ- 5BG VSS 6 7 8 9 µPD75P238KF X1 IC XT2 XT1 4 5 T15/S10/P142 T14/S11/P143 PH0/T13/S12/P150 PH1/T12/S13/P151 PH2/T11/S14/P152 X2 2 3 S7/P133 S8/P140 S9/P141 VDD VLOAD AVDD VDD VPP 87 868584 8382 81807978777675747372 88 1 S5/P131 S6/P132 AN0 AVREF RESET P00/INT4 P01/SCK0 P02/SO0/SB0 P03/SI0/SB1 AN4/P90 AN5/P91 AN6/P92 AN7/P93 AVSS AN2 AN3 AN1 PIN CONFIGURATION (TOP VIEW) IC (Internally Connected) pins should be connected directly to VSS. P32/MD2 P33/MD3 P40 P41 P42 P83/SI1 VDD µPD75P238 PIN NAME P00 P10 P20 P30 to to to to P03 P13 P23 P33 : : : : Port0 Port1 Port2 Port3 SCK0, SCK1 SO0, SO1 SI0, SI1 SB0, SB1 P40 P50 P60 P70 to to to to P43 P53 P63 P73 : : : : Port4 Port5 Port6 Port7 INT0, INT1, INT4 : External Vectored Interrupt Input 0, 1, 4 INT2 : External Test Input 2 PPO : Programmable Pulse Output TI0 : Timer Input 0 P80 to P83 P90 to P93 P100 to P103 P110 to P113 : : : : Port8 Port9 Port10 Port11 PTO0 BUZ PCL AN0 to AN7 : : : : Programmable Timer Output 0 Buzzer Clock Programmable Clock Output Analog Input 0 to 7 P120 P130 P140 P150 : : : : Port12 Port13 Port14 Port15 AVREF AVDD AVSS X1, X2 : : : : Analog Reference Voltage Analog VDD Analog VSS Main System Clock Oscillation 1, 2 PH0 to PH3 T0 to T15 S0 to S23 VDD : : : : PortH Digit Output Segment Output Positive Power Supply XT1, XT2 RESET VPP MD0 to MD3 : : : : Subsystem Clock Oscillation 1, 2 Reset Programming Power Supply Mode Selection 0 to 3 VSS VLOAD : Ground IC : Power Supply for FIP Driver to to to to P123 P133 P143 P153 : : : : Serial Serial Serial Serial Clock I/O 0, 1 Data Output 0, 1 Data Input 0, 1 Bus I/O 0, 1 : Internally Connected 3 TIO INTBT TIMER/EVENT COUNTER #0 TI0/P13 PTO0/P20 PORT 0 4 P00-P03 PORT 1 4 P10-P13 SBS (2) PORT 2 4 P20-P23 BANK PORT 3 4 P30/MD0 -P33/MD3 PORT 4 4 P40-P43 PORT 5 4 P50-P53 PORT 6 4 P60-P63 PORT 7 4 P70-P73 PORT 8 4 P80-P83 PORT 9 4 P90-P93 SP (8) PROGRAM COUNTER (15) ALU CY INTT0 WATCH TIMER BUZ/P23 INTW TIMER/ PULSE GENELATOR PPO/P80 GENERAL REG. ROM PROGRAM MEMORY 32640 × 8 DECODE AND CONTROL INTTPG RAM DATA MEMORY 1024 × 4 SI0/SB1/P03 SERIAL INTERFACE SO0/SB0/P02 SCK0/P01 BLOCK DIAGRAM 4 BASIC INTERVAL TIMER INTCSI SI1/P83 SO1/P82 SERIAL INTERFACE 10 T0-T9 4 T10/S15/PH3/P153T13/S12/PH0/P150 2 T14/S11/ P143T15/S10/P142 SCK1/P81 N fX / 2 INT0/P10 INTERRUPT CONTROL INT1/P11 INT2/P12 CLOCK OUTPUT CONTROL CLOCK DIVIDER CLOCK GENERATOR SUB MAIN STAND BY CONTROL FIP CONTROLLER/ DRIVER CPU CLOCK Φ 10 S0/P120-S9/P141 8 S16/P100-S23/P113 INT4/P00 TI0 AVDD AVREF AVSS 8 XT1 XT2 X1 X2 VLOAD EVENT COUNTER PORT 10-15 A/D CONVERTER RESET VDD BIT SEQ. BUFFER(16) VSS VPP 24 P100-P153 µPD75P238 AN0-AN3 AN4/P90-AN7/P93 PCL/P22 µPD75P238 1. PIN FUNCTIONS 1.1 PORT PINS (1/2) Pin Name Input/Output P00 Dual-Function Pin 8-Bit I/O After Reset SCK0 Input P02 SO0/SB0 P03 SI0/SB1 P10 4-bit input port (PORT0). Internal pull-up resistor specification by software is possible for P01 to P03 as a 3bit unit. INT1 Input P12 INT2 P13 TI0 P20 PTO0 P21 — Input/output P22 PCL P23 BUZ × F –A Input F –B M –C With noise elimination function INT0 P11 Input/Output Circuit Type*1 B INT4 P01 * Function 4-bit input port (PORT1). Internal pull-up resistor specification by software is possible as a 4-bit unit. × Input B –C 4-bit input/output port (PORT2). Internal pull-up resistor specification by software is possible as a 4-bit unit. × Input E–B Programmable 4-bit input/output port (PORT3). Input/output settable bit-wise. Internal pull-up resistor specification by software is possible as a 4-bit unit. × Input E–C P30 to P33 *2 Input/output MD0 to MD3 P40 to P43 *2 Input/output — N-ch open-drain 4-bit input/output port (PORT4). Data input/output pins for program memory write/verify (low-order 4 bits). Input M–A Input M–A P50 to P53 *2 Input/output — N-ch open-drain 4-bit input/output port (PORT5). Data input/output pins for program memory write/verify (high-order 4 bits). P60 to P63 Input/output — Programmable 4-bit input/output port (PORT6). Input/output settable bit-wise. Internal pull-up resistor specification by software is possible as a 4-bit unit. Input E–C P70 to P73 Input/output — 4-bit input/output port (PORT7). Input E 1. A circle denotes Schmitt-triggerd input. 2. Direct LED drive capability 5 µPD75P238 1.1 PORT PINS (2/2) Pin Name Input/Output DualFunction Pin P80 Input/output PPO P81 Input/output SCK1 Function 8-Bit I/O After Reset Input/Output Circuit Type*1 A F 4-bit input port (PORT8). × Input P82 Input/output SO1 E P83 Input SI1 B P90 to P93 Input AN4 to AN7 4-bit input port (PORT9). P100 to P103 Output S16 to S19 P-ch open-drain 4-bit high-voltage output port. P110 to P113 Output S20 to S23 P-ch open-drain 4-bit high-voltage output port. P120 to P123 Output S0 to S3 P-ch open-drain 4-bit high-voltage output port. Internal pull-down resistors. × Input Y–A High impedance I–D I–E VLOAD level P130 to P133 Output P140 P141 S4 to S7 Output S9 S10/T15 P143*2 S11/T14 P150*2 S12/T13/PH0 P151*2 I–E P-ch open-drain 4-bit high-voltage output port. Internal pull-down resistor on P140 only. I–D High impedance S14/T11/PH2 P153*2 S15/T10/PH3 PH0 S12/T13/P150 Output I–D P-ch open-drain 4-bit high-voltage output port. P152*2 S13/T12/P151 P-ch open-drain 4-bit high-voltage output port. PH2 S14/T11/P152 PH3 S15/T10/P153 1. A circle denotes Schmitt-triggerd input. 2. Direct LED drive capability. 6 VLOAD level S13/T12/PH1 Output * I–E S8 P142*2 PH1 P-ch open-drain 4-bit high-voltage output port. Internal pull-down resistors. × High impedance I–D µPD75P238 1.2 NON-PORT PINS (1/2) Pin Name Input/Output DualFunction Pin PPO Output P80 Timer/pulse generator pulse output pin. TI0 Input P13 External event pulse input pin for timer/event counter #0 or event counter #1. PTO0 Output P20 Timer/event counter output pin. Input E–B PCL Output P22 Clock output pin. Input E–B BUZ Output P23 Fixed-frequency output pin (for buzzer or system clock trimming use). Input E–B SCK0 Input/output P01 Serial clock input/output pin. Input F –A SO0/SB0 Input/output P02 Serial data output pin. Serial bus input/output pin. Input F –B SI0/SB1 Input/output P03 Serial data input pin. Serial bus input/output pin. Input M –C INT4 Input P00 Edge-detected vectored interrupt input pin (either rising or falling edge detection). INT0 P10 Input INT1 Function Edge-detected vectored interrupt input pin (detected edge selectable). P11 Input/Output Circuit Type* Input A B –C B Clocked B –C Asynchronous INT2 Input P12 Edge-detection testable input pin (rising edge detection). SCK1 Input/output P81 Serial clock input/output pin. Input F SO1 Output P82 Serial data output pin. Input E SI1 Input P83 Serial data input pin. Input B Asynchronous AN0 to AN3 Y AN4 to AN7 AVREF P90 to P93 Y–A A/D converter reference voltage input pin. Input AV DD A/D converter power supply pin. AVSS A/D converter reference GND potential pin. Input XT1 Input Subsystem clock oscillation crystal resonator input. When an external clock is used, the clock is input to XT1 and XT2 is left open. RESET Input System reset input pin. MD0 to MD3 Input XT2 VPP Z Main system clock oscillation crystal/ceramic resonator input. When an external clock is used, the clock is input to X1 and the inverted clock to X2. X1, X2 IC B –C A/D converter analog input pin. Input * After Reset P30 to P33 Mode selection pin for program memory write/verify. B E–C ★ Internally Connected . Connect to VSS directly. Program voltage application pin for program memory write/verify . Connected to VDD in normal operation. Applies +12.5 V in program memory write/verify. A circle denotes Schmitt-triggerd input. 7 µPD75P238 1.2 NON-PORT PINS (2/2) Pin Name Input/Output DualFunction Pin Function VDD (3 pins) Positive power supply pins. Apply +6 V in PROM write/verify. VSS (2 pins) Ground potential pin. FIP controller/driver pull-down resistor connection/ power supply pin. VLOAD Digit output high-voltage large large-current output pins. Digit/segment output dual-function high-voltage largecurrent output pins. Unused pins usable as Port H. Usable as Port 15 in static mode. High impedance I–D Digit/segment output dual-function high-voltage largecurrent output pin. Usable as Port 14 in static mode. High impedance I–D P120 to P123 VLOAD level I–E P130 to P133 VLOAD level I–E VLOAD level I–E PH3/P153 to PH0/P150 T14/S11 P143 T15/S10 P142 Output S4 to S7 * Segment high-voltage output pins. Usable as Port 12 to Port 14 in static mode. S8 * P140 S9 P141 High impedance I–D S16 to S19 P100 to P103 High impedance I–D High impedance I–D S20 to S23 8 I–D I–E T10/S15 to T13/S12 S0 to S3 * Input/Output Circuit Type VLOAD level T0 to T9 * * After Reset Internal pull-down resistor P110 to P113 Segment high-voltage output pins. Usable as Port 10 & Port 11 in static mode. µPD75P238 1.3 PIN INPUT/OUTPUT CIRCUITS The input/output circuits for each of the pins are shown in Fig. 1-1 in partially simplified form. Fig. 1-1 Pin Input/Output Circuits (1/3) TYPE A TYPE D VDD VDD data P-ch OUT P-ch IN N-ch CMOS Standard Input Buffer TYPE B output disable N-ch Push-Pull Output with High Impedance Output Capability (P-ch and N-ch both OFF) TYPE E data IN/OUT Type D output disable IN Type A Schmitt-Triggered Input with Hysteresis Characteristics Input/Output Circuit Composed of Type D Push-Pull Output and Type A Input Buffer TYPE B-C TYPE E-B VDD VDD P.U.R. output disable P.U.R. P-ch P.U.R. enable P-ch data IN/OUT Type D output disable IN Type A P.U.R. : Pull-Up Resistor Schmitt-Triggered Input with Hysteresis Characteristics P.U.R.:Pull-Up Resistor 9 µPD75P238 Fig. 1-1 Pin Input/Output Circuits (2/3) TYPE E-C TYPE F-B VDD VDD P.U.R. P.U.R. P.U.R. enable P.U.R. enable P-ch data P-ch VDD output disable (P-ch) IN/OUT Type D P-ch IN/OUT data output disable output disable N-ch output disable (N-ch) Type A Type B P.U.R.:Pull-Up Resistor P.U.R.:Pull-Up Resistor TYPE F-C TYPE F VDD data P.U.R. IN/OUT Type D P.U.R. enable output disable P-ch data Type B IN/OUT Type D output disable Type B Input /Output Circuit Composed of Type D Push- P.U.R.:Pull-Up Resistor Pull Output and Type B Schmitt-Triggered Input TYPE F-A TYPE I-D VDD P.U.R. P.U.R. enable VDD P-ch data data P-ch IN/OUT output disable N-ch Type B P.U.R.:Pull-Up Resistor P-ch OUT Type D 10 VDD µPD75P238 Fig. 1-1 Pin Input/Output Circuits (3/3) TYPE Y TYPE I-E VDD VDD P-ch data P-ch P-ch AVDD IN OUT AVDD Sampling C N-ch P.D.R AVSS N-ch + AVSS VLOAD AVSS Reference Voltage (From Series Resistance String Voltage Tap) P.D.R: Pull-Down Resistor TYPE Y-A TYPE M-A IN/OUT data N-ch P-ch output disable AVDD IN AVDD Sampling C N-ch AVSS + AVSS Middle-High Voltage Input Buffer AVSS Reference Voltage (From Series Resistance String Voltage Tap) P.U.R.:Pull-Up Resistor P.U.R: Pull-Up Resistor TYPE M-C TYPE Z VDD P.U.R. P.U.R. enable P-ch IN/OUT data N-ch output disable Type B AVSS P.U.R: Pull-Up Resistor P.U.R.:Pull-Up Resistor 11 µPD75P238 1.4 DISPOSITION OF UNUSED PIN Table 1-2 Recommended Commection of Unused Pins (1/2) Pin P00/INT4 Recommended Connection Connect to VSS. P01/SCK0 P02/SO0/SB0 Connect to VSS or VDD. P03/SI1/SB1 P10/INT0 to P12/INT2 Connect to VSS. P13/TI0 P20/PTO0 P21 P22/PCL P23/BUZ P30 to P33 Input state : Output state : Connect to VSS or VDD. Leave open. P40 to P43 P50 to P53 P60 to P63 P70 to P73 P80 to PPO P81 to SCK1 Connect to VSS or VDD. P82/SO1 P83/SI1 P90/AN4 to P93/AN7 12 Connect to VSS. µPD75P238 Table 1-2 Recommended Commection of Unused Pins (2/2) Recommended Connection Pin P100/S16 to P103/S19 P110/S20 to P113/S23 P120 to P123 Leave open. P130 to P133 P140 to P143 P150 to P153 AN0 to AN3 Connect to VSS. AV REF AV DD Connect to VDD. AV SS Connect to VSS. XT1 Connect to VSS or VDD. XT2 Leave open. VLOAD Connect to VSS or leave open. IC Connect to VSS. ★ 13 µPD75P238 2. DIFFERENCES BETWEEN µPD75P238 AND µPD75238 The µPD75P238 is a product with the program memory of the µPD75238 using on-chip mask ROM replaced by one-time PROM or EPROM. Table 2-1 shows differences between µPD75P238 and µPD75238. The differences between these products must be thoroughly checked when, for example, switching from use of PROM for application system debugging and reproduction to use of a mask ROM product for volume production. For details of CPU function and on-chip hardware, refer to the document "µPD75238 User's Manual" (IEU-731). Table 2-1 Differences between µPD75P238 and µPD75238 Product Name Parameter µPD75238 µPD75P238 Mask ROM 32K × 8 ROM One-time PROM, EPROM 32K × 8 1K × 4 RAM FIP controller/ driver No. of segments 9 to 24 No. of digits 9 to16 Pull-up resistors Ports 4 & 5 No Port 7 No On-chip S0 to S8 S9 Pull-down resistors No Mask option No S16 to S23 On-chip T0 to T9 No T10 to T15 Pin 5 VDD VPP Pin connection Pins 70 to 73 ★ Electrical specifications The mask ROM products and PROM products have different consumption currents, operating temperature range etc. See the Electrical Specifications section in the relevant Data Sheet for details. 2.7 to 6.0 V Operating supply voltage range Subsystem clock feedback resistor ★ ★ P30/MD0 to P33/MD3 P30 to P33 Mask option On-chip 94-pin plastic QFP (■ ■ 20 mm) 94-pin ceramic WQFN Package 94-pin plastic QFP (■ ■ 20 mm) Others The mask ROM products and PROM products have different circuit scales and mask layouts, and therefore differ in terms of noise resistance and noise radiation. Note Noise resistance and noise radiation differs between the PROM products and mask ROM products. When investigating a switch from preproduction to volume production, throughout evaluation should be carried out with the mask ROM CS product (not the ES product). 14 µPD75P238 3. PROGRAM MEMORY (PROM) The program memory is PROM with a 32640 × 8-bit configuration wich stores program and table tata etc. The program memory is addressed by the program counter. In addition, table data can be referenced by a table referencing instruction (MOVT). The rage of address to which branch instructions and subroutine call instructions and subroutine call instructions and subroutine call instructions can branch is shown in Fig. 3-1. The entire space comprising 0000H to 7F7FH can be directly branched to by the entire-space branch instruction (BRA !addr1) and the entire-space call instruction (CALLA !addr1). The relative branch instruction (BR $addr) allows branching to addresses [PC contents –15 to –1 and +2 to +16] irrespective of block boundaries. In addition, the following addresses are specially allocated (except for 0000H and 0001H, the entire area can be used as ordinary program memory). • Addresses 0000H & 0001H Vector table to which the program start address and MBE & RBE set value upon RESET input are written. Reset servicing can be started from any address in the 16K (000H to 3FFFH). • Addresses 0002H to 000FH Vector table to which the program start address and MBE & RBE set value for the various vectore interrupts are written. Interrupt servicing can be started from any address in the 16K space (0000H to 3FFFH). • Addresses 0020H to 007FH Table area referenced by GETI instruction*. * The GETI instruction allows any 2- or 3-byte instruction or any two 1-byte instructions to be implemented as 1 byte, and is used to reduce the number of program steps. 15 µPD75P238 Fig. 3-1 Program Memory Map 7 0 6 Internal Reset Start Address (High-Order 6 Bits) 0000H MBE RBE 0002H MBE RBE INTBT/INT4 Start Address (High-Order 6 Bits) (Low-Order 8 Bits) BRA !addr Instruction Branch Address (Low-Order 8 Bits) 0004H MBE RBE INT0 Start Address (High-Order 6 Bits) (Low-Order 8 Bits) 0006H MBE RBE INT1 Start Address (High-Order 6 Bits) BR !addr Instruction Branch Address (Low-Order 8 Bits) 0008H CALLF ! faddr Instruction Entry Address MBE RBE INTSO Start Address (High-Order 6 Bits) (Low-Order 8 Bits) 000AH MBE RBE INTT0 Start Address (High-Order 6 Bits) (Low-Order 8 Bits) 000CH CALL !addr Instruction Branch Address MBE RBE INTTPG Start Address (High-Order 6 Bits) (Low-Order 8 Bits) 000EH MBE RBE BRCB ! caddr Instruction Branch Address INTKS Start Address (High-Order 6 Bits) (Low-Order 8 Bits) ≈ 0020H ≈ ≈ ≈ 0FFFH 1000H ≈ ≈ 1FFFH 2000H ≈ ≈ BRCB !caddr instruction Branch Address 2FFFH 3000H ≈ ≈ BRCB !caddr instruction Branch Address 3FFFH 4000H ≈ ≈ 4FFFH 5000H ≈ ≈ 5FFFH 6000H ≈ ≈ ≈ ≈ 07FFH 0800H 6FFFH 7000H BR $addr Instruction Relative Branch Address (-15 to -1, +2 to +16) Branch/Call Addresses by GETI GETI Instruction Reference Table ≈ 007FH 0080H CALLA !addr Instruction Branch Address BRCB !caddr instruction Branch Address BRCB !caddr instruction Branch Address BRCB !caddr instruction Branch Address BRCB !caddr instruction Branch Address BRCB !caddr instruction Branch Address 7F7FH Note The above interrupt vector start addresses are 14-bit, and thus should be set in the 16K space (0000H to 3FFFH). Remarks In addition to the above, branching is possible with the BR PCDE and BR PCXA instructions to addresses with the low-order 8 bits only of the PC modified. 16 µPD75P238 4. STACK BANK SELECTION REGISTER (SBS) The stack bank selection register specifies one memory bank from memory banks 0 to 3 as the stack area.Its format is shown in Fig. 4-1. The stack bank selection register is set by a 4-bit memory manipuration instruction. On RESET input bit only is set to "1" and the remaining bits are undefined. Therefore this register must always be initialized to 00××B* at the start of a program. Fig. 4-1 Stack Bank Selection Register Format Address F84H 3 2 1 0 SBS3 SBS2 SBS1 SBS0 Symbol SBS Stack Area Specification 0 0 Memory bank 0 0 1 Memory bank 1 1 0 Memory bank 2 1 1 Memory bank 3 0 0 Ensure that 0 is written to bits 2 & 3. Note After RESET input a subroutine call instruction and interrupt enabling instruction should be executed after setting the stack bank selection register. * ×× should be set to the desired value. 17 µPD75P238 5. PROGRAM MEMORY WRITE AND VERIFY OPERATIONS The program memory incorporated in the µ PD75P238 is 32640 × 8-bit electrically writable PROM. Write/verify operations on this PROM are executed using the pins shown in the table below. Address updating is performed by means of clock input from the X1 pin rather than by address input. Table 5-1 Pins Used for Program Memory Write/Verify Pin Name Function VPP Voltage applecation pin for program memory write/verify (normally VDD potential). X1, X2 Address update clock input for program memory write/verify. Inverse of X1 pin signal is input to X2 pin. MD0 to MD3 Operating mode selection pin for program memory write/verify. P40 to P43 (low-order 4 bits) P50 to P53 (high-order 4 bits) 8-bit data input/output pin for progrm memory write/verify. VDD Supply voltage application pin. Applies 2.7 to 6.0 V in normal operation, and 6 V for program memory write/verify. Note 1. Pins not used in a program memory write/verify operation are handled as follows: Ports 0 to 2, ports 6 to 15 T0 to T9, AN0 to AN3, XT1 • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • Connect to GND VLOAD, AVREF, AVSS, RESET AVDD • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • Connect to VDD XT2 • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • Leave open 2. On the µPD75P238KF which is equipped with an erase window the shading cover film should be attached except when performing EPROM erasure. 3. Since the µPD75P238GJ one-time PROM version is not provided with an erase window, program memory contents cannot be erased. 18 µPD75P238 5.1 PROGRAM MEMORY WRITE/VERIFY OPERATING MODES When +6 V is applied to the VDD pin and +12.5 V to the VPP pin, the µPD75P238 enters the program memory write/ verify mode. This mode comprises one of the operating modes shown in Table 5-2 according to the setting of pins MD0 to MD3. Table 5-2 Program Memory Write/Verify Operating Modes Operating Mode Setting Operating Mode VPP + 12.5 V Remarks VDD MD0 MD1 MD2 MD3 H L H L Program memory address zero-clear L H H H Write mode L L H H Verify mode H × H H Program inhibit mode +6V × : L or H 19 µPD75P238 5.2 PROGRAM MEMORY WRITE PROCEDURE The procedure for writing to program memory is as shown below, allowing high-speed writing. (1) Unused pins are connected to VSS. The X1 pin is driven low. (2) 5 V is supplied to the VDD and VPP pins. (3) (4) (5) (6) 10 µs wait. Program memory address zero-clear mode. 6V is supplied to VDD, 12.5 V to VPP. Program inhibit mode. (7) (8) (9) (10) Data is written in 1 ms write mode. Program inhibit mode. Verify mode. If write is successful go to (10), otherwise repeat (7) to (9). (Number of times written in (7) to (9): X) × 1 ms additional writes. (11) (12) (13) (14) Program inhibit mode. Program memory address is updated (+1) by inputting 4 pulses to the X1 pin. Steps (7) to (12) are repeated until the last address. Program memory address zero-clear mode. (15) V DD / VPP pin voltage is changed to 5 V. (16) Power-off. Steps (2) to (12) of this procedure are shown in Fig. 5-1. Fig. 5-1 Program Memory Write Timing Repeated X Times Write ≈ VPP Additional Write Verify VPP VDD ≈ VDD + 1 VDD VDD ≈ X1 Data Output MD0 Data Input ≈ 0 to P53 ≈ P40 to P43 ≈ (P30) MD1 ≈ (P31) MD2 ≈ (P32) MD3 (P33) 20 Data Input Address Increment µPD75P238 5.3 PROGRAM MEMORY READ PROCEDURE µPD75P238 program memory contents can be read using the following procedure. Reading is performed in verify mode. (1) Unused pins are connected to VSS. The X1 pin is driven low. (2) 5 V is supplied to the VDD and VPP pins. (3) 10 µs wait. (4) (5) (6) (7) Program memory address zero-clear mode. 6 V supplied to VDD, and 12.5 V to VPP. Program inhibit mode. Verify mode. When clock pulses are input to the X1 pin, data is output sequentially, one address per 4-pulse-input cycle. (8) Program inhibit mode. (9) Program memory address zero-clear mode. (10) VDD / VPP pin voltage is changed to 5 V. (11) Power-off. Steps (2) to (9) of this procedure are shown in Fig. 5-2. Fig. 5-2 Program Memory Read Timing ≈ VPP VPP ≈ VDD VDD +1 VDD VDD ≈ X1 Data Output Data Output ≈ P50 to P53 ≈ P40 to P43 (P30) MD1 "L" ≈ ≈ MD0 ≈ (P31) MD2 ≈ (P32) MD3 (P33) 21 µPD75P238 5.4 ERASURE (µPD75P238KF ONLY) The Programmed data contents of the µPD75P238KF can be erased by exposure to ultraviolet light through the window in the top. The ultraviolet wave length which effects erasure is 250 nm, and the quantity of radiation necesary for complete erasure is 15 W•s/ cm2 (ultraviolet radiation intensity x erasure time). Using a commercially available ultraviolet lamp (254 nm vavelength, 12 mW/cm 2 intensity) erasure can be accomplished in approximately 15 to 20 minutes. Note 1. Memory contents may also be erased by prolonged exposure to direct sunlight fluorescent lighting. To protect the contents ensure that the top window is masked with the shading cover film. The shading cover film supplied with NEC's UV EPROM products should be used. 2. When carrying out erasure the distance between the ultraviolet lamp and the µPD75P238KF should normally be no greater than 2.5 cm. Remarks 22 A longer erasure time may be required if there is deterioration of the ultraviolet lamp, or if the package window is not clean, etc. µPD75P238 6. ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS (Ta = 25°C) PARAMETER SYMBOL TEST CONDITIONS RATING UNIT –0.3 to +7.0 V VDD –40 to VDD +0.3 V –0.3 to +13.5 V –0.3 to V DD +0.3 V –0.3 to +11 V –0.3 to V DD +0.3 V VDD –40 to VDD +0.3 V 1 pin except display output pins –15 mA S0 to S9, S16 to S23 1 pin –15 mA T0 to T15 1 pin –30 mA All pins except display output pins –30 mA –120 mA Peak value 30 mA Effective value 15 mA Peak value 100 mA Effective value 60 mA Peak value 100 mA 60 mA VDD Supply voltage VLOAD VPP VI1 Except ports 4, 5 VI2 Ports 4, 5 VO Pins except display output pins VOD Display output pins Input voltage Open-drain Output voltage Output current high IOH All display output pins 1 pin Output current low IOL* Total of port 0, 2, 3, 4 Total of port 5 to 8 Effective value * Operating temperature Topt –40 to +70 °C Storage temperature Tstg –65 to +150 °C The Effective value should be calculated as follows. [Effective value] = [Peak value] × Note Duty Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter, or even momentarily. In other words, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under ★ conditions which ensure that the absolute ratings are not exceeded. 23 µPD75P238 OPERATING SUPPLY VOLTAGE RANGE (Ta = –40 to +70 °C) PARAMETER MIN. MAX. UNIT CPU*1 *2 6.0 V Display controller 4.5 6.0 V Timer/pulse generator 4.5 6.0 V Other hardware*1 2.7 6.0 V * 1. 2. 24 TEST CONDITIONS Except the system clock oscillator, display controller and timer/pulse generator. The operating power supply voltage range varies depending on the cycle time. Refer to the section describing AC characteristics. µPD75P238 MAIN SYSTEM CLOCK RESONATOR CHARACTERISTICS (Ta = –40 to +70 °C, VDD = 2.7 to 6.0 V) RESONATOR RECOMMENDED CHARACTERISTICS X1 Oscillator frequency (fx)*1 X2 Ceramic resonator C1 C2 X1 Crystal resonator C2 X1 Oscillation stabilization time*2 TEST CONDITIONS VDD = Oscillator voltage range X2 External Clock µPD74HCU04 Oscillation stabilization time*2 MIN. TYP. 2.0 After VDD has reached MIN. value of oscillator voltage range. Oscillator frequency (fx)*1 X2 C1 PARAMETER 2.0 VDD = 4.5 to 6.0 V 4.19 MAX. UNIT 6.2 MHz 4 ms 6.2 MHz 10 ms 30 ms X1 input frequency (fx)*1 2.0 6.2 MHz X1 input high and low level width (tXH, tXL) 81 250 ns * 1. Oscillator frequency and input frequency indicate oscillator characteristics only. Refer to the AC characteristics for the instruction execution time. 2. Oscillation stability time is time required for oscillation to stabilize after VDD has reached the MIN. value in oscillation voltage range or STOP mode has been released. Note ★ When the main system clock oscillator is used, the following should be noted concerning wiring in the area in the figure enclosed by a dotted line to prevent the influence of wiring capacitance, etc. • The wiring should be kept as short as possible. • No other signal lines should be crossed. • Keep away from lines caring a high fluctuating current. • The oscillator capacitor grounding point should always be at the same potential as VSS. Do not connect to a ground pattern carrying a high current. • A signal should not be taken from the oscillator. 25 µPD75P238 SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS (Ta = –40 to +70 °C, VDD = 2.7 to 6.0 V) RECOMMENDED CHARACTERISTICS RESONATOR XT1 C4 XT1 MIN. TYP. MAX. UNIT 32 32.768 35 kHz 1.0 2 s 10 s VDD = 4.5 to 6.0 V R C3 TEST CONDITIONS Oscillator frequency (f XT)*1 XT2 Crystal resonator PARAMETER Oscillation stabilization time*1 XT1 input frequency (f XT)*1 32 100 kHz X1 input high and low level width (tXTH, tXTL ) 5 15 µs XT2 External Clock * 1. 2. ★ Note Oscillator frequency and input frequency indicate oscillator characteristics only. Refer to the AC characteristics for the instruction execution time. Oscillation stability time is time required for oscillation to stabilize after VDD has reached the MIN. value in oscillation voltage range. When subsystem clock oscillator is used, the following should be noted concerning wiring in the area in the figure enclosed by a dotted line to prevent the influence of wiring capacitance, etc. • The wiring should be kept as short as possible. • No other signal lines should be crossed. • Keep away from lines caring a high fluctuating current. • The oscillator capacitor grounding point should always be at the same potential as VSS. Do not connect to a ground pattern carrying a high current. • A signal should not be taken from the oscillator. The subsystem clock oscillator is a low-amplitude circuit in order to achieve a low consumption current, and is more prone to misoperation due to noise than the main system, clock oscillator. Particular care is therefore required with the wiring method when the subsystem clock is used. CAPACITANCE (Ta =25 °C, VDD = 0 V) PARAMETER Input capacitance Output capacitance (Output except display output) SYMBOL CI CO Input/output capacitance CIO Output capacitance (Display output) CO 26 TEST CONDITIONS f = 1 MHz 0 V for pins except measured pins MIN. TYP. MAX. UNIT 15 pF 15 pF 15 pF 35 pF µPD75P238 RECOMMENDED OSCILLATOR CONTANTS MAINSYSTEMCLOCK : CERAMIC RESONATOR (Ta = – 40 to + 85 °C) MAUNFACTURER PRODUCT NAME CSA2.0MG ---------------------------- FREQUENCY (MHz) 2.0 CST2.0MG CSA2.5MG093 ---------------------------CST2.5MGW093 2.5 CSA4.19MGU Murata Mfg. ---------------------------CST4.19MGWU 4.19 CSA2.5MG ---------------------------CST2.5MGW 2.5 CSA4.19MG ---------------------------CST4.19MGW 4.19 CSA6.0MG ---------------------------CST6.0MGW 6.00 RECOMMENDED OSCILLATOR CONSTANTS(pF) C1 C2 30 30 – – 30 30 – – 30 30 – – 30 30 – – 30 30 – – 30 30 – – OSCILLATOR VOLTAGE RANGE(V) MIN. MAX. -------------------------- -------------------------- --------------------------------------On-chip capacitor product 2.7 6.0 -------------------------- -------------------------- --------------------------------------On-chip capacitor product --------------------------------------- -------------------------- -------------------------- REMARKS On-chip capacitor product 3.0 6.0 --------------------------------------On-chip capacitor product 3.3 6.0 --------------------------------------On-chip capacitor product 4.0 6.0 --------------------------------------On-chip capacitor product MAIN SYSTEM CLOCK : CRYSTAL RESONATOR (Ta = – 20 to + 70 °C) MAUNFACTURER Kinseki, Ltd. PRODUCT NAME HC-49/U-S FREQUENCY (MHz) 3.072 to 6.000 RECOMMENDED OSCILLATOR CONSTANTS(pF) OSCILLATOR VOLTAGE RANGE(V) C1 C2 MIN. MAX. 22 22 4.0 6.0 REMARKS 27 µPD75P238 DC CHARACTERISTICS (Ta = –40 to +70 °C, VDD = 2.7 to 6.0 V) (1/3) PARAMETER Input voltage high SYMBOL Output voltage high UNIT VDD V VIH2 Port 0, 1, RESET, P81, P83 0.8 VDD VDD V VIH3 X1, X2, XT1 VDD –0.4 VDD V 0.65 VDD VDD V 0.7 VDD VDD V 0.7 VDD 10 V Port 7 VDD = 4.5 to 6.0 V VIH5 Port 4, 5 VIL1 All ports and pins except those listed below. 0 0.3 VDD V VIL2 Port 0, 1, RESET, P81, P83 0 0.2 VDD V VIL3 X1, X2, XT1 0 0.4 V VOH All output pins, except port 4, 5 and P03 VOL ILIH1 Input leakage current high All output pins All ports and pins except those listed below. ILIH2 X1, X2, XT1 ILIH3 Ports 4, 5 ILIL1 All ports and pins except those listed below. ILIL2 28 MAX. 0.7 VDD SB0, SB1 Input leakage current low TYP. All ports and pins except those listed below. Ports 3, 4, 5 Output voltage low MIN. VIH1 VIH4 Input voltage low TEST CONDITIONS X1, X2, XT1 Open-drain VDD = 4.5 to 6.0 V IOH = –1 mA VDD –1.0 V VDD = 2.7 IOH = to 6.0 V –100 µA V VDD = 4.5 IOH = 15 mA to 6.0 V VDD –0.5 2.0 V VDD = 4.5 IOL = to 6.0 V 1.6 mA 0.4 V VDD = 2.7 IOL = to 6.0 V 400 µA 0.5 V 0.2 VDD V 3 µA 20 µA 20 µA –3 µA –20 µA Open-drain pull-up resistor ≥ 1 kΩ 0.4 VIN = VDD VIN = 10 V VIN = 0 V µPD75P238 DC CHARACTERISTICS (Ta = –40 to +70 °C, VDD = 2.7 to 6.0 V) (2/3) PARAMETER Output leakage current high SYMBOL µA ILOH2 Port 4, 5 VOUT = 10 V 20 µA ILOL1 All ports and pins except those listed below. VOUT = 0 V –3 µA ILOL2 Display output VOUT = VLOAD = VDD – 35 V –10 µA IOD S0 to S9, S16 to S23 VDD = 4.5 to 6.0 V VOD = VDD – 2 V RL Display output RV1 Port 0, 1, 2, 3, VDD = 5 V ± 10% 6 (Except P00) VIN = 0 V VDD = 3 V ± 10% 6MHz crystal oscillation C1 = C2 = 22 pF*4 VOD – VLOAD = 35 V Operating mode HALT mode IDD2 Power supply current*1 IDDI IDD2 4. UNIT 3 IDDI * 1. 2. 3. MAX. VOUT = VDD (Mask option) On-chip pull-up resistor TYP. ILOH1 T0 to T15 On-chip pull-down resistor MIN. All ports and pins except those listed below. Output leakage current low Display output current TEST CONDITIONS 4.19MHz crystal oscillation C1 = C2 = 22 pF*4 Operating mode HALT mode –3 –5.5 mA –15 –22 mA 25 50 135 kΩ 15 40 80 kΩ 300 kΩ 30 VDD = 5V ±10%*2 9 18 mA VDD = 3 V ±10%*3 1 3 mA VDD = 5 V ±10% 900 2700 µA VDD = 3 V ±10% 300 900 µA VDD = 5 V ±10%*2 5 15 mA VDD = 3 V ±10%*3 0.9 2.7 mA VDD = 5 V ±10% 600 1800 µA VDD = 3 V ±10% 200 600 µA Current to the on-chip pull-down resistor (pull-up) and power-on reset circuit (mask option) is not included. When the processor clock control register (PCC) is set to 0011 and is operated at high-speed mode. When the PCC register is set to 0000 and is operated in the low-speed mode. Includes the case where the subsystem clock oscillating. 29 µPD75P238 DC CHARACTERISTICS (Ta = –40 to +70 °C, VDD = 2.7 to 6.0 V) (3/3) PARAMETER SYMBOL IDD3 TEST CONDITIONS 32 kHz crystal oscillation*2 IDD4 Power supply current*1 32 kHz crystal oscillation*2 IDD6 TYP. MAX. UNIT Operating mode VDD = 3 V ±10% 100 300 µA HALT mode VDD = 3 V ±10% 20 60 µA 0.5 20 µA 0.3 10 µA 5 µA 15 µA VDD = 5 V ±10% XT1 = 0 V STOP mode IDD5 * 1. 2. MIN. VDD = 3 V ±10% STOP mode Ta = 25°C VDD = 3 V ±10% 5 Current to the on-chip pull-down resistor (pull-up) and power-on reset circuit (mask option) is not included. When the system clock control register (SCC) is set to 1001 and is operated with the subsystem clock with main system clock oscillation stopped. A/D CONVERTER CHARACTERISTICS (Ta = –40 to +70 °C, VDD = 2.7 to 6.0 V, AVSS = VSS = 0 V, 2.7 ≤ AVDD ≤ VDD) PARAMETER SYMBOL TEST CONDITIONS Resolution Absolute accuracy*1 2.5 V ≤ AVREF ≤ V DD MIN. TYP. MAX. UNIT 8 8 8 bit –10 ≤ Ta ≤ +70°C ±1.5 –40 ≤ Ta < –10°C ±2.0 LSB Conversion time tCONV *2 168/fX µs Sampling time tSAMP *3 44/f X µs Analog input voltage VIAN AVREF V Analog input impedance RAN 1000 AVREF current IAREF 1.0 AVSS MΩ 2.0 mA * 1. 2. Absolute accuracy except quantization error (±1/2 LSB). Time from execution of conversion start instruction to EOC = 1 (28.0 µs when fX = 6.0 MHz, 40.1 µs when fX = 4.19 MHz) 3. Time from execution of conversion start instruction to the end of sampling (7.33 µ s when fX = 6.0 MHz, 10.5 µs when fX = 4.19 MHz) 30 µPD75P238 AC CHARACTERISTICS (Ta = –40 to +70 °C, VDD = 2.7 to 6.0 V) (1) Basic Operation PARAMETER CPU clock cycle time (minimum instruction execution time = one machine cycle)*1 SYMBOL tCY TEST CONDITIONS Operation with main system clock MIN. VDD = 4.75 to 6.0 V Operation with subsystem clock MAX. UNIT 0.67 64 µs 2.6 64 µs 125 µs 0 1 MHz 0 275 kHz 114 VDD = 4.5 to 6.0 V TI0 input frequency TYP. 122 fTI TI0 input high and low-level widths tTIH, tTIL Interrupt input high and low-level widths tINTH, tINTL RESET low level widths tRSL 0.48 µs 1.8 µs INT0 *2 µs INT1, 2, 4 10 µs 10 µs VDD = 4.5 to 6.0 V tcy vs VDD (When main system clock is in operation) * 1. CPU clock (Φ) cycle time is determined by the oscillator for frequency of the connected oscillator, the system clock control register (SCC) and processor clock control register (PCC). The cycle time tCY characteristics for supply voltage 64 60 6 5 Operation Guaranteed Range 4 Cycle Time tcy [µs] VDD when the main system clock is in operation is shown on the right. 2. 2tCY or 128/f X is set by interrupt mode register (IM0) setting. 70 3 2 1 0.5 0 1 2 3 4 5 6 Power Supply Voltage VDD [V] 31 µPD75P238 (2) Serial Transfer Operation (a) 2-Wired and 3-Wired Serial I/O Modes (SCK ... Internal clock output) PARAMETER SYMBOL TEST CONDITIONS VDD = 4.5 to 6.0 V SCK cycle time tKCY1 TYP. MAX. UNIT fX = 6.0 MHz 1340 ns fX = 4.19 MHz 1600 ns fX = 6.0 MHz 2680 ns fX = 4.19 MHz 3800 ns (tKCY1/2) -50 ns (tKCY1/2) -150 ns VDD = 4.5 to 6.0 V SCK high and low level widths MIN. tKL1 tKH1 SI setup time (to SCK↑) tSIK1 150 ns SI hold time (from SCK↑) tKSI1 400 ns SO output delay time from SCK↓ tKSO1 RL = 1 kΩ , CL = 100 pF* VDD = 4.5 to 6.0 V 250 ns 1000 ns MAX. UNIT * RL and CL denote load resistor and load capacitance of SO output line. (b) 2-Wired and 3-Wired Serial I/O Modes (SCK ... External clock input) PARAMETER SYMBOL TEST CONDITIONS VDD = 4.5 to 6.0 V SCK cycle time MIN. TYP. 800 ns 3200 ns 400 ns 1600 ns tKCY2 VDD = 4.5 to 6.0 V SCK high and low level widths tKL2 tKH2 SI setup time (to SCK↑) tSIK2 100 ns SI hold time (from SCK↑) tKSI2 400 ns SO output delay time from SCK↓ tKSO2 RL = 1 kΩ , CL = 100 pF* VDD = 4.5 to 6.0 V * RL and CL denote load resistor and load capacitance of SO output line. 32 300 ns 1000 ns µPD75P238 (c) SBI Mode (SCK ... Internal clock output (Master)) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT fX = 6.0 MHz 1340 ns fX = 4.19 MHz 1600 ns fX = 6.0 MHz 2680 ns fX = 4.19 MHz 3800 ns tKCY3/2-50 ns tKCY3/2-150 ns VDD = 4.5 to 6.0 V SCK cycle time tKCY3 VDD = 4.5 to 6.0 V SCK high and low level widths tKL3 tKH3 SB0, 1 setup time (to SCK ↑) tSIK3 150 ns SB0, 1 hold time (from SCK ↑) tKSI3 tKCY3/2 ns SB0, 1 output delay time from SCK ↓ tKSO3 SB0, 1 ↓ from SCK ↑ tKSB tKCY3 ns SCK from SB0, 1 ↓ tSBK tKCY3 ns SB0, 1 low level widths tSBL tKCY3 ns SB0, 1 high level widths tSBH tKCY3 ns RL = 1 kΩ, CL = 100 pF* VDD = 4.5 to 6.0 V 0 250 ns 0 1000 ns * RL and CL denote load resistor and load capacitance of SO output lines. 33 µPD75P238 (d) SBI Mode (SCK ... External clock input (Slave)) PARAMETER SCK cycle time SCK high and low level widths SYMBOL tKCY4 tKL4 tKH4 TEST CONDITIONS VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V MIN. TYP. MAX. UNIT 800 ns 3200 ns 400 ns 1600 ns SB0, 1 setup time (to SCK ↑) tSIK4 100 ns SB0, 1 hold time (from SCK ↑) tKSI4 tKCY4/2 ns SB0, 1 output delay time from SCK ↓ tKSO4 RL = 1 kΩ CL = 100 pF* VDD = 4.5 to 6.0 V 0 300 ns 0 1000 ns SB0, 1 ↓ from SCK ↑ tKSB tKCY4 ns SCK ↓ from SB0, 1 ↓ tSBK tKCY4 ns SB0, 1 low level widths tSBL tKCY4 ns SB0, 1 high level widths tSBH tKCY4 ns * RL and CL denote load resistor and load capacitance of SO output lines. 34 µPD75P238 AC Timing Test Points (Except X1 and XT1 Inputs) 0.8 VDD 0.8 VDD Test Points 0.2 VDD 0.2 VDD Clock Timings 1/fX tXL tXH VDD -0.5 V 0.4 V X1 Input 1/fXT tXTL tXTH VDD -0.5 V 0.4 V XT1 Input TI0 Timing 1/fTI tTIL tTIH TI0 35 µPD75P238 Serial Transfer Timing 3-wired serial I/O mode: tKCY1 tKL1 tKH1 SCK tSIK1 tKSI1 Input Data SI tKSO1 SO Output Data 2-wired serial I/O mode: tKCY2 tKL2 tKH2 SCK tKSO2 SB0,1 36 tSIK2 tKSI2 µPD75P238 Serial Transfer Timing Bus release signal transfer: tKL3,4 tKCY3,4 tKH3,4 SCK tKSB tSBL tSBH tSIK3,4 tSBK tKSI3,4 SB0,1 tKSO3,4 Command signal transfer: tKL3,4 tKCY3,4 tKH3,4 SCK tKSB tSIK3,4 tSBK tKSI3,4 SB0,1 tKSO3,4 Interrupt Input Timing tINTL tINTH INT0,1,2,4 RESET Input Timing tRSL RESET 37 µPD75P238 DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (Ta = –40 to 70 °C) PARAMETER SYMBOL Data retention power supply voltage VDDDR Data retention power supply current*1 IDDDR Release signal set time tSREL Oscillation stabilization wait time*2 tWAIT * 1. 2. 3. BTM3 TEST CONDITIONS MIN. MAX. 2.0 VDDDR = 2.0 V 0.1 Release by RESET Release by interrupt request UNIT 6.0 V 10 µA µs 0 217/fx ms *3 ms Current to the on-chip pull-up resistor and power-on reset circuit (mask option) is not included. Oscillation stability wait time is time to stop CPU operation to prevent unstable operation upon oscillation start. According to the setting of the basic interval timer mode register (BTM). (see below) BTM2 BTM1 Wait Time BTM0 Values at fX = 6.0 MHz in Parentheses 38 TYP. 20 Values at fX = 4.19 MHz in Parentheses — 0 0 0 2 /fx (approx. 175 ms) 220/fx (approx. 250 ms) — 0 1 1 217/fx (approx. 21.8 ms) 217/fx (approx. 31.3 ms) — 1 0 1 215/fx (approx. 5.46 ms) 215/fx (approx. 7.82 ms) — 1 1 1 213/fx (approx. 1.37 ms) 213/fx (approx. 1.95 ms) µPD75P238 Data Retention Timing (STOP mode release by RESET) HALT Mode STOP Mode Operating Mode Data Retention Mode VDD VDDDR tSREL STOP Instruction Execution Standby Release Signal (Interrupt Request) tWAIT Data Retention Timing (Standby release signal: STOP mode release by interrupt signal) Internal Reset Operation HALT Mode STOP Mode Operating Mode Data Retention Mode VDD VDDDR tSREL STOP Instruction Execution RESET tWAIT 39 µPD75P238 DC PROGRAMMING CHARACTERISTICS (Ta = 25 ±5 °C, VDD = 6.0 ±0.25 V, VPP = 12.5 ±0.3 V, VSS = 0 V) PARAMETER Input voltage high Input voltage low Input leakage current SYMBOL TEST CONDITIONS TYP. MAX. UNIT VIH1 Except X1 and X2 0.7 VDD VDD V VIH2 X1, X2 VDD –0.5 VDD V VIL1 Except X1 and X2 0 0.3 VDD V VIL2 X1, X2 0 0.4 V 10 µA ILI VIN = V IL or VIH Output voltage high VOH IOH = –1 mA Output voltage low VOL IOH = 1.6 mA VDD supply current IDD VPP supply current IPP Note MIN. VDD –1.0 V MD0 = VIL, MDI =VIH 0.4 V 30 mA 30 mA 1. VPP, including overshoot, should not exceed +13.5 V. 2. VDD should be applied before VPP and cut after VPP. AC PROGRAMMING CHARACTERISTICS (Ta = 25 ±5 °C, VDD = 6.0 ±0.25 V, VPP = 12.5 ±0.3 V, VSS = 0 V) (1/2) PARAMETER SYMBOL *1 TEST CONDITIONS MIN. TYP. MAX. UNIT Address setup time*2 (to MD0 ↓) tAS tAS 2 µs MD1 setup time (to MD0 ↓) tM1S tOES 2 µs Data setup time (to MD0 ↓) tDS tDS 2 µs Address hold time*2 (from MD0 ↑) tAH tAH 2 µs Data hold time (from MD0 ↑) tDH tDH 2 µs Data output float delay time from MD0 ↑ tDF tDF 0 VPP setup time (to MD3 ↑) tVPS tVPS 2 µs VDD setup time (to MD3 ↑) tVDS tVCS 2 µs Initial program pulse widths tPW tPW 0.95 Additional program pulse widths tOPW tOPW 0.95 MD0 setup time (to MD1 ↑) tMOS tCES 2 Data output delay time from MD0 ↓ tDV tDV * 1. 2. 40 MD0 = MD1 = VIL 130 1.0 ns 1.05 ms 21.0 ms µs 1 µs The corresponding µPD27C256 symbol. Internal address signal is incremented by one on the rise of fourth X1 input and is not connected to the pin. µPD75P238 AC PROGRAMMING CHARACTERISTICS (Ta = 25 ±5 °C, VDD = 6.0 ±0.25 V, VPP = 12.5 ±0.3 V, VSS = 0 V) (2/2) PARAMETER SYMBOL *1 TEST CONDITIONS MIN. TYP. MAX. UNIT MD1 hold time (from MD0 ↑) tM1H MD1 recovered time (to MD0 ↓) tM1R Program counter reset time tPCR X1 input high and low level widths tXH, tXL X1 input frequency fX Initial mode set time tI 2 µs MD3 setup time (to MD1 ↑) tM3S 2 µs MD3 hold time (from MD1 ↓) tM3H 2 µs MD3 setup time (to MD0 ↓) tM3SR When reading program memory 2 µs µs tOEH 2 µs 2 µs 10 µs 0.125 µs tM1H + tM1R ≥ 50 µs tOR 4.19 MHz Data output delay time from tDAD address*2 tACC When reading program memory 2 Data output hold time from address*2 tHAD tOH When reading program memory 0 MD3 hold time (from MD0↑) tM3HR When reading program memory 2 µs Data output float delay time from MD3↓ tDFR When reading program memory 2 µs * 1. 2. 130 ns The corresponding µPD27C256 symbol. Internal address signal is incremented by one on the rise of fourth X1 input and is not connected to the pin. 41 µPD75P238 Write Timing of Program Memory tVPS VPP VPP VDD tVDS VDD VDD + 1 VDD tXH X1 P40 to P43 P50 to P53 tDS tI tXL Output Data Input Data tOH tDV Input Data Input Data tDH tAH tDS tDF tAS MD0 tPW tM1R tMOS tOPW MD1 tPCR tM1S tM1H MD2 tM3H tM3S MD3 Read Timing of Program Memory tVPS VPP VPP VDD tVDS VDD VDD + 1 VDD tXH X1 tXL tDAD tHAD P40 to P43 P50 to P53 Output Data tDV tI MD0 MD1 tPCR MD2 tM3SR MD3 42 Output Data tM3HR tDFR µPD75P238 7. PACKAGE INFORMATION 94 PIN PLASTIC QFP ( 20) A F2 B 71 72 48 47 F1 Q 5°±5° S C D detail of lead end 94 1 G1 24 23 G2 H I M J M P K N L S94GJ-80-5BG-2 NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS INCHES A 23.2 ± 0.4 0.913+0.017 –0.016 B 20.0 ± 0.2 0.787+0.009 –0.008 C 20.0 ± 0.2 0.787+0.009 –0.008 D 23.2 ± 0.4 0.913+0.017 –0.016 F1 1.6 0.063 F2 0.8 0.031 G1 1.6 0.063 G2 0.8 0.031 H 0.35 ± 0.10 0.014+0.004 –0.005 I 0.15 0.006 J 0.8 (T.P.) 0.031 (T.P.) K 1.6 ± 0.2 0.063 ± 0.008 L 0.8 ± 0.2 0.031–0.008 M 0.15 +0.10 –0.05 N 0.12 P 3.7 Q 0.1 ± 0.1 S 4.0 MAX. +0.009 0.006 +0.004 –0.003 0.005 0.146 0.004 ± 0.004 0.158 MAX. 43 µPD75P238 94 PIN CERAMIC WQFN A D C T Y K B W S 94 Q U H I 1 M R G F E J X94KW-80A-1 NOTE Each lead centerline is located within 0.08 mm (0.003 inch) of its true position (T.P.) at maximum material condition. 44 ITEM MILLIMETERS INCHES A 20.0 ± 0.4 0.787+0.017 –0.016 B 18.0 0.709 C 18.0 0.709 D 20.0 ± 0.4 0.787+0.017 –0.016 E 1.94 0.076 F 2.14 0.084 G 4.064 MAX. 0.160 MAX. H 0.51 ± 0.10 0.020 ± 0.004 I 0.08 0.003 J 0.8 (T.P.) 0.031 (T.P.) K 1.0 ± 0.2 0.039 –0.008 Q C 1.0 C 0.039 R 1.6 0.063 S 1.6 0.063 T R 1.75 0.069 U 11.5 0.453 W 0.75 ± 0.2 0.030 –0.009 +0.009 +0.008 µPD75P238 ★ 8. RECOMMENDED SOLDERING CONDITIONS This product should be soldered and mounted under the conditions recommended in the table below. For details of recommended soldering conditions, refer to the information document "Surface Mount Technology Manual" (IEI-1207). For soldering methods and conditions other than those recommended below, contact our salesman. Table 8-1 Surface Mount Type Soldering Conditions µ PD75P238GJ-×××-5BG : 94-pin plastic QFP (■ ■ 20 mm) Soldering Method * Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 230 °C, Duration: 30 sec. max. (at 210 °C or above); Number of times: Once, Time limit: 7 days* (125 °C prebaking requires 10 hours thereafter) IR30-107-1 VPS Package peak temperature: 215 °C, Duration: 40 sec. max. (at 200 °C or above); Number of times: Once, Time limit: 7 days* (125 °C prebaking requires 10 hours thereafter) VP15-107-1 Pin part heating Pin part temperature: 300 °C max.; Duration: 3 sec. max., (per device side) For the storage period after dry-pack decapsulation, storage conditions are max. 25 °C, 65% RH. Note Use of more than one soldering method should be avoided (except in the case of pin part heating). 45 µPD75P238 APPENDIX A. DEVELOPMENT TOOLS Softwar Hardware The following support tools are available for system development using the µ PD75P238. IE-75000-R*1 IE-75001-R 75X series in-circuit emulator IE-75000-R-EM*2 IE-75000-R/IE-75001-R emulation board EP-75238GJ-R EV-9200G-94 µPD75P238 emulation probe 94-pin conversion socket EV-9200G-94 is provided PG-1500 PROM programmer PA-75P238GJ PG-1500 connected with µPD75P238GJ PROM program adapter PA-75P238KF PG-1500 connected with µPD75P238KF PROM program adapter IE control program PG-1500 controller RA75X relocatable assembler Host machine PC-9800 series (MS-DOS™ Ver.3.30 to Ver.5.00A*3) IBM PC/AT™ (PC DOS™ Ver.3.1) * 1. Maintenance product 2. Not incorporated in IE-75001-R 3. The task swap function, which is provided with Ver.5.00/5.00A. is not available with this software. Remarks 46 For development tools manufactured by a third party, see the "75X Series Selection Guide" (IF-151). µPD75P238 ★ APPENDIX B. RELATED DOCUMENTS Device Related Documents Document Name Document No. User’s Manual Instruction Application Table 75X Series Selection Guide Development Tools Related Documents Document Name Document No. Software Hardware IE-75000-R/IE-75001-R User’s Manual IE-75000-R-EM User’s Manual EP-75238GJ-R User’s Manual PG-1500 User’s Manual RA75X Assembler Package User’s Manual Operation Volume Language Volume PG-1500 Controller User’s Manual Other Documents Document Name Document No. Package Manual Surface Mount Technology Manual Quality Grade on NEC Semiconductor Devices NEC Semiconductor Device Reliability & Quality Control Electrostatic Discharge (ESD) Test Semiconductor Devices Quality Guarantee Guide Microcomputer Related Products Guide Other Manufactures Volume Note The contents of the above related documents are subjected to change without notice. The latest documents should be used for design, etc. 47 µPD75P238 48 µPD75P238 49 µPD75P238 [MEMO] No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact our sales people in advance. Application examples recommended by NEC Corporation Standard : Computer, Office equipment, Communication equipment, Test and Measurement equipment, Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc. Special : Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime systems, etc. M4 92.6 FIP is a trademark of NEC Corporation. MS-DOS is a trademark of MicroSoft Corporation. PC DOS, PC/AT are trademarks of IBM Corporation.