DATA SHEET MOS INTEGRATED CIRCUIT µPD75P308 4-BIT SINGLE-CHIP MICROCOMPUTER DESCRIPTION The µPD75P308 is a model of the µPD75308 equipped with a one-time PROM or EPROM instead of an internal mask ROM. Two types are available as the µ PD75P308. The one-time PROM type is ideal for production of a small quantity of many different types of application systems as data can only be written once to the one-time PROM of this type. Programs can be written and rewritten to the built-in EPROM type making it ideal for system evaluation. Detailed functions are described in the followig user's manual. Be sure to read it for designing. µ PD75308 User's Manual: IEM-5016 FEATURES • • µ PD75308 compatible Memory capacity • Program memory (PROM): 8064 x 8 bits • Data memory (RAM): 512 x 4 bits • • • Can be connected to a pull-up resistor through software: Ports 0-3, 6, 7 Open-drain input/output: Ports 4 and 5 Single power source: 5V ± 5% ORDERING INFORMATION Part Number Package Internal ROM µPD75P308GF-3B9 80-pin plastic QFP (14 x 20 mm) One-time PROM µPD75P308K 80-pin ceramic WQFN (LCC w/window) EPROM ★ QUALITY GRADE Part Number Package Quality Grade µPD75P308GF-001-3B9 80-pin plastic QFP (14 x 20 mm) Standard µPD75P308K 80-pin Ceramic WQFN (LCC w/window) Standard Please refer to "Quality Grade on NEC Semiconductor Devices" (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. The function common to the one-time PROM and EPROM types of product is referred to as PROM throughout this document. The information in this document is subject to change without notice. Document No. IC-2472B (O. D. No. IC-7208C) Date Published November 1993 P Printed in Japan The mark ★ shows major revised points. NEC Corporation 1989 µPD75P308 P71/KR5 P72/KR6 P73/KR7 RESET S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 1 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 P70/KR4 S13 2 63 P63/KR3 S14 3 62 P62/KR2 S15 4 61 P61/KR1 S16 5 60 P60/KR0 S17 6 59 X2 S18 7 58 X1 S19 8 57 VPP S20 9 56 XT2 S21 10 55 XT1 S22 11 54 VDD S23 12 53 P33 (MD3) S24/BP0 13 52 P32 (MD2) S25/BP1 14 51 P31/SYNC (MD1) S26/BP2 15 50 P30/LCDCL (MD0) S27/BP3 16 49 P23/BUS S28/BP4 17 48 P22/PCL S29/BP5 18 47 P21 S30/BP6 19 46 P20/PTO0 S31/BP7 20 45 P13/TI0 COM0 21 44 P12/INT2 COM1 22 43 P11/INT1 COM2 23 42 P10/INT0 COM3 24 41 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 P02/SO/SB0 P01/SCK P00/INT4 P53 P52 P51 P50 VSS P43 P42 P41 P40 VLC2 VLC1 VLCO BIAS µ PD75P308GF-3B9 S12 µ PD75P308K 2 S10 S11 PIN CONFIGURATION P03/SI/SBI PROGRAM COUNTER(13) INTBT TI0/P13 SP(8) ALU TIMER/EVENT COUNTER #0 PTO0/P20 BANK WATCH TIMER INTW SI/SBI/P03 fLCD PROGRAM MEMORY (PROM) GENERAL REG. DECODE AND CONTROL SERIAL INTERFACE SO/SB0/P02 SCK/P01 4 P00-P03 PORT1 4 P10-P13 PORT2 4 P20-P23 PORT3 4 P30-P33 /MD0-MD3 PORT4 4 P40-P43 PORT5 4 P50-P53 PORT6 4 P60-P63 PORT7 4 P70-P73 CY INTT0 BUZ/P23 PORT0 DATA MEMORY (RAM) 512 x 4 BITS 8064 x 8 BITS INTCSI 24 BLOCK DIAGRAM BASIC INTERVAL TIMER S0-S23 INT0/P10 INT1/P11 INTERRUPT CONTROL INT2/P12 INT4/P00 4 COM0-COM3 3 VLCO -VLC2 LCD CONTROLLER 8 /DRIVER fX/2 N BIT SEQ. BUFFER(16) S24/BP0 -S31/BP7 CLOCK OUTPUT CONTROL CLOCK DIVIDER SYSTEM CLOCK GENERATOR SUB MAIN STAND BY CONTROL CPU CLOCK f LCD BIAS LCDCL/P30 SYNC/P30 PCL/P22 XT1 XT2 X1 X2 VPP VDD VSS RESET 3 µPD75P308 KR0/P60KR3/P63, KR4/P70KR7/P73 8 µ PD75P308 CONTENTS 1. ★ PIN FUNCTIONS ................................................................................................................................. 5 1.1 PORT PINS ................................................................................................................................................. 5 1.2 NON PORT PINS ....................................................................................................................................... 6 1.3 PIN INPUT/OUTPUT CIRCUITS ................................................................................................................ 7 1.4 NOTES ON USING P00/INT4 AND RESET PINS ..................................................................................... 9 2. DIFFERENCES BETWEEN µPD75P308 AND µPD75308 .................................................................. 10 3. WRITING AND VERIFYING PROM (PROGRAM MEMORY) ........................................................... 11 3.1 OPERATION MODES FOR WRITING/VERIFYING PROGRAM MEMORY ............................................ 11 3.2 PROGRAM MEMORY WRITE PROCEDURE .......................................................................................... 12 3.3 PROGRAM MEMORY READ PROCEDURE ............................................................................................ 13 3.4 ERASURE (µPD75P308K ONLY) ............................................................................................................. 14 4. ELECTRICAL SPECIFICATIONS ........................................................................................................ 15 5. PACKAGE DRAWINGS ...................................................................................................................... 28 6. RECOMMENDED SOLDERING CONDITIONS ................................................................................. 30 APPENDIX A. DEVELOPMENT TOOLS ................................................................................................. 31 ★ APPENDIX B. RELATED DOCUMENTS ................................................................................................ 32 4 µPD75P308 1. PIN FUNCTIONS 1.1 PORT PINS Pin Name Input/Output P00 Also Served As Input Input/Output SCK P02 Input/Output SO/SB0 P03 Input/Output SI/SBI P12 INT1 Input TI0 P20 PTO0 Input/Output P22 P23 P30*2 P31*2 P32*2 P33*2 P40-43*2 P50-P53*2 P61 — PCL KR0 Input/Output KR1 P62 KR2 P63 KR3 P70 KR4 P71 P72 Input/Output KR5 KR6 P73 KR7 BP0 S24 BP1 BP2 X Input F -A F -B M -C 4-bit input port (PORT1) Internal pull-up resistors can be specified in 4-bit units by software. X Input B -C 4-bit input/output port (PORT2) Internal pull-up resistors can be specified in 4-bit units by software. X Input E-B X Input E-B High impedance M-A High impedance M-A Input F -A Input F -A *3 G-C Programmable 4-bit input/output port (PORT6) This port can be specified for input/output in bit units. Internal pull-up resistors can be specified in 4-bit units by software. ● ● 4-bit input/output port (PORT7) Internal pull-up resistors can be specified in 4-bit units by software. S25 Output S26 BP3 S27 BP4 S28 BP5 BP6 Input/ Output Circuit TYPE*1 With noise elimination function BUZ LCDCL MD0 Programmable 4-bit input/output port (PORT3) SYNC MD1 This port can be specified for input/output Input/Output in bit units. MD2 Internal pull-up resistors can be specified in 4-bit units by software. MD3 N-ch open-drain 4-bit input/output port (PORT4) Data input/output pin for writing and Input/Output — verifying of program memory (PROM) (lower 4 bits) N-ch open-drain 4-bit input/output port (PORT5) Data input/output pin for writing and Input/Output — verifying of program memory (PROM) (upper 4 bits) P60 1-bit output port (BIT PORT) Shared with a segment output pin. X ★ S29 Output BP7 *1: INT2 P13 P21 When Reset B 4-bit input port (PORT0) Pull-up resistors can be specified in 3-bit units for the P01 to P03 pins by software. INT0 P11 8-Bit I/O INT4 P01 P10 Function S30 S31 Circles indicate schmitt trigger inputs. 2: Can directly drive LED. 3: For BP0-7, V LC1 indicated below are selected as the input source. However, the output level is changed depending on BP0-7 and the VLC1 external circuits. 5 µ PD75P308 1.2 NON PORT PINS Pin Name Input/Output Also Served As Function When Reset Input/ Output Circuit TYPE*1 — B -C Input P13 Timer/event counter external event pulse input PTO0 Output P20 Timer/event counter output Input E-B PCL Input/Output P22 Clock output Input E-B BUZ Input/Output P23 Input E-B SCK Input/Output P01 Input F -A Input F -B Input M -C — B — B -C TI0 Fixed frequency output (for buzzer or for trimming the system clock) Serial clock input/output Serial data output SO/SB0 Input/Output P02 SI/SB1 Input/Output P03 Serial bus input/output Serial data input Serial bus input/output Edge detection vector interrupt input (either rising INT4 Input or falling edge detection is effective) P10 Edge detection vector interrupt input (detection P11 edge can be selected) P12 Edge detection testable input (rising edge detection) — B -C KR0-KR3 Input/Output P60-P63 Testable input/output(parallel falling edge detection) Input F -A KR4-KR7 Input/Output P70-P73 Testable input/output(parallel falling edge detection) Input F -A INT0 Input INT1 INT2 ★ P00 Input S0-S23 Output — Segment signal output *3 G-A S24-S31 Output BP0-7 Segment signal output *3 G-C COM0COM3 Output — Common signal output *3 G-B VLC0-VLC2 — — LCD drive power — — BIAS — — External dividing resistor disconnect output High-impedance — Input/Output P30 Externally expanded driver clock output Input E-B SYNC *2 Input/Output P31 Input E-B X1, X2 Input — — — XT1 Input — — — XT2 — — RESET Input — Externally expanded driver sync clock output To connect the crystal/ceramic oscillator to the main system clock generator. When inputting the external clock, input the external clock to pin X1, and the reverse phase of the external clock to pin X2. To connect the crystal oscillator to the subsystem clock generator. When the external clock is used, in XT1 inputs the external clock. In this case, pin XT2 must be left open. Pin XT1 can be used as a 1-bit input (test) pin. System reset input (low level active) — B To select mode when writing/verifying of program memory (PROM) Program voltage application when writing and verifying of program memory (PROM) Connect to VDD during the normal operation Apply +12.5V when writing/verifying EPROM Input E-B LCDCL *2 MD0-MD3 Input/Output *1: 2: 3: P30-P33 VPP — — VDD — — Positive power supply — — VSS — — GND — — — Circles indicate schmitt trigger inputs. These pins are provided for future system expansion. At present, these pins are used only as pins P30 and P31. For these display output, VLCX indicated below are selected as the input source. S0 to S31: VLC1, COM0 to COM2: VLC2, COM3: VLC0 However, display output level varies depending on the particular display output and VLCX external circuit. 6 — µPD75P308 1.3 PIN INPUT/OUTPUT CIRCUITS The following shows a simplified input/output circuit diagram for each pin of the µ PD75P308. TYPE D (for TYPE E–B, F-A) TYPE A (for TYPE E–B) VDD data P–ch P–ch OUT IN output disable N–ch Input buffer of CMOS standard N–ch Push–pull output that can be set in a output high–impedance state (both P–ch and N–ch are off) TYPE E–B TYPE B VDD P.U.R. P.U.R. enable P–ch IN data IN/OUT Type D output disable Type A Schmitt trigger input with hysteresis characteristics TYPE B–C P.U.R. : Pull–Up Resistor VDD TYPE E–E P.U.R. VDD P.U.R. enable P.U.R. P–ch P.U.R. enable P–ch data Type D IN/OUT output disable IN Type A P.U.R. : Pull–Up Resistor Schmitt trigger input with hysteresis characteristics Type B P.U.R. : Pull–Up Resistor 7 µ PD75P308 TYPE F–A TYPE G–B VDD V LC0 P-ch P.U.R. enable P–ch V LC1 data P-ch N-ch IN/OUT Type D output disable OUT COM data N-ch P-ch Type B V LC2 P.U.R. : Pull–Up Resistor N-ch TYPE F–B TYPE G– C VDD V DD P.U.R. P-ch P.U.R. enable output disable (P) P–ch V LC0 VDD V LC1 P-ch data output disable IN/OUT P-ch SEG data/Bit Port data N-ch OUT N-ch output disable (N) V LC2 N-ch P.U.R. : Pull–Up Resistor TYPE G–A TYPE M–A V LC0 IN/OUT P-ch data V LC1 P-ch SEG data OUT N-ch output disable N-ch V LC2 N-ch 8 Middle voltage input buffer µPD75P308 TYPE M-C VDD P.U.R. P.U.R. enable P–ch IN/OUT data N-ch output disable P.U.R. : Pull–Up Resistor 1.4 NOTES ON USING P00/INT4 AND RESET PINS In addition to the functions shown in sections 1.1 and 1.2, the P00/INT4 and RESET pins also have a function to set a test mode (for IC testing) in which the internal operations of the µPD75P308 are tested. When a voltage higher than VDD is applied to either of these pins, the test mode is set. This means that, even during ordinary operation, the µPD75P308 may be set in the test mode if a noise exceeding VDD is applied. For example, if the wiring length of the P00/INT4 or RESET pin is too long, noise superimposed on the wiring line of the pin may cause the above problem. Therefore, keep the wiring length of these pins as short as possible to suppress the noise; otherwise, take noise preventive measures as shown below by using external components. • Connect diode with low VF between V DD • Connect capacitor between VDD and P00/INT4, RESET pin and P00/INT4, RESET pin V DD Diode with low V F V DD V DD V DD P00/INT4, RESET P00/INT4, RESET 9 µPD75P308 2. DIFFERENCES BETWEEN µPD75P308 AND µPD75308 The µ PD75P308 is a model of the µ PD75308 and is equipped with a PROM instead of a mask ROM. Programs can be rewritten to the PROM of the µ PD75P308. Table 2-1 shows the differences between the µ PD75P308 and µPD75308. You should fully consider these differences when you debug or produce your application system on an experimental basis by using the PROM model, and then proceed to mass-produce the system by using the mask ROM model. For the details of the CPU and the internal hardware, refer to µ PD75308 User's Manual (IEM-5016). Table 2-1 Differences between µPD75P308 and µPD75308 µPD75P308K Item µPD75P308GF • EPROM Program Memory Pull-up Resistor • PROM (one-time model) µPD75308GF • Mask ROM • 0000H-1F7FH • 0000H-1F7FH • 0000H-1F7FH • 8064 x 8 bits • 8064 x 8 bits • 8064 x 8 bits Ports 4, 5 Dividing Resistor for LCD Not provided Mask option Not provided Mask option Driving Power Supply Pin Connection Pins 50-53 P30/MD0-P33/MD3 P30-P33 Pin 57 VPP NC Electrical Specifications ★ Current dissipations and operating temperature ranges differ between µPD75P308 and µPD75308. For detail, refer to the specification documents of each mode. Operating Voltage Range Package 5V±5% 80-pin ceramic WQFN 2.7-6.0V 80-pin plastic QFP (14 x 20 mm) (LCC w/window) Others different. ★ ★ Noise immunity and noise radiation differ because circuit scale and mask layout are Note: The noise immunity and noise radiation differ between the PROM and mask ROM models. To replace the PROM model with the mask ROM model in the course of experimental production to mass production, evaluate your system by using the CS mode (not ES model) of the mask ROM model. 10 µPD75P308 3. WRITING AND VERIFYING PROM (PROGRAM MEMORY) The program memory of the µPD75P308 is a PROM of 8064 x 8 bits. To write data to or verify the contents of this PROM, the pins listed in the table below are used. Note that no address input pins are provided because the address is updated by the clock input through the X1 pin. Pin Name Function VPP Applies voltage when program memory is written/verified (normally, at VDD potential) These pins input clock that updates address when program memory is written/verified. To X2 pin, X1, X2 input signal 180º out of phase in respect to signal to X1 pin. MD0-MD3 These pins select operation mode when program memory is written/verified. P40-P43 (Lower 4) These pins input/output 8-bit data when program memory is written/verified. P50-P53 (Upper 4) Power supply voltage application pin. VDD Apply 5V ± 5% to this pin during normal operation and 6V when program memory is written/verified. Note 1: Always cover the erasure window of the µPD75P308K with a light-opaque film except when the contents of the program memory are erased. 2: The one-time PROM model µ PD75P308GF is not equipped with a window and therefore, the contents of the program memory of this model cannot be erased by exposing it to ultraviolet rays. 3.1 OPERATION MODES FOR WRITING/VERIFYING PROGRAM MEMORY When +6V is applied to the VDD pin of the µ PD75P308 with +12.5V applied to the VPP pin, the µ PD75P308 is set in the program memory write/verify mode. In this mode, the following operation modes can be set by using the MD0-MD3 pins. At this time, pull down the levels of all the other pins to VSS. Operating Mode Specification Operating Mode VPP +12.5 V VDD +6 V MD0 MD1 MD2 MD3 H L H L Program memory address 0 clear mode L H H H Write mode L L H H Verify mode H x H H Program inhibit mode x: L or H 11 µ PD75P308 3.2 PROGRAM MEMORY WRITE PROCEDURE The program memory write procedure is as follows. High-speed program memory write is possible. (1) Ground the unused pins through pull-down resistors. The X1 pin must be low. (2) Supply 5 V to the VDD and VPP pins. (3) Wait for 10 microseconds. (4) Set program memory address 0 clear mode. (5) Supply 6 V to the VDD pin and 12.5 V to the VPP pin. (6) Set program inhibit mode. (7) Write data in 1-millisecond write mode. (8) Set program inhibit mode. (9) Set verify mode. If data has been written connectly, proceed to step (10). If data has not yet been written, repeat steps (7) to (9). (10) Write additional data for (the number of times data was written (X) in steps (7) to (9)) times 1 milliseconds. (11) Set program inhibit mode. (12) Supply a pulse to the X1 pin four times to update the program memory address by 1. (13) Repeat steps (7) to (12) to the last address. (14) Set program memory address 0 clear mode. (15) Change the voltages of VDD and V PP pins to 5 V. (16) Turn off the power supply. Steps (2) to (12) are illustrated below. X-time repetition Write Verify Additional data write VPP VPP VDD VDD+1 VDD VDD X1 P40-P43 P50-P53 MD0 (P30) MD1 (P31) MD2 (P32) MD3 (P33) 12 Data input Data output Data input Address increment µPD75P308 3.3 PROGRAM MEMORY READ PROCEDURE The contents of the program memory can be read in the following procedure. (1) Ground the unused pins through pull-down resistors. The X1 pin must be low. (2) Supply 5 V to the VDD and V PP pins. (3) Wait for 10 microseconds. (4) Set program memory address 0 clear mode. (5) Supply 6 V to the VDD pin and 12.5 V to the V PP pin. (6) Set program inhibit mode. (7) Set verify mode. Data of each address is sequentially output each time a clock pulse is input to the X1 pin four times. (8) Set program inhibit mode. (9) Set program memory address 0 clear mode. (10) Change the voltages of V DD and VPP pins to 5 V. (11) Turn off the power supply. Steps (2) to (9) are illustrated below. VPP VPP VDD VDD+1 VDD VDD X1 P40-P43 P50-P53 Data output Data output MD0 (P30) MD1 (P31) MD2 (P32) MD3 (P33) 13 µPD75P308 3.4 ERASURE (µPD75P308K ONLY) The contents of the data programmed to the µ PD75P308 can be erased by exposing the window of the program memory to ultraviolet rays. The wavelength of the ultraviolet rays used to erase the contents is about 250 nm, and the quantity of the ultraviolet rays necessary for complete erasure is 15 W.s/cm2 (= ultraviolet ray intensity x erasure time). When a commercially available ultraviolet ray lamp (wavelength: 254 nm, intensity: 12 mW/cm2) is used, about 15 to 20 minutes is required. Note 1: The contents of the program memory may be erased when the µPD75P308 is exposed for a long time to direct sunlight or the light of fluorescent lamps. To protect the contents from being erased, mask the window of the program memory with the light-opaque film supplied as an accessory with the UV EPROM products. 2: To erase the memory contents, the distance between the ultraviolet ray lamp and the µPD75P308 should be 2.5 cm or less. Remarks: The time required for erasure changes depending on the degradation of the ultraviolet ray lamp and the surface condition (dirt) of the window of the program memory. 14 µPD75P308 4. ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS (T a = 25°C) Parameter Symbol Conditions Rating Unit Supply Voltage VDD -0.3 to +7.0 V Supply Voltage VPP -0.3 to +13.5 V -0.3 to VDD+0.3 V -0.3 to +11 V -0.3 to VDD+0.3 V 1 Pin -15 mA All pins -30 mA Peak value 30 mA Effective value 15 mA 100 mA 60 mA 100 mA 60 mA VI1 Other than ports 4 or 5 VI2 *1 Ports 4 and 5 Input Voltage Output Voltage VO High-Level Output Current I OH Open-drain One pin Low-Level Output Current *2 I OH Peak value Total of ports 0, 2, 3, 5 Effective value Peak value Total of ports 4, 6, 7 Effective value Operating Temperature Topt -10 to +70 °C Storage Temperature Tstg -65 to +150 °C *1: The impedance of the power source (pull-up resistor) must be 50 KΩ minimum when a voltage higher than 10V is applied to ports 4 and 5. 2: Effective value = Peak value x √Duty 15 µPD75P308 MAIN SYSTEM CLOCK OSCILLATOR CIRCUIT CHARACTERISTICS (T a = -10 to +70°C, VDD = 5 to ±5 V) Recommended Oscillator Item Constants Ceramic*3 Conditions MIN. TYP. MAX. Unit 5.0*4 MHz 4 ms 5.0*4 MHz 10 ms 1.0 5.0*4 MHz 100 500 ns Oscillation X1 X2 1.0 frequency (fXX)*1 C2 Oscillation stabilization C1 *2 time VDD Crystal After VDD came to MIN. of oscillation voltage range Oscilaltion X1 X2 1.0 frequency (fXX)*1 4.19 C2 Oscillation stabilization C1 time*2 VDD External Clock X1 input frequency X1 X2 (fX)*1 X1 input high-, low-level µ PD74HCU04 widths (tXH, tXL) * 1: The oscillation frequency and X1 input frequency are indicated only to express the characteristics of the oscillator circuit. For instruction execution time, refer to AC Characteristics. 2: Time required for oscillation to stabilize after VDD reaches the minimum value of the oscillation voltage range or the STOP mode has been released. 3: The oscillators below are recommended. ★ 4: When the oscillation frequency is 4.19 MHz < fx ≤ 5.0 MHz, do not select PCC = 0011 as the instruction execution time: otherwise, one machine cycle is set to less than 0.95 µ s, falling short of the rated minimum value of 0.95 µ s. ★ Caution: When using the oscillation circuit of the main system clock, wire the portion enclosed in dotted line in the figures as follows to avoid adverse influences on the wiring capacity: • Keep the wiring length as short as possible. • Do not cross the wiring over the other signal lines. Do not route the wiring in the vicinity of lines through which a high alternating current flows. • Always keep the ground point of the capacitor of the oscillator circuit at the same potential as VDD . Do not connect the power source pattern through which a high current flows. • Do not extract signals from the oscillation circuit. RECOMMENDED OSCILLATION CIRCUIT CONSTANTS MAIN SYSTEM CLOCK: CERAMIC OSCILLATOR (Ta = -10 to +70°C) Manufacturer Murata Mfg. Co., Ltd. 16 External Capacitance [pF] Oscillation Voltage Range [V] C1 C2 MIN. MAX. CSA 2.00MG 30 30 4.75 5.25 CSA 4.19MG 30 30 4.75 5.25 CSA 4.19MGU 30 30 4.75 5.25 CST 4.19MG 30 pF (internal) 30 pF (internal) 4.75 5.25 Product Name µPD75P308 SUBSYSTEM CLOCK OSCILLATOR CIRCUIT CHARACTERISTICS (Ta = -10 to +70°C, VDD = 5 V ±5%) Recommended Oscillator Item Constants Crystal Conditions MIN. TYP. MAX. Unit 32 32.768 35 kHz 1.0 2 s 32 100 kHz 5 15 µs Oscillation XT1 XT2 R C3 C4 frequency (fXT) Oscillation stabilization time* VDD External Clock XT1 input frequency XT1 XT2 Open (fXT) XT1 input high-, low-level widths (tXTH, tXTL) *: Time required for oscillation to stabilize after VDD reaches the minimum value of the oscillation voltage range. Caution: When using the oscillation circuit of the subsystem clock, wire the portion enclosed in dotted line ★ in the figures as follows to avoid adverse influences on the wiring capacity: • Keep the wiring length as short as possible. • Do not cross the wiring over the other signal lines. Do not route the wiring in the vicinity of lines through which a high alternating current flows. • Always keep the ground point of the capacitor of the oscillator circuit at the same potential as VDD . Do not connect the power source pattern through which a high current flows. • Do not extract signals from the oscillation circuit. The amplification factor of the subsystem clock oscillation circuit is designed to be low to reduce the current dissipation and therefore, the subsystem clock oscillation circuit is influenced by noise more easily than the main system clock oscillation circuit. When using the subsystem clock, therefore, exercise utmost care in wiring the circuit. CAPACITANCE (Ta = 25°C, VDD = 0 V) Parameter Symbol Input Capacitance CIN Output Capacitance COUT Input/Output Capacitance CIO Conditions f = 1 MHz Pins other than thosemeasured are at 0 V MIN. TYP. MAX. Unit 15 pF 15 pF 15 pF 17 µPD75P308 DC CHARACTERISTICS (Ta = -10 to +70°C, V DD = 5V ±5%) Parameter Symbol High-Level Input Voltage Low-Level Input Voltage Conditions MIN. TYP. Ports 2, 3 0.7 VDD VDD V VIH2 Ports 0, 1, 6, 7, RESET 0.8 VDD VDD V VIH3 Ports 4, 5 0.7 VDD 10 V VIH4 X1, X2, XT1 VDD-0.5 VDD V VIL1 Ports 2, 3, 4, 5 0 0.3 VDD V VIL2 Ports 0, 1, 6, 7, RESET 0 0.2 VDD V VIL3 X1, X2, XT1 Ports 0, 2, 3, 6, 7 BIAS 0 0.4 V VOH1 Open-drain IOH = -1mA VDD-1.0 BP0-7 IOH = -100µA*1 Ports 0, 2, 3, Ports 3, 4, 5 V OL1 6, 7 IOL = 15mA VOL2 SB0, 1 Open-drain Pull-up R ≥ 1kΩ V OL3 BP0-7 IOL = 100 µA*1 VOH2 Low-Level Output Voltage V VDD-2.0 V 0.4 2.0 V 0.4 V 0.2VDD V 1.0 V Other than below 3 µA X1, X2, XT1 20 µA Ports 4, 5 20 µA Other than below -3 µA X1, X2, XT1 IOL = 1.6mA ILIH1 ILIH2 ILIH3 Low-Level Input Leakage Current Low-Level Output Leakage Current Internal Pull-Up Resistor -20 µA VOUT = VDD Other than below 3 µA ILOH2 VOUT = 10V Ports 4.5 20 µA ILOL VOUT = 0V -3 µA RLI Ports 0, 1, 2, 3, 6, 7 (except P00) VIN = 0V 80 KΩ 2.5 VDD V 0 ±0.2V V 0 ±0.2V V *2 VODC (Common) *2 VODS (Segment) Supply Current VIN = 0V 15 VLCD LCD Drive Voltage LCD Output Voltage Deviation VIN = 10V ILOH1 ILIL2 LCD Output Voltage Deviation VIN = VDD ILIL1 High-Level Output Leakage Current *3 Unit VIH1 High-Level Output Voltage High-Level Input Leakage Current MAX. V LCD0 = V LCD I0 = ±5 µA 2 V LCD1 = V LCD x — V LCD2 = V LCD x I0 = ±1 µA 4.19MHz crystal *4 *6 IDD2 oscillator C1 = C2 = 22pF HALT mode IDD4 32 kHz crystal oscillator 3 1 — 3 2.7 V ≤ VLCD ≤ VDD IDD1 IDD3 40 *5 HALT mode XT1 = 0V STOP mode 5 15 mA 500 1500 µA 350 1000 35 100 0.5 20 µA µA * 1: When using two of BP0-BP3 and two of BP4-BP7 for output at the same time. 2: "Voltage deviation" means the difference between the ideal segment or common output value (VLCDn: = 0, 1, 2) and output voltage. 3: Currents for the built-in pull-up resistor are not included. 4: Including when the subsystem clock is operated. 5: When operated with the subsystem clock by setting the system clock control register (SCC) to 1001 to stop the main system clock operation. 6: When operand in the high-speed mode with the processor clock control register (PCC) set to 0011. 18 µPD75P308 AC CHARACTERISTICS (Ta = -10 to + 70°C, VDD = 5V ±5%) Operation Other Than Serial Transfer Parameter Symbol Conditions MIN. TYP. MAX. Unit 64 µs 125 µs 1 MHz CPU Clock Cycle Time*1 (Minimum Instruction Execution Time 0.95 w/subsystem clock 114 tCY = 1 Machine Cycle) TI0 Input Frequency w/main system clock 122 fTI 0 tTIH, tTIL 0.48 µs TI0 Input High-, Low-Level Widths Interrupt Input High-, Low-Level tINTH, INT0 *2 µs Widths tINTL KR0-7, INT1, 2, 4 10 µs RESET Low-Level Width tRSL 10 µs t cy vs VDD (with main system clock) 70 * 1: The CPU clock (Φ) cycle time is determined 64 60 by the oscillation frequency of the connected oscillator, system clock control register 6 (PCC). 5 The figure on the right is cycle time tCY vs. 4 supply voltage VDD characteristics at the main system clock. 2: 2tCY or 128/fXX depending on the setting of the interrupt mode register (IM0). Cycle time t cy [µs] (SCC), and processor clock control register 3 2 1 0.5 0 1 2 3 4 5 6 Supply voltage VDD [V] 19 µPD75P308 SERIAL TRANSFER OPERATION TWO-LINE AND THREE-LINE SERIAL I/O MODES (SCK: internal clock output) Parameter SCK Cycle Time SCK High-, Low-Level Widths ★ Symbol Conditions MIN. TYP. MAX. Unit tKCY1 Output 1600 ns tKH1, tKL1 Output tKCY1/2-50 ns SI Set-Up Time (vs. SCK↑ ) tSIK1 150 ns SI Hold Time (vs. SCK↑ ) tKSI1 400 ns SCK ↓ → SO Output Delay Time tKSO1 RL = 1kΩ, CL = 100pF* 250 ns MAX. Unit *: RL and C L are load resistance and load capacitance of the SO output line. TWO-LINE AND THREE-LINE SERIAL I/O MODES (SCK: external clock input) Parameter SCK Cycle Time SCK High-, Low-Level Widths ★ Symbol Conditions MIN. tKCY2 Input 800 ns tKH2, tKL2 Input 400 ns SI Set-Up Time (vs. SCK↑ ) tSIK2 100 ns SI Hold Time (vs. SCK↑ ) tKSI2 400 ns SCK ↓ → SO Output Delay Time tKSO2 R L = 1kΩ, CL = 100pF* *: RL and C L are load resistance and load capacitance of the SO output line. 20 TYP. 300 ns µPD75P308 SBI MODE (SCK: internal clock output (master)) Parameter SCK Cycle Time Symbol Conditions MIN. TYP. MAX. Unit 1600 ns t KH3 tKCY/2 -50 ns SB0, 1 Set-Up Time (vs. SCK ↑ ) tSIK3 150 ns SB0, 1 Hold Time (vs. SCK↑ ) tKSI3 tKCY/2 ns SCK ↓ → SB0, 1 Output Delay Time t KSO3 SCK ↑ → SB0, 1↓ tKSB tKCY ns SB0, 1 ↓ → SCK↓ tSBK tKCY ns SB0, 1 Low-Level Width t SBL tKCY ns SB0, 1 High-Level Width t SBH tKCY ns SCK High-, Low-Level Widths tKCY3 tKL3 RL = 1kΩ, CL = 100pF* 0 250 ns ★ *: R L and CL are load resistance and load capacitance of the SO output line. SBI MODE (SCK: external clock output (master)) Parameter SCK Cycle Time SCK High-, Low-Level Widths Symbol Conditions tKCY4 tKL4 tKH4 MIN. TYP. MAX. Unit 1600 ns 400 ns SB0, 1 Set-Up Time (vs. SCK↑ ) tSIK4 100 ns SB0, 1 Hold Time (vs. SCK↑ ) tKSI4 t KCY/2 ns SCK ↓ → SB0, 1 Output Delay Time t KSO4 SCK ↑ → SB0, 1↓ tKSB t KCY ns SB0, 1 ↓ → SCK↓ tSBK t KCY ns SB0, 1 Low-Level Width t SBL t KCY ns SB0, 1 High-Level Width t SBH t KCY ns RL = 1kΩ, CL = 100pF* 0 300 ns ★ *: R L and CL are load resistance and load capacitance of the SO output line. 21 µ PD75P308 AC TIMING TEST POINT (excluding X1 and XT1 inputs) 0.8 VDD 0.8 VDD Test points 0.2 VDD 0.2 VDD CLOCK TIMING 1/fX tXL tXH X1 input VDD –0.5V 0.4 V 1/fXT tXTL tXTH XT1 input VDD –0.5V 0.4 V TI0 TIMING 1/fTI tTIL TI0 22 tTIH µPD75P308 SERIAL TRANSFER TIMING THREE-LINE SERIAL I/O MODE: tKCY1 tKL1 tKH1 SCK tSIK1 SI tKSI1 Input data tKSO1 Output data SO TWO-LINE SERIAL I/O MODE: tKCY tKH tKL SCK tKSO tSIK tKSI SB0,1 23 µPD75P308 SERIAL TRANSFER TIMING BUS RELEASE SIGNAL TRANSFER t KCY3,4 tKL3,4 tKH3,4 SCK tKSB tSBL tSBH tSIK3,4 tSBK SB0,1 tKSO3,4 COMMAND SIGNAL TRANSFER tKCY3,4 tKL3,4 tKH3,4 SCK tKSB tSIK3,4 tSBK SB0,1 tKSO3,4 INTERRUPT INPUT TIMING tINTL INT0, 1, 2, 4 KR0-7 RESET INPUT TIMING tRSL RESET 24 tINTH tKSI3,4 tKSI3,4 µPD75P308 LOW-VOLTAGE DATA RETENTION CHARACTERISTICS OF DATA MEMORY IN STOP MODE (T a = -10 to +70°C) Parameter Symbol Conditions MIN. TYP. MAX. Unit 6.0 V 10 µA Data Retention Supply VDDDR Voltage 2.0 Data Retention Supply IDDDR Current* 1 VDDDR = 2.0V 0.1 Oscillation Stabilization Released by RESET t WAIT Wait Time*2 µs 0 tSREL Release Signal Set Time 2 17/fX ms *3 ms Released by interrupt *1: Does not include current folowing through internal pull-up resistor 2: The oscillation stabilization wait time is the time during which the CPU is stopped to prevent unstable operation when oscillation is started. 3: Depends on the setting of the basic interval timer mode register (BTM) as follows: BTM3 BTM2 BTM1 BTM0 WAIT time ( ): f X = 4.19 MHz — 0 0 — 2 20/fX (approx. 250 ms) — 0 1 — 217/f X (approx. 31.3 ms) — 1 0 — 215/f X (approx. 7.82 ms) — 1 1 — 213/f X (approx. 1.95 ms) DATA RETENTION TIMING (releasing STOP mode by RESET) Internal reset operation HALT mode STOP mode Operation mode Data retention mode VDD VDDDR tSREL STOP instruction execution RESET tWAIT DATA RETENTION TIMING (standby release signal: releasing STOP mode by interrupt) HALT mode STOP mode Operation mode Data retention mode VDD VDDDR tSREL STOP instruction execution Standby release signal (interrupt request) tWAIT 25 µPD75P308 DC PROGRAMMING CHARACTERISTICS (Ta = 25 ±5°C, VDD = 6.0±0.25V, V PP = 12.5±0.3V, VSS = 0V) Parameter Symbol High-Level Input Voltage Low-Level Input Voltage MAX. Unit VIH1 Other than X1 or X2 Conditions 0.7 VDD VDD V VIH2 X1 and X2 VDD –0.5 VDD V VIL1 Other than X1 or X2 0 0.3 V DD V 0 0.4 V 10 µA VIL2 X1 and X2 Input Leakage Current ILI VIN = V IL or VIH High-Level Output Voltage VOH IOH = –1 mA Low-Level Output Voltage VOL IOL = 1.6 mA VDD Supply Current IDD VPP Supply Current IPP MIN. TYP. VDD –1.0 V MD0 = V IL, MD1 = VIH 0.4 V 30 mA 30 mA Notes 1: VPP must not exceed +13.5 V, including the overshoot. 2: Apply VDD before VPP and disconnect it after VPP. AC PROGRAMMING CHARACTERISTICS (Ta = 25±5°C, VDD = 6.0±0.25V, V PP = 12.5±0.3V, VSS = 0V) Symbol *1 Address Set-Up Time*2 (vs.MD0↓) tAS tAS 2 µs MD1 Set-Up Time (vs. MD0↓) tM1S tOES 2 µs Data Set-Up Time (vs. MD0↓) tDS tDS 2 µs Address Hold Time*2 (vs.MD0↑) tAH tAH 2 µs Data Hold Time (vs. MD0↑) tDH tDH 2 µs MD0 ↑→ Data Output Float Delay Time tDF tDF 0 Parameter TYP. MAX. 130 Unit ns VPP Set-Up Time (vs. MD3↑) tVPS tVPS 2 µs tVDS tVCS 2 µs Initial Program Pulse Width tPW tPW 0.95 Additional Program Pulse Width tOPW tOPW 0.95 MD0 Set-Up Time (vs. MD1↑) tMOS tCES MD0 ↓→ Data Output Delay Time tDV tDV MD1 Hold Time (vs. MD0↑) tM1H tOEH MD1 Recovery Time (vs. MD0↓) tM1R tOR 1.0 1.05 ms 21.0 ms µs 2 1 MD0 = MD1 = VIL tM1H + tM1R ≥ 50 µs µs 2 µs 2 µs tPCR – 10 µs tXH,tXL – 0.125 µs X1 Input Frequency fX – Initial Mode Set Time tI – 2 µs MD3 Set-Up Time (vs. MD1↑) tM3S – 2 µs MD3 Hold Time (vs. MD1↓) tM3H – 2 µs MD3 Set-Up Time (vs. MD0↓) tM3SR – When data is read from program memory 2 µs Address → Data Output Delay Time tDAD tACC When data is read from program memory Address → Data Output Hold Time tHAD tOH When data is read from program memory 0 MD3 Hold Time (vs. MD0↑) tM3HR – When data is read from program memory 2 tDFR – When data is read from program memory X1 Input High-/Low- Level Width *2 *2 ★ MIN. VDD Set-Up Time (vs. MD3↑) Program Counter Reset Time ★ Conditions MD3 ↓→ Data Output Float Delay Time 4.19 MHz 2 µs 130 ns µs 2 µs *1: These symbols are the corresponding µ PD27C256 symbols. 2: The internal address signal is incremented by 1 at the fourth rising edge of X1 input. The internal address is not connected to any pin. 26 µPD75P308 PROGRAM MEMORY WRITE TIMING tVPS VPP VPP VDD VDD VDD+1 VDD tVDS tXH X1 P40-P43 P50-P53 Data output Data input tDS t OH tI tDV Data input tDF tXL tDH tAH tDS Data input tAS MD0 tMOS tM1R tPW tOPW MD1 tPCR tM1S tM1H MD2 tM3H tM3S MD3 PROGRAM MEMORY READ TIMING tVPS VPP VPP VDD VDD VDD+1 VDD tVDS tXH X1 tXL P40-P43 P50-P53 tHAD Data output tDV tI tDAD Data output tM3HR tDFR MD0 MD1 tPCR MD2 tM3SR MD3 27 µPD75P308 5. PACKAGE DRAWINGS 80 PIN PLASTIC QFP (14×20) A B 41 40 64 65 F Q 5°±5° S C D detail of lead end 25 24 80 1 G H I M J M P K N L P80GF-80-3B9-2 NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition. 28 ITEM MILLIMETERS INCHES A 23.6 ± 0.4 0.929 ± 0.016 B 20.0 ± 0.2 0.795 +0.009 –0.008 C 14.0 ± 0.2 0.551+0.009 –0.008 D 17.6 ± 0.4 0.693 ± 0.016 F 1.0 0.039 G 0.8 0.031 H 0.35 ± 0.10 0.014 +0.004 –0.005 I 0.15 0.006 J 0.8 (T.P.) 0.031 (T.P.) K 1.8 ± 0.2 0.071 –0.009 L 0.8 ± 0.2 0.031+0.009 –0.008 M 0.15+0.10 –0.05 0.006+0.004 –0.003 N 0.15 0.006 P 2.7 Q 0.1 ± 0.1 S 3.0 MAX. +0.008 0.106 0.004 ± 0.004 0.119 MAX. µPD75P308 80 PIN CERAMIC WQFN A Q K C D B T W S 80 H U I 1 M R E F G J X80KW-80A-1 NOTE Each lead centerline is located within 0.08 mm (0.003 inch) of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS INCHES A 20.0 ± 0.4 0.787+0.017 –0.016 B 19.0 0.748 C 13.2 0.520 D 14.2 ± 0.4 0.559 ± 0.016 E 1.64 0.065 F 2.14 0.084 G 4.064 MAX. 0.160 MAX. H 0.51 ± 0.10 0.020 ± 0.004 I 0.08 0.003 J 0.8 (T.P.) 0.031 (T.P.) K 1.0 ± 0.2 0.039 –0.008 Q C 0.5 C 0.020 R 0.8 0.031 S 1.1 0.043 T R 3.0 R 0.118 U 12.0 0.472 W 0.75 ± 0.2 0.030 –0.009 +0.009 +0.008 29 µ PD75P308 ★ 6. RECOMMENDED SOLDERING CONDITIONS It is recommended that µ PD75P308 be soldered under the following conditions. For details on the recommended soldering conditions, refer to Information Document "Semiconductor Devices Mounting Manual" (IEI-616). The soldering methods and conditions are not listed here, consult NEC. Table 6-1 Soldering Conditions µPD75P308GF-3B9: 80-pin plastic QFP (14 x 20 mm) Soldering Method *: Soldering Conditions Symbol for Recommended Condition Wave Soldering Soldering bath temperature: 260°C max., time: 10 seconds max., number of times: 1, pre-heating temperature: 120°C max. (package surface temperature), maximum number of days: 2 days*, (beyond this period, 16 hours of pre-baking is required at 125°C). WS60-162-1 Infrared Reflow Package peak temperature: 230°C, time: 30 seconds max. (210°C min.), number of times: 1, maximum number of days: 2 days* (beyond this period, 16 hours of pre-baking is required at 125°C) IR30-162-1 VPS Package peak temperature: 215°C, time: 40 seconds max. (200°C min.), number of times: 1, maximum number of days: 2 days* (beyond this period, 16 hours of pre-baking is required at 125°C) VP15-162-1 Pin Partial Heating Pin temperature: 300°C max., time: 3 seconds max. (per side) — Number of days after unpacking the dry pack. Storage conditions are 25°C and 65%RH max. Caution: Do not use two or more soldering methods in combination (except the pin partial heating method). Notice A model that can be soldered under the more stringent conditions (infrared reflow peak temperature: 235°C, number of times: 2, and an extended number of days) is also available. For details, consult NEC. 30 µPD75P308 APPENDIX A. DEVELOPMENT TOOLS The following development support tools are readily available to support development of systems using µPD75P308: PROM writing tools Hardare IE-75000-R*1 In-circuit emulator for 75K series IE-75001-R IE-75000-R-EM *2 Emulation board for IE-75000-R and IE-75001-R EP-75308GF-R Emulation prove for µPD75P308GF, provided with 80-pin conversion socket, EV-9200G-80 PG-1500 PA-75P308GF EV-9200G-80. PROM programmer PROM programmer adapter solely used for µ PD75P308GF. It is connected to PG-1500. PA-75P308K PROM programmer adapter solely used for µ PD75P308K. It is connected to PG-1500. Software IE Control Program Host machine PG-1500 Controller • PC-9800 series (MS-DOSTM Ver.3.30 to Ver.5.00A*3 ) RA75X Relocatable • IBM PC/ATTM (PC DOSTM Ver.3.1) Assembler *1: Maintenance product 2: Not provided with IE-75001-R 3: Ver.5.00/5.00A has a task swap function, but this function cannot be used with this software. Remarks: For development tools from other companies, refer to 75X Series Selection Guide (IF-151). 31 µ PD75P308 ★ APPENDIX B. 32 RELATED DOCUMENTS µPD75P308 GENERAL NOTES ON CMOS DEVICES 1 STATIC ELECTRICITY (ALL MOS DEVICES) Exercise care so that MOS devices are not adversely influenced by static electricity while being handled. The insulation of the gates of the MOS device may be destroyed by a strong static charge. Therefore, when transporting or storing the MOS device, use a conductive tray, magazine case, or conductive buffer materials, or the metal case NEC uses for packaging and shipment, and use grounding when assembling the MOS device system. Do not leave the MOS device on a plastic plate and do not touch the pins of the device. Handle boards on which MOS devices are mounted similarly . 2 PROCESSING OF UNUSED PINS (CMOS DEVICES ONLY) Fix the input level of CMOS devices. Unlike bipolar or NMOS devices, if a CMOS device is operated with nothing connected to its input pin, intermediate level input may be generated due to noise, and an inrush current may flow through the device, causing the device to malfunction. Therefore, fix the input level of the device by using a pull-down or pull-up resistor. If there is a possibility that an unused pin serves as an output pin (whose timing is not specified), each pin should be connected to VDD or GND through a resistor. Refer to “Processing of Unused Pins” in the documents of each devices. 3 STATUS BEFORE INITIALIZATION (ALL MOS DEVICES) The initial status of MOS devices is undefined upon power application. Since the characteristics of an MOS device are determined by the quantity of injection at the molecular level, the initial status of the device is not controlled during the production process. The output status of pins, I/O setting, and register contents upon power application are not guaranteed. However, the items defined for reset operation and mode setting are subject to guarantee after the respective operations have been executed. When using a device with a reset function, be sure to reset the device after power application. 33 µ PD75P308 [MEMO] No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. The devices listed in this document are not suitable for uses in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for the applications not intended by NEC, please contact our sales people in advance. Application examples recommended by NEC Corporation Standard: Computer, Office equipment, Communication equipment, Test and Measurement equipment, Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products,etc. Special: Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime system, etc. M4 92.6 MS-DOS is a trademark of Microsoft Corporation. PC DOS and PC/AT are trademarks of IBM Corporation. 34