NSC 100341

100341
Low Power 8-Bit Shift Register
General Description
Features
The 100341 contains eight edge-triggered, D-type flip-flops
with individual inputs (Pn) and outputs (Qn) for parallel operation, and with serial inputs (Dn) and steering logic for bidirectional shifting. The flip-flops accept input data a setup
time before the positive-going transition of the clock pulse
and their outputs respond a propagation delay after this rising clock edge.
The circuit operating mode is determined by the Select inputs S0 and S1, which are internally decoded to select either
“parallel entry”, “hold”, “shift left” or “shift right” as described
in the Truth Table. All inputs have 50 kΩ pull-down resistors.
n
n
n
n
n
35% power reduction of the 100141
2000V ESD protection
Pin/function compatible with 100141
Voltage compensated operating range = −4.2V to −5.7V
Standard Microcircuit
Drawing (SMD) 5962-9459101
Logic Symbol
Pin Names
Description
CP
Clock Input
S0, S1
Select Inputs
D0, D7
Serial Inputs
P0–P7
Parallel Inputs
Q0–Q7
Data Outputs
DS100315-1
© 1998 National Semiconductor Corporation
DS100315
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100341 Low Power 8-Bit Shift Register
August 1998
Connection Diagrams
24-Pin DIP
24-Pin Quad Cerpak
DS100315-3
DS100315-2
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2
Logic Diagram
DS100315-5
Truth Table
Function
Inputs
Outputs
D7
D0
S1
S0
CP
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
Load Register
X
X
L
L
N
P7
P6
P5
P4
P3
P2
P1
P0
Shift Left
X
L
L
H
N
Q6
Q5
Q4
Q3
Q2
Q1
Q0
L
Shift Left
X
H
L
H
N
Q6
Q5
Q4
Q3
Q2
Q1
Q0
H
Shift Right
L
X
H
L
N
L
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Shift Right
H
X
H
L
N
H
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Hold
X
X
H
H
X
Hold
X
X
X
X
H
Hold
X
X
X
X
L
No Change
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
N = LOW-to-HIGH Transition
3
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Absolute Maximum Ratings (Note 1)
≥2000V
ESD (Note 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Recommended Operating
Conditions
Above which the useful life may be impaired
Storage Temperature (TSTG)
Maximum Junction Temperature (TJ)
Ceramic
VEE Pin Potential to Ground Pin
Input Voltage (DC)
Output Current (DC Output HIGH)
Case Temperature (TC)
Military
Supply Voltage (VEE)
−65˚C to +150˚C
+175˚C
−7.0V to +0.5V
VEE to +0.5V
−50 mA
−55˚C to +125˚C
−5.7V to −4.2V
Note 1: Absolute maximum ratings are those values beyond which the device may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: ESD testing conforms to MIL-STD-883, Method 3015.
Military Version
DC Electrical Characteristics
VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = −55˚C to +125˚C
Symbol
Parameter
Conditions
Min
Max
Units
TC
VOH
Output HIGH Voltage
−1025
−870
mV
0˚C to +125˚C
−1085
−870
mV
−55˚C
VOL
Output LOW Voltage
−1830 −1620
mV
0˚C to +125˚C
−1830 −1555
mV
−55˚C
VOHC
Output HIGH Voltage
−1035
mV
0˚C to +125˚C
VOLC
Output LOW Voltage
VIH
Input HIGH Voltage
−1085
−1165
mV
−55˚C
−1610
mV
0˚C to +125˚C
−1555
mV
−870
mV
VIN = VIH (Max)
Loading with
or VIL(Min)
50Ω to −2.0V
VIN = VIH (Min)
Loading with
or VIL(Max)
50Ω to −2.0V
IIL
IIH
IEE
Input LOW Current
Input LOW Current
−1830 −1475
mV
0.50
µA
Guaranteed HIGH Signal
−55˚C to +125˚C
Guaranteed LOW Signal
−55˚C to +125˚C
for All Inputs
VEE = −4.2V
(Notes 3, 4,
5)
240
µA
0˚C to +125˚C
340
µA
−55˚C
VIN = VIH (Max)
−168
−55
mA
−55˚C to +125˚C
−178
−55
mA
Power Supply Current
(Notes 3, 4,
5, 6)
(Notes 3, 4,
5, 6)
(Notes 3, 4,
5, 6)
VIN = VIL (Min)
VEE = −5.7V
Input High Current
(Notes 3, 4,
5)
−55˚C
−55˚C to +125˚C
for All Inputs
VIL
Notes
(Notes 3, 4,
5)
Inputs Open
VEE = −4.2V to −4.8V
VEE = −4.2V to −5.7V
(Notes 3, 4,
5)
Note 3: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals −55˚C), then testing immediately
without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides “cold start” specifications which can be considered a
worst case condition at cold temperatures.
Note 4: Screen tested 100% on each device at −55˚C, +25˚C and +125˚C, Subgroups 1, 2, 3, 7, and 8.
Note 5: Sample tested (Method 5005, Table I) on each manufactured lot at −55˚C, +25˚C, and +125˚C, Subgroups A1, 2, 3, 7, and 8.
Note 6: Guaranteed by applying specified input condition and testing VOH/VOL.
AC Electrical Characteristics
VEE = −4.2V to −5.7V, VCC = VCCA = GND
Symbol
Parameter
fmax
Max Clock Frequency
tPLH
Propagation Delay
tPHL
CP to Output
tTLH
Transition Time
tTHL
20% to 80%, 80% to 20%
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TC = −55˚C
TC = +25˚C
TC = +125˚C
Min
Max
Min
Max
Min
0.50
2.50
0.50
2.30
0.50
2.80
ns
0.30
1.30
0.30
1.30
0.30
1.30
ns
400
400
Units
Conditions
300
MHz
Figures 2, 3
4
(Notes 7, 8,
9, 11)
Figures 1, 3
4
Notes
Max
AC Electrical Characteristics
(Continued)
VEE = −4.2V to −5.7V, VCC = VCCA = GND
Symbol
Parameter
TC = −55˚C
TC = +25˚C
TC = +125˚C
Min
Min
Min
Max
Max
Units
Conditions
Notes
Max
Setup Time
ts
th
Dn, Pn
0.60
0.60
0.60
Sn
1.70
1.60
2.40
Dn, Pn
0.90
0.90
0.90
Sn
0.50
0.50
0.50
2.00
2.00
2.00
ns
Figure 4
(Note 10)
Hold Time
tpw(H)
Pulse Width HIGH
ns
ns
Figure 3
CP
Note 7: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals −55˚C), then testing immediately
after power-up. This provides “cold start” specifications which can be considered a worst case condition at cold temperatures.
Note 8: Screen tested 100% on each device at +25˚C temperature only, Subgroup A9.
Note 9: Sample tested (Method 5005, Table I) on each manufactured lot at +25˚C, Subgroup A9, and at +125˚C and −55˚C temperatures, Subgroups A10 and A11.
Note 10: Not tested at +25˚C, +125˚C and −55˚C temperature (design characterization data).
Note 11: The propagation delay specified is for the switching of a single output. Delays may vary up to 0.40 ns if multiple outputs are switching simultaneously.
Test Circuitry
DS100315-6
Notes:
VCC, VCCA = +2V, VEE = −2.5V
L1, L2 and L3 = equal length 50Ω impedance lines
RT = 50Ω terminator internal to scope
Decoupling 0.1 µF from GND to VCC and VEE
All unused outputs are loaded with 50Ω to GND
CL = Fixture and stray capacitance ≤ 3 pF
Pin numbers shown are for Flatpak; for DIP see logic symbol
FIGURE 1. AC Test Circuit
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Test Circuitry
(Continued)
DS100315-7
Notes:
For shift right mode pulse generator connected to S0 is moved to S1.
Pulse generator connected to S1 has a LOW frequency 99% duty cycle, which allows occasional parallel load.
The feedback path from output to input should be as short as possible.
FIGURE 2. Shift Frequency Test Circuit (Shift Left)
Switching Waveforms
DS100315-8
FIGURE 3. Propagation Delay and Transition Times
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Switching Waveforms
(Continued)
DS100315-9
Notes:
ts is the minimum time before the transition of the clock that information must be present at the data input.
th is the minimum time after the transition of the clock that information must remain unchanged at the data input.
FIGURE 4. Setup and Hold Times
7
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Physical Dimensions
inches (millimeters) unless otherwise noted
24-Lead Ceramic Dual-In-Line Package (0.400" Wide) (D)
NS Package Number J24E
24-Lead Quad Cerpak (F)
NS Package Number W24B
9
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100341 Low Power 8-Bit Shift Register
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the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness.
ure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
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