ONSEMI 2N5191G

2N5190, 2N5191, 2N5192
Silicon NPN Power
Transistors
Silicon NPN power transistors are for use in power amplifier and
switching circuits, — excellent safe area limits. Complement to PNP
2N5194, 2N5195.
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Features
• ESD Ratings: Machine Model, C; > 400 V
4.0 AMPERES
NPN SILICON
POWER TRANSISTORS
40, 60, 80 VOLTS − 40 WATTS
Human Body Model, 3B; > 8000 V
• Epoxy Meets UL 94 V−0 @ 0.125 in.
• Pb−Free Packages are Available*
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Collector−Emitter Voltage
2N5190
2N5191
2N5192
VCEO
40
60
80
Vdc
Collector−Base Voltage
2N5190
2N5191
2N5192
VCBO
40
60
80
Vdc
VEBO
5.0
Vdc
Collector Current
IC
4.0
Adc
Base Current
IB
1.0
Adc
Total Device Dissipation @ TC = 25°C
Derate above 25°C
PD
40
320
W
mW/°C
TJ, Tstg
–65 to +150
°C
Characteristic
Symbol
Max
Unit
Thermal Resistance, Junction−to−Case
RqJC
3.12
°C/W
Emitter−Base Voltage
Operating and Storage Junction
Temperature Range
TO−225AA
CASE 77
STYLE 1
3 2
1
MARKING DIAGRAM
YWW
2
N519xG
THERMAL CHARACTERISTICS
Y
= Year
WW
= Work Week
2N519x = Device Code
x = 0, 1, or 2
G
= Pb−Free Package
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
ORDERING INFORMATION
Package
Shipping†
2N5190
TO−225AA
500 Units/Box
2N5190G
TO−225AA
(Pb−Free)
500 Units/Box
2N5191
TO−225AA
500 Units/Box
2N5191G
TO−225AA
(Pb−Free)
500 Units/Box
2N5192
TO−225AA
500 Units/Box
2N5192G
TO−225AA
(Pb−Free)
500 Units/Box
Device
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
March, 2006 − Rev. 12
1
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Publication Order Number:
2N5191/D
2N5190, 2N5191, 2N5192
ELECTRICAL CHARACTERISTICS* (TC = 25_C unless otherwise noted)
Symbol
Characteristic
Min
Max
Unit
40
60
80
−
−
−
Vdc
−
−
−
1.0
1.0
1.0
mAdc
−
−
−
−
−
−
0.1
0.1
0.1
2.0
2.0
2.0
mAdc
−
−
−
0.1
0.1
0.1
mAdc
−
1.0
mAdc
25
20
10
7.0
100
80
−
−
−
−
0.6
1.4
Vdc
OFF CHARACTERISTICS
VCEO(sus)
Collector−Emitter Sustaining Voltage (Note 1)
(IC = 0.1 Adc, IB = 0)
2N5190
2N5191
2N5192
Collector Cutoff Current
(VCE = 40 Vdc, IB = 0)
(VCE = 60 Vdc, IB = 0)
(VCE = 80 Vdc, IB = 0)
2N5190
2N5191
2N5192
ICEO
Collector Cutoff Current
(VCE = 40 Vdc, VEB(off) = 1.5 Vdc)
(VCE = 60 Vdc, VEB(off) = 1.5 Vdc)
(VCE = 80 Vdc, VEB(off) = 1.5 Vdc)
(VCE = 40 Vdc, VEB(off) = 1.5 Vdc, TC = 125_C)
(VCE = 60 Vdc, VEB(off) = 1.5 Vdc, TC = 125_C)
(VCE = 80 Vdc, VEB(off) = 1.5 Vdc, TC = 125_C)
2N5190
2N5191
2N5192
2N5190
2N5191
2N5192
Collector Cutoff Current
(VCB = 40 Vdc, IE = 0)
(VCB = 60 Vdc, IE = 0)
(VCB = 80 Vdc, IE = 0)
2N5190
2N5191
2N5192
ICEX
ICBO
Emitter Cutoff Current
(VBE = 5.0 Vdc, IC = 0)
IEBO
ON CHARACTERISTICS (Note 1)
hFE
DC Current Gain
(IC = 1.5 Adc, VCE = 2.0 Vdc)
2N5190/2N5191
2N5192
2N5190/2N5191
2N5192
(IC = 4.0 Adc, VCE = 2.0 Vdc)
−
Collector−Emitter Saturation Voltage
(IC = 1.5 Adc, IB = 0.15 Adc)
(IC = 4.0 Adc, IB = 1.0 Adc)
VCE(sat)
Base−Emitter On Voltage
(IC = 1.5 Adc, VCE = 2.0 Vdc)
VBE(on)
−
1.2
Vdc
fT
2.0
−
MHz
DYNAMIC CHARACTERISTICS
Current−Gain — Bandwidth Product
(IC = 1.0 Adc, VCE = 10 Vdc, f = 1.0 MHz)
*JEDEC Registered Data.
1. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2.0%.
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2
hFE , DC CURRENT GAIN (NORMALIZED)
2N5190, 2N5191, 2N5192
10
7.0
5.0
TJ = 150°C
VCE = 2.0 V
VCE = 10 V
3.0
2.0
1.0
0.7
0.5
−55 °C
25°C
0.3
0.2
0.1
0.004
0.007
0.01
0.02
0.03
0.05
0.1
0.2
0.3
IC, COLLECTOR CURRENT (AMP)
0.5
2.0
1.0
3.0
4.0
VCE , COLLECTOR−EMITTER VOLTAGE (VOLTS)
Figure 1. DC Current Gain
2.0
TJ = 25°C
1.6
1.2
IC = 10 mA
100 mA
1.0 A
3.0 A
0.8
0.4
0
0.05 0.07 0.1
0.2
0.3
0.5
0.7
1.0
2.0
3.0
5.0 7.0 10
IB, BASE CURRENT (mA)
20
30
50
70
100
200
300
500
Figure 2. Collector Saturation Region
θV, TEMPERATURE COEFFICIENTS (mV/°C)
2.0
TJ = 25°C
1.6
1.2
0.8
VBE(sat) @ IC/IB = 10
VBE @ VCE = 2.0 V
0.4
VCE(sat) @ IC/IB = 10
0
0.005 0.01 0.02 0.03 0.05
0.1
0.2 0.3 0.5
1.0
2.0 3.0 4.0
+2.5
+2.0
+1.5
hFE@VCE + 2.0V
2
TJ = −65°C to +150°C
*APPLIES FOR IC/IB ≤
+1.0
+0.5
*qV for VCE(sat)
0
−0.5
−1.0
−1.5
qV for VBE
−2.0
−2.5
0.005
0.01 0.02 0.03 0.05
0.1
0.2 0.3 0.5
1.0
IC, COLLECTOR CURRENT (AMP)
IC, COLLECTOR CURRENT (AMP)
Figure 3. “On” Voltages
Figure 4. Temperature Coefficients
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3
2.0 3.0 4.0
RBE , EXTERNAL BASE−EMITTER RESISTANCE (OHM
2N5190, 2N5191, 2N5192
103
VCE = 30 V
102
TJ = 150°C
101
100
100°C
10−1
REVERSE
10− 2
25°C
ICES
−0.2 −0.1
0
+0.4 +0.5
+0.6
106
IC ≈ ICES
105
IC = 2 x ICES
104
103
(TYPICAL ICES VALUES
OBTAINED FROM FIGURE 5)
102
20
40
80
100
120
140
160
Figure 5. Collector Cut−Off Region
Figure 6. Effects of Base−Emitter Resistance
300
VCC
RC
Vin
TJ = +25°C
200
SCOPE
RB
Cjd<<Ceb
t1
−4.0 V
t3
RB and RC varied
to obtain desired
current levels
t1 ≤ 7.0 ns
100 < t2 < 500 ms
t3 < 15 ns
Vin
t2
TURN−OFF PULSE
100
Ceb
70
50
DUTY CYCLE ≈ 2.0%
APPROX −9.0 V
30
Ccb
0.1
0.2 0.3
0.5
2.0
IC/IB = 10
TJ = 25°C
1.0
20 30 40
10
0.7
0.5
t, TIME (s)
μ
tr @ VCC = 10 V
tf @ VCC = 30 V
0.3
0.2
0.1
0.07
0.05
td @ VEB(off) = 2.0 V
0.5 0.7 1.0
0.2 0.3
IC, COLLECTOR CURRENT (AMP)
ts′
1.0
tr @ VCC = 30 V
0.03
0.02
0.05 0.07 0.1
2.0 3.0 5.0
Figure 8. Capacitance
2.0
0.1
0.07
0.05
1.0
VR, REVERSE VOLTAGE (VOLTS)
Figure 7. Switching Time Equivalent Test Circuit
0.3
0.2
60
TJ, JUNCTION TEMPERATURE (°C)
APPROX
+11 V
0.7
0.5
VCE = 30 V
IC = 10 x ICES
VBE, BASE−EMITTER VOLTAGE (VOLTS)
TURN−ON PULSE
APPROX
+11 V
Vin 0
VEB(off)
+0.1 +0.2 +0.3
CAPACITANCE (pF)
10− 3
−0.4 −0.3
FORWARD
107
2.0
0.03
0.02
0.05 0.07 0.1
3.0 4.0
Figure 9. Turn−On Time
tf @ VCC = 10 V
IB1 = IB2
IC/IB = 10
ts′ = ts − 1/8 tf
TJ = 25°C
0.5 0.7 1.0
0.2 0.3
IC, COLLECTOR CURRENT (AMP)
Figure 10. Turn−Off Time
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4
2.0
3.0 4.0
2N5190, 2N5191, 2N5192
10
IC, COLLECTOR CURRENT (AMP)
5.0ms
5.0
There are two limitations on the power handling ability of
a transistor; average junction temperature and second
breakdown. Safe operating area curves indicate IC − VCE
limits of the transistor that must be observed for reliable
operation; i.e., the transistor must not be subjected to greater
dissipation than the curves indicate.
The data of Figure 11 is based on TJ(pk) = 150_C; TC is
variable depending on conditions. Second breakdown pulse
limits are valid for duty cycles to 10% provided TJ(pk)
v 150_C. At high case temperatures, thermal limitations
will reduce the power that can be handled to values less than
the limitations imposed by second breakdown.
100ms
1.0ms
TJ = 150°C
2.0
dc
1.0
SECONDARY BREAKDOWN LIMIT
THERMAL LIMIT AT TC = 25°C
BONDING WIRE LIMIT
CURVES APPLY BELOW RATED VCEO
2N5191
0.5
0.2
0.1
1.0
2N5192
2.0
5.0
10
20
50
VCE, COLLECTOR−EMITTER VOLTAGE (VOLTS)
100
r(t), EFFECTIVE TRANSIENT
THERMAL RESISTANCE (NORMALIZED)
Figure 11. Rating and Thermal Data
Active−Region Safe Operating Area
1.0
0.7
0.5
D = 0.5
0.3
0.2
0.1
0.07
0.05
qJC(max) = 3.12°C/W 2N5190−92
0.2
0.1
0.05
0.02
0.01
0.03
SINGLE PULSE
0.02
0.01
0.01
0.02 0.03
0.05
0.1
0.2
0.3 0.5
1.0
2.0
3.0 5.0 10
t, TIME OR PULSE WIDTH (ms)
20
50
100
200
500
1000
Figure 12. Thermal Response
DESIGN NOTE: USE OF TRANSIENT THERMAL RESISTANCE DATA
A train of periodical power pulses can be represented by
the model shown in Figure A. Using the model and the
device thermal response, the normalized effective transient
thermal resistance of Figure 12 was calculated for various
duty cycles.
To find qJC(t), multiply the value obtained from Figure 12
by the steady state value qJC.
Example:
The 2N5190 is dissipating 50 watts under the following
conditions: t1 = 0.1 ms, tp = 0.5 ms. (D = 0.2).
Using Figure 12, at a pulse width of 0.1 ms and D = 0.2,
the reading of r(t1, D) is 0.27.
The peak rise in function temperature is therefore:
tP
PP
PP
t1
1/f
t1
tP
PEAK PULSE POWER = PP
DUTY CYCLE, D = t1 f −
Figure A
DT = r(t) x PP x qJC = 0.27 x 50 x 3.12 = 42.2_C
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5
2N5190, 2N5191, 2N5192
PACKAGE DIMENSIONS
TO−225AA
CASE 77−09
ISSUE Z
−B−
U
F
Q
−A−
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 077−01 THRU −08 OBSOLETE, NEW STANDARD
077−09.
C
M
1 2 3
H
DIM
A
B
C
D
F
G
H
J
K
M
Q
R
S
U
V
K
J
V
G
S
R
0.25 (0.010)
A
M
M
B
M
D 2 PL
0.25 (0.010)
M
A
M
B
M
INCHES
MIN
MAX
0.425
0.435
0.295
0.305
0.095
0.105
0.020
0.026
0.115
0.130
0.094 BSC
0.050
0.095
0.015
0.025
0.575
0.655
5 _ TYP
0.148
0.158
0.045
0.065
0.025
0.035
0.145
0.155
0.040
−−−
MILLIMETERS
MIN
MAX
10.80
11.04
7.50
7.74
2.42
2.66
0.51
0.66
2.93
3.30
2.39 BSC
1.27
2.41
0.39
0.63
14.61
16.63
5 _ TYP
3.76
4.01
1.15
1.65
0.64
0.88
3.69
3.93
1.02
−−−
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. BASE
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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For additional information, please contact your
local Sales Representative.
2N5191/D