WL CS P6 PMCM650VNE 12 V, N-channel Trench MOSFET 7 April 2015 Product data sheet 1. General description N-channel enhancement mode Field-Effect Transistor (FET) in a 6 bumps Wafer Level Chip-Size Package (WLCSP) using Trench MOSFET technology. 2. Features and benefits • • • • Low threshold voltage Ultra small package: 0.98 × 1.48 × 0.35 mm Trench MOSFET technology ElectroStatic Discharge (ESD) protection > 2 kV HBM 3. Applications • • • • Relay driver High-speed line driver Low-side loadswitch Switching circuits 4. Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage Tj = 25 °C - - 12 V VGS gate-source voltage -8 - 8 V ID drain current - - 8.4 A - 21 25 mΩ VGS = 4.5 V; Tamb = 25 °C; t ≤ 5 s [1] Static characteristics RDSon drain-source on-state resistance [1] VGS = 4.5 V; ID = 3 A; Tj = 25 °C Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated, mounting pad for 2 drain 6 cm . Scan or click this QR code to view the latest information for this product PMCM650VNE NXP Semiconductors 12 V, N-channel Trench MOSFET 5. Pinning information Table 2. Pinning information Pin Symbol Description Simplified outline A1 G gate A2 S source A B1 S source B B2 S source C1 D drain C2 D drain 1 Graphic symbol 2 D G C S Transparent top view 017aaa255 WLCSP6 (OLPMCM650VNE) 6. Ordering information Table 3. Ordering information Type number PMCM650VNE Package Name Description Version WLCSP6 WLCSP6: wafer level chip-size package; 6 bumps (3 x 2) OLPMCM650VNE 7. Marking Table 4. Marking codes Type number Marking code PMCM650VNE AA 2 PIN A1 INDICATION MARKING CODE (EXAMPLE) 1 A B C Top view, balls down Fig. 1. aaa-013901 WLCSP6 marking code description PMCM650VNE Product data sheet All information provided in this document is subject to legal disclaimers. 7 April 2015 © NXP Semiconductors N.V. 2015. All rights reserved 2 / 15 PMCM650VNE NXP Semiconductors 12 V, N-channel Trench MOSFET 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage Tj = 25 °C - 12 V VGS gate-source voltage -8 8 V ID drain current VGS = 4.5 V; Tamb = 25 °C; t ≤ 5 s [1] - 8.4 A VGS = 4.5 V; Tamb = 25 °C [1] - 6.4 A VGS = 4.5 V; Tamb = 100 °C [1] - 4.1 A - 26 A [2] - 556 mW [1] - 1300 mW - 12500 mW IDM peak drain current Tamb = 25 °C; single pulse; tp ≤ 10 µs Ptot total power dissipation Tamb = 25 °C Tsp = 25 °C Tj junction temperature -55 150 °C Tamb ambient temperature -55 150 °C Tstg storage temperature -65 150 °C - 1.2 A Source-drain diode IS source current PMCM650VNE Product data sheet Tamb = 25 °C [1] [1] Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated, mounting pad for [2] drain 6 cm . Device mounted on an FR4 Printed Circuit Board (PCB), single-sided copper, tin-plated and standard footprint. 2 All information provided in this document is subject to legal disclaimers. 7 April 2015 © NXP Semiconductors N.V. 2015. All rights reserved 3 / 15 PMCM650VNE NXP Semiconductors 12 V, N-channel Trench MOSFET 017aaa123 120 Pder (%) Ider (%) 80 80 40 40 0 - 75 Fig. 2. 017aaa124 120 - 25 25 75 125 Tj (°C) 0 - 75 175 Normalized total power dissipation as a function of junction temperature Fig. 3. - 25 25 75 125 Tj (°C) 175 Normalized continuous drain current as a function of junction temperature aaa-013878 102 ID (A) tp = 10 µs Limit RDSon = VDS/ID tp = 100 µs 10 tp = 1 ms 1 tp = 10 ms DC; Tsp = 25 °C 10-1 tp = 100 ms DC; Tamb = 25 °C; drain mounting pad 6 cm2 10-2 10-1 1 10 102 VDS (V) IDM = single pulse Fig. 4. Safe operating area; junction to ambient; continuous and peak drain currents as a function of drainsource voltage 9. Thermal characteristics Table 6. Thermal characteristics Symbol Parameter Conditions Rth(j-a) thermal resistance from junction to ambient in free air in free air; t ≤ 5 s PMCM650VNE Product data sheet All information provided in this document is subject to legal disclaimers. 7 April 2015 Min Typ Max Unit [1] - 180 225 K/W [2] - 65 85 K/W [3] - 75 95 K/W [3] - 45 55 K/W © NXP Semiconductors N.V. 2015. All rights reserved 4 / 15 PMCM650VNE NXP Semiconductors 12 V, N-channel Trench MOSFET Symbol Parameter Rth(j-sp) thermal resistance from junction to solder point [1] [2] [3] Conditions Min Typ Max Unit - 5 10 K/W Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard footprint. 2 Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for drain 6 cm . aaa-013880 103 Zth(j-a) (K/W) 2 Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for drain, 4-layer, 1 cm . duty cycle = 1 102 0.75 0.33 0.20 0.50 0.25 0.10 10 0.05 0.02 0 0.01 1 10-3 10-2 10-1 1 10 102 tp (s) 103 FR4 PCB, standard footprint Fig. 5. Transient thermal impedance from junction to ambient as a function of pulse duration; typical values 102 aaa-013881 duty cycle = 1 0.75 0.50 Zth(j-a) (K/W) 0.33 0.20 0.25 0.10 10 0.05 0.02 0.01 0 1 10-3 10-2 10-1 FR4 PCB, mounting pad for drain 6 cm Fig. 6. 1 10 102 tp (s) 103 2 Transient thermal impedance from junction to ambient as a function of pulse duration; typical values PMCM650VNE Product data sheet All information provided in this document is subject to legal disclaimers. 7 April 2015 © NXP Semiconductors N.V. 2015. All rights reserved 5 / 15 PMCM650VNE NXP Semiconductors 12 V, N-channel Trench MOSFET 10. Characteristics Table 7. Characteristics Symbol Parameter Conditions Min Typ Max Unit Static characteristics V(BR)DSS drain-source breakdown voltage ID = 250 µA; VGS = 0 V; Tj = 25 °C 12 - - V VGSth gate-source threshold voltage ID = 250 µA; VDS = VGS; Tj = 25 °C 0.4 0.6 0.9 V IDSS drain leakage current VDS = 12 V; VGS = 0 V; Tj = 25 °C - - 1 µA IGSS gate leakage current VGS = 8 V; VDS = 0 V; Tj = 25 °C - - 10 µA VGS = -8 V; VDS = 0 V; Tj = 25 °C - - -10 µA VGS = 4.5 V; VDS = 0 V; Tj = 25 °C - - 5 µA VGS = -4.5 V; VDS = 0 V; Tj = 25 °C - - -5 µA VGS = 2.5 V; VDS = 0 V; Tj = 25 °C - - 200 nA VGS = -2.5 V; VDS = 0 V; Tj = 25 °C - - -200 nA VGS = 4.5 V; ID = 3 A; Tj = 25 °C - 21 25 mΩ VGS = 4.5 V; ID = 3 A; Tj = 150 °C - 34 41 mΩ VGS = 2.5 V; ID = 3 A; Tj = 25 °C - 24 32 mΩ VGS = 1.8 V; ID = 2 A; Tj = 25 °C - 28 40 mΩ VGS = 1.5 V; ID = 1 A; Tj = 25 °C - 33 45 mΩ RDSon drain-source on-state resistance gfs forward transconductance VDS = 6 V; ID = 3 A; Tj = 25 °C - 26 - S RG gate resistance f = 1 MHz; Tj = 25 °C - 8.6 - Ω Dynamic characteristics QG(tot) total gate charge VDS = 6 V; ID = 3 A; VGS = 4.5 V; - 15.4 - nC QGS gate-source charge Tj = 25 °C - 1 - nC QGD gate-drain charge - 3.6 - nC Ciss input capacitance VDS = 6 V; f = 1 MHz; VGS = 0 V; - 1060 - pF Coss output capacitance Tj = 25 °C - 330 - pF Crss reverse transfer capacitance - 305 - pF td(on) turn-on delay time VDS = 6 V; ID = 3 A; VGS = 4.5 V; - 11 - ns tr rise time RG(ext) = 6 Ω; Tj = 25 °C - 31 - ns td(off) turn-off delay time - 80 - ns tf fall time - 43 - ns PMCM650VNE Product data sheet All information provided in this document is subject to legal disclaimers. 7 April 2015 © NXP Semiconductors N.V. 2015. All rights reserved 6 / 15 PMCM650VNE NXP Semiconductors 12 V, N-channel Trench MOSFET Symbol Parameter Conditions Min Typ Max Unit IS = 1.2 A; VGS = 0 V; Tj = 25 °C - 0.7 1.2 V Source-drain diode VSD source-drain voltage 20 ID (A) aaa-017443 4.5 V aaa-017444 10-3 1.4 V 1.8 V 2.5 V ID (A) 16 1.3 V 10-4 12 1.2 V 8 (1) 10-5 (2) (3) 1.1 V 4 VGS = 1.0 V 0 Fig. 7. 0 1 2 3 VDS (V) 10-6 4 0 0.2 0.4 Tj = 25 °C Tj = 25 °C; VDS = 5 V Output characteristics: drain current as a function of drain-source voltage; typical values (1) minimum values (2) typical values (3) maximum values Fig. 8. aaa-017445 80 1.2 V RDSon 0.8 1.0 VGS (V) Sub-threshold drain current as a function of gate-source voltage aaa-017446 60 1.4 V 1.3 V 0.6 RDSon 60 40 Tj = 150 °C 40 1.8 V 20 0 VGS = 4.5 V 0 4 8 12 16 ID (A) 0 20 Tj = 25 °C Fig. 9. Tj = 25 °C 20 2.5 V Product data sheet 1 2 3 4 VGS (V) 5 ID = 3 A Drain-source on-state resistance as a function of drain current; typical values PMCM650VNE 0 Fig. 10. Drain-source on-state resistance as a function of gate-source voltage; typical values All information provided in this document is subject to legal disclaimers. 7 April 2015 © NXP Semiconductors N.V. 2015. All rights reserved 7 / 15 PMCM650VNE NXP Semiconductors 12 V, N-channel Trench MOSFET aaa-017447 25 aaa-017448 1.5 ID (A) a 20 1.0 15 10 Tj = 150 °C 5 0 0.5 Tj = 25 °C 0 0.5 1.0 1.5 VGS (V) 0 -60 2.0 VDS > ID × RDSon Fig. 11. Transfer characteristics: drain current as a function of gate-source voltage; typical values 60 120 180 aaa-017450 104 VGS(th) (V) Tj (°C) Fig. 12. Normalized drain-source on-state resistance as a function of junction temperature; typical values aaa-017449 1.5 0 C (pF) 1.0 (1) (1) 103 (2) 0.5 0 -60 (3) 0 (2) (3) 60 120 Tj (°C) 102 10-1 180 1 ID = 0.25 mA; VDS = VGS f = 1 MHz; VGS = 0 V (1) maximum values (2) typical values (3) minimum values (1) Ciss Product data sheet VDS (V) 102 (2) Coss (3) Crss Fig. 13. Gate-source threshold voltage as a function of junction temperature PMCM650VNE 10 Fig. 14. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values All information provided in this document is subject to legal disclaimers. 7 April 2015 © NXP Semiconductors N.V. 2015. All rights reserved 8 / 15 PMCM650VNE NXP Semiconductors 12 V, N-channel Trench MOSFET aaa-017451 5 VDS VGS (V) ID 4 VGS(pl) 3 VGS(th) VGS 2 QGS1 QGS2 QGS 1 QGD QG(tot) 003aaa508 0 0 4 8 12 Fig. 16. MOSFET transistor: Gate charge waveform definitions 16 20 QG (nC) ID = 3 A; VDS = 6 V; Tamb = 25 °C Fig. 15. Gate-source voltage as a function of gate charge; typical values aaa-017452 1.2 IS (A) 0.8 Tj = 150 °C 0.4 Tj = 25 °C 0 0 0.2 0.4 0.6 VSD (V) 0.8 VGS = 0 V Fig. 17. Source current as a function of source-drain voltage; typical values 11. Test information P t2 duty cycle δ = t1 t2 t1 t 006aaa812 Fig. 18. Duty cycle definition PMCM650VNE Product data sheet All information provided in this document is subject to legal disclaimers. 7 April 2015 © NXP Semiconductors N.V. 2015. All rights reserved 9 / 15 PMCM650VNE NXP Semiconductors 12 V, N-channel Trench MOSFET 12. Package outline WLCSP6: wafer level chip-size package; 6 bumps (3 x 2) PMCM650VNE A D B A2 E A A1 ball A1 index area detail X C ball A1 index area y1 C y 1 e2 2 A B C v w b e C A B C X e1 0 1 mm scale Dimensions (mm are the original dimensions) Unit A A1 A2 b D E e e1 e2 v w y max 0.375 0.215 0.160 0.275 1.51 1.01 nom 0.345 0.200 0.145 0.260 1.48 0.98 0.50 1.00 0.50 0.15 0.05 0.05 min 0.315 0.185 0.130 0.245 1.45 0.95 mm Note Device back is metal coated on Drain potential. Outline version pmcm650vne-ssmos_po References IEC JEDEC JEITA European projection Issue date 15-03-24 15-03-25 PMCM650VNE Fig. 19. Package outline WLCSP6 (OL-PMCM650VNE) PMCM650VNE Product data sheet All information provided in this document is subject to legal disclaimers. 7 April 2015 © NXP Semiconductors N.V. 2015. All rights reserved 10 / 15 PMCM650VNE NXP Semiconductors 12 V, N-channel Trench MOSFET 13. Soldering Footprint information for reflow soldering of PMCM650VNE package PMCM650VNE 0.15 0.35 0 .25 0.5 0.25 1.2 solder resist solder paste = solderland occupied area 0.5 1.7 Dimensions in mm pmcm650vne-ssmos_fr Fig. 20. Reflow soldering footprint for WLCSP6 (OL-PMCM650VNE) PMCM650VNE Product data sheet All information provided in this document is subject to legal disclaimers. 7 April 2015 © NXP Semiconductors N.V. 2015. All rights reserved 11 / 15 PMCM650VNE NXP Semiconductors 12 V, N-channel Trench MOSFET 14. Revision history Table 8. Revision history Data sheet ID Release date Data sheet status Change notice Supersedes PMCM650VNE v.1 20150407 Product data sheet - - PMCM650VNE Product data sheet All information provided in this document is subject to legal disclaimers. 7 April 2015 © NXP Semiconductors N.V. 2015. All rights reserved 12 / 15 PMCM650VNE NXP Semiconductors 12 V, N-channel Trench MOSFET In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. 15. 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Contents 1 General description ............................................... 1 2 Features and benefits ............................................1 3 Applications ........................................................... 1 4 Quick reference data ............................................. 1 5 Pinning information ............................................... 2 6 Ordering information ............................................. 2 7 Marking ................................................................... 2 8 Limiting values .......................................................3 9 Thermal characteristics .........................................4 10 Characteristics ....................................................... 6 11 Test information ..................................................... 9 12 Package outline ................................................... 10 13 Soldering .............................................................. 11 14 Revision history ................................................... 12 15 15.1 15.2 15.3 15.4 Legal information .................................................13 Data sheet status ............................................... 13 Definitions ...........................................................13 Disclaimers .........................................................13 Trademarks ........................................................ 14 © NXP Semiconductors N.V. 2015. All rights reserved For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 7 April 2015 PMCM650VNE Product data sheet All information provided in this document is subject to legal disclaimers. 7 April 2015 © NXP Semiconductors N.V. 2015. All rights reserved 15 / 15