ITF87056DQT
Data Sheet
5A, 20V, 0.045 Ohm, Dual P-Channel,
2.5V Specified Power MOSFET
Packaging
TSSOP-8
File Number
4813.2
Features
• Ultra Low On-Resistance
- rDS(ON) = 0.045Ω, VGS = −4.5V
- rDS(ON) = 0.048Ω, VGS = −4.0V
- rDS(ON) = 0.077Ω, VGS = −2.5V
• 2.5V Gate Drive Capability
• Gate to Source Protection Diode
• Simulation Models
- Temperature Compensated PSPICE™ and SABER
Electrical Models
- Spice and SABER Thermal Impedance Models
- www.intersil.com
5
1
23
March 2000
4
• Peak Current vs Pulse Width Curve
Symbol
• Transient Thermal Impedance Curve vs Board Mounting
Area
DRAIN1(1)
(8) DRAIN2
OURCE1(2)
(7) SOURCE2
SOURCE1(3)
(6) SOURCE2
GATE1(4)
(5) GATE2
• Switching Time vs RGS Curves
Ordering Information
PART NUMBER
ITF87056DQT
PACKAGE
TSSOP-8
BRAND
87056
NOTE: When ordering, use the entire part number. ITF87056DQT2
is available only in tape and reel.
Absolute Maximum Ratings
TA = 25oC, Unless Otherwise Specified
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
Drain Current
Continuous (TA = 25oC, VGS = -4.5V) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TA = 25oC, VGS = -4.0V) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TA = 100oC, VGS = -4.0V) (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TA = 100oC, VGS = -2.5V) (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM
Power Dissipation (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL
Package Body for 10s, See Techbrief TB370 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
NOTES:
ITF87056DQT
-20
-20
±12
UNITS
V
V
V
5.0
5.0
3.0
2.5
Figure 4
2.0
16
-55 to 150
A
A
A
A
W
mW/oC
oC
300
260
oC
oC
1. TJ = 25oC to 125oC.
2. 62.5oC/W measured using FR-4 board with 0.50 in2 (322.6 mm2 ) copper pad at 1 second.
3. 230oC/W measured using FR-4 board with 0.0022 in2 (1.44 mm2) copper pad at 1000 seconds.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
1
CAUTION: These devices are sensitive to electrostatic discharge. Follow proper ESD Handling Procedures.
SABER© is a Copyright of Analogy Inc. PSPICE® is a registered trademark of MicroSim Corporation.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 2000
ITF87056DQT
TA = 25oC, Unless Otherwise Specified
Electrical Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
-20
-
-
V
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
BVDSS
ID = 250µA, VGS = 0V Figure 11
Zero Gate Voltage Drain Current
IDSS
VDS = -20V, VGS = 0V
-
-
-10
µA
Gate to Source Leakage Current
IGSS
VGS = ±12V
-
-
±10
µA
-0.5
-
-1.5
V
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250µA Figure 10
Drain to Source On Resistance
rDS(ON)
ID = 5.0A, VGS = -4.5V Figures 8, 9
-
0.037
0.045
Ω
ID = 3.0A, VGS = -4.0V Figure 8
-
0.039
0.048
Ω
ID = 2.5A, VGS = -2.5V Figure 8
-
0.057
0.077
Ω
Pad Area = 0.50 in2 (322.6 mm2) (Note 2)
-
-
62.5
oC/W
Pad Area = 0.017 in2 (11.2 mm2) Figure 20
-
-
199
oC/W
Pad Area = 0.0022 in2 (1.44 mm2) Figure 20
-
-
230
oC/W
VDD = -10V, ID = 2.5A
VGS = -2.5V,
RGS = 15Ω
Figures 14, 18, 19
-
470
-
ns
-
1240
-
ns
-
700
-
ns
-
775
-
ns
-
225
-
ns
-
470
-
ns
-
1200
-
ns
-
800
-
ns
-
8.6
-
nC
-
4.1
-
nC
-
0.5
-
nC
THERMAL SPECIFICATIONS
Thermal Resistance Junction to
Ambient
RθJA
SWITCHING SPECIFICATIONS (VGS = -2.5V)
Turn-On Delay Time
td(ON)
Rise Time
tr
Turn-Off Delay Time
td(OFF)
Fall Time
tf
SWITCHING SPECIFICATIONS (VGS = -4.5V)
Turn-On Delay Time
td(ON)
Rise Time
tr
Turn-Off Delay Time
td(OFF)
Fall Time
VDD = -10V, ID = 5.0A
VGS = -4.5V,
RGS = 16Ω
Figures 15, 18, 19
tf
GATE CHARGE SPECIFICATIONS
Total Gate Charge
Qg(TOT)
VGS = 0V to -4.5V
Gate Charge at -2V
Qg(-2)
VGS = 0V to -2V
Threshold Gate Charge
Qg(TH)
VGS = 0V to -0.5V
VDD = -10V,
ID = 5.0A,
Ig(REF) = 1.0mA
Figures 13, 16, 17
Gate to Source Gate Charge
Qgs
-
1.2
-
nC
Gate to Drain “Miller” Charge
Qgd
-
1.8
-
nC
-
750
-
pF
-
215
-
pF
-
100
-
pF
MIN
TYP
MAX
UNITS
ISD = -5.0A
-
-0.86
-
V
trr
ISD = -5.0A, dISD/dt = 10A/µs
-
40
-
ns
QRR
ISD = -5.0A, dISD/dt = 10A/µs
-
5
-
nC
CAPACITANCE SPECIFICATIONS
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
VDS = -10V, VGS = 0V,
f = 1MHz
Figure 12
Source to Drain Diode Specifications
PARAMETER
SYMBOL
Source to Drain Diode Voltage
VSD
Reverse Recovery Time
Reverse Recovered Charge
2
TEST CONDITIONS
ITF87056DQT
Typical Performance Curves
-6
ID, DRAIN CURRENT (A)
1.0
0.8
0.6
0.4
VGS = -4.5V, RθJA = 62.5oC/W
-4
-2
VGS = -2.5V, RθJA = 230oC/W
0.2
0
0
0
25
50
75
100
125
25
150
50
75
100
125
150
TA , AMBIENT TEMPERATURE (oC)
TA , AMBIENT TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
AMBIENT TEMPERATURE
2
THERMAL IMPEDANCE
ZθJA, NORMALIZED
1
0.1
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
RθJA = 230oC/W
PDM
t1
0.01
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
SINGLE PULSE
0.001
10-5
10-4
10-3
10-2
10-1
100
101
102
103
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
-300
RθJA = 230oC/W
IDM, PEAK CURRENT (A)
POWER DISSIPATION MULTIPLIER
1.2
TC = 25oC
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
-100
VGS = -4.5V
I = I25
150 - TA
125
VGS = -2.5V
-10
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
-1
10-5
10-4
10-3
10-2
10-1
100
t, PULSE WIDTH (s)
FIGURE 4. PEAK CURRENT CAPABILITY
3
101
102
103
ITF87056DQT
Typical Performance Curves
(Continued)
100ms
-10
1ms
-1
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
RθJA
-0.1
-15
SINGLE PULSE
TJ = MAX RATED
TA = 25oC
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
-100
10ms
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
-12
-9
-6
TJ = 150oC
-3
TJ = -55oC
-1
-10
0
-0.5
-40
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TA = 25oC
ID, DRAIN CURRENT (A)
VGS = -4.5V
VGS = -3V
VGS = -2.5V
-9
VGS = -2V
-6
-3
100
VGS = -1.5V
0
0
-0.5
-1.0
-1.5
-2.5
90
80
ID = -5A
70
ID = -2.5A
60
50
40
30
-1
-2.0
-2
-3
-4
-5
VGS, GATE TO SOURCE VOLTAGE (V)
FIGURE 7. SATURATION CHARACTERISTICS
FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
1.4
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = VDS, ID = -250µA
1.4
1.2
1.0
0.8
VGS = -4.5V, ID = -5A
0.6
0.4
-80
-40
0
40
80
120
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
4
160
NORMALIZED GATE
THRESHOLD VOLTAGE
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
-2.0
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDS, DRAIN TO SOURCE VOLTAGE (V)
1.6
-1.5
FIGURE 6. TRANSFER CHARACTERISTICS
rDS(ON), DRAIN TO SOURCE
ON RESISTANCE (mΩ)
-15
-1.0
VGS, GATE TO SOURCE VOLTAGE (V)
VDS, DRAIN TO SOURCE VOLTAGE (V)
-12
TJ = 25oC
= 230oC/W
1.2
1.0
0.8
0.6
0.4
-80
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
ITF87056DQT
Typical Performance Curves
(Continued)
2000
VGS = 0V, f = 1MHz
ID = -250µA
CISS = CGS + CGD
1000
C, CAPACITANCE (pF)
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
1.10
1.05
1.00
0.95
COSS ≅ CDS + CGD
100
CRSS = CGD
0.90
-80
-40
0
40
80
120
50
-0.1
160
-1
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
1500
VDD = -10V
VGS = -2.5V, VDD = -10V, ID = -2.5A
-4
-3
-2
WAVEFORMS IN
DESCENDING ORDER:
ID = -5A
ID = -2.5A
-1
0
2
4
6
1000
tf
750
td(OFF)
500
td(ON)
8
0
10
Qg, GATE CHARGE (nC)
20
1500
VGS = -4.5V, VDD = -10V, ID = -5A
td(OFF)
SWITCHING TIME (ns)
1250
1000
tf
750
tr
500
td(ON)
250
10
20
30
40
RGS, GATE TO SOURCE RESISTANCE (Ω)
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
5
40
FIGURE 14. SWITCHING TIME vs GATE RESISTANCE
FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
0
30
RGS, GATE TO SOURCE RESISTANCE (Ω)
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
0
tr
1250
250
0
-20
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
SWITCHING TIME (ns)
VGS , GATE TO SOURCE VOLTAGE (V)
-5
-10
VDS , DRAIN TO SOURCE VOLTAGE (V)
50
50
ITF87056DQT
Test Circuits and Waveforms
Qgs
VDS
RL
Qgd
VDS
Qg(TH)
0
VGS = -0.5V
VGS
VGS = -2V
-VGS
VDD
Qg(-2)
+
VGS = -4.5V
VDD
DUT
Ig(REF)
Qg(TOT)
0
Ig(REF)
FIGURE 16. GATE CHARGE TEST CIRCUIT
FIGURE 17. GATE CHARGE WAVEFORMS
tON
tOFF
td(OFF)
td(ON)
RL
VDS
-
VDS
0V
DUT
0
90%
90%
10%
-VGS
50%
VGS
FIGURE 18. SWITCHING TIME TEST CIRCUIT
6
10%
10%
+
VGS
RGS
tf
tr
0
50%
PULSE WIDTH
90%
FIGURE 19. SWITCHING TIME WAVEFORM
ITF87056DQT
Thermal Resistance vs Mounting Pad Area
The maximum rated junction temperature, TJM, and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, PDM, in an
application. Therefore the application’s ambient temperature,
TA (oC), and thermal resistance RθJA (oC/W) must be
reviewed to ensure that TJM is never exceeded. Equation 1
mathematically represents the relationship and serves as
the basis for establishing the rating of the part.
( T JM – T A )
P DM = ------------------------------R θJA
300
Rθβ, RθJA (oC/W)
250
(EQ. 1)
230 oC/W - 0.0022in2
RθJA = 138.68- 14.95 * ln(AREA)
199 oC/W - 0.017in2
200
150
100
50
Rθβ = 63.46 - 15.08 * ln(AREA)
0
0.001
In using surface mount devices such as the TSSOP-8
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
power dissipation ratings. Precise determination of PDM is
complex and influenced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
Rθβ
Intersil provides thermal information to assist the designer’s
preliminary application evaluation. Figure 20 defines the
RθJA for the device as a function of the top copper
(component side) area. This is for a horizontally positioned
FR-4 board with 1oz copper after 1000 seconds of steady
state power with no air flow. This graph provides the
necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Intersil device Spice
thermal model or manually utilizing the normalized maximum
transient thermal impedance curve.
Displayed on the curve are RθJA values listed in the
Electrical Specifications table. The points were chosen to
depict the compromise between the copper board area, the
thermal resistance and ultimately the power dissipation,
PDM .
1
While Equation 2 describes the thermal resistance of a
single die, several devices are offered with two die in the
TSSOP-8 package. The dual die TSSOP-8 package
introduces an additional thermal component, thermal
coupling resistance, Rθβ. Equation 3 describes Rθβ as a
function of the top copper mounting pad area.
4. The use of thermal vias.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
0.1
FIGURE 20. THERMAL RESISTANCE vs MOUNTING PAD AREA
3. The use of external heat sinks.
5. Air flow and board orientation.
0.01
AREA, TOP COPPER AREA (in2) PER DIE
= 63.46 – 15.08 ×
ln ( Area )
(EQ. 3)
The thermal coupling resistance vs copper area is also
graphically depicted in Figure 20. It is important to note the
thermal resistance (RθJA) and thermal coupling resistance
(Rθβ) are equivalent for both die. For example at 0.1 square
inches of copper:
RθJA1 = RθJA2 = 173oC/W
Rθβ1 = Rθβ2 = 98oC/W
TJ1 and TJ2 define the junction temperature of the
respective die. Similarly, P1 and P2 define the power
dissipated in each die. The steady state junction
temperature can be calculated using Equation 4 for die 1
and Equation 5 for die 2.
Example: To calculate the junction temperature of each die
when die 2 is dissipating 0.5W and die 1 is dissipating 0W.
The ambient temperature is 70oC and the package is
mounted to a top copper area of 0.1 square inches per die.
Use Equation 4 to calculate TJ1 and Equation 5 to calculate
TJ2 .
.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 20 or by calculation using
Equation 2. RθJA is defined as the natural log of the area
times a coefficient added to a constant. The area, in square
inches is the top copper area including the gate and source
pads.
R θJA = 138.68 – 14.95 ×
ln ( Area )
7
(EQ. 2)
T J1 = P 1 R θJA + P 2 R θβ + T A
(EQ. 4)
o
o
TJ1 = (0 Watts)(173 C/W) + (0.5 Watts)(98 C/W) + 70oC
TJ1 = 119oC
T J2 = P 2 R θJA + P 1 R θβ + T A
(EQ. 5)
o
o
TJ2 = (0.5 Watts)(173 C/W) + (0 Watts)(98 C/W) + 70oC
ITF87056DQT
TJ2 = 156.5oC
The transient thermal impedance (ZθJA) is also affected by
varied top copper board area. Figure 21 shows the effect of
copper pad area on single pulse transient thermal
impedance. Each trace represents a copper pad area in
square inches corresponding to the descending list in the
graph. Spice and SABER thermal models are provided for
each of the listed pad areas.
Copper pad area has no perceivable effect on transient
thermal impedance for pulse widths less than 100ms. For
pulse widths less than 100ms the transient thermal
impedance is determined by the die and package. Therefore,
CTHERM1 through CTHERM5 and RTHERM1 through
RTHERM5 remain constant for each of the thermal models. A
listing of the model component values is available in Table 1.
ZθJA, THERMAL
IMPEDANCE (oC/W)
200
150
COPPER BOARD AREA - DESCENDING ORDER
0.02 in2
0.14 in2
0.26 in2
0.38 in2
100
0.50 in2
50
0
10-1
100
101
t, RECTANGULAR PULSE DURATION (s)
FIGURE 21. THERMAL IMPEDANCE vs MOUNTING PAD AREA
8
102
103
ITF87056DQT
PSPICE Electrical Model
.SUBCKT ITF87056DQT 2 1 3 ;
REV January 2000
CA 12 8 9.3e-10
CB 15 14 10.5e-10
CIN 6 8 6.3e-10
LDRAIN
ESG
DBODY 5 7 DBODYMOD
DBREAK 7 11 DBREAKMOD
DESD1 91 9 DESD1MOD
DESD2 91 7 DESD2MOD
DPLCAP 10 6 DPLCAPMOD
DRAIN
2
5
+
8
6
RLDRAIN
RSLC1
51
+
RSLC2
5
51
EBREAK 5 11 17 18 -28.75
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 5 10 8 6 1
EVTHRES 6 21 19 8 1
EVTEMP 6 20 18 22 1
EBREAK
-
ESLC
9
-
20
DBODY
RDRAIN
EVTHRES
+ 19 8
EVTEMP
RGATE
GATE
1
21
16
MWEAK
6
18 +
22
DBREAK
MSTRO
DESD1
91
DESD2
11
MMED
RLGATE
LDRAIN 2 5 1.0e-9
LGATE 1 9 1.04e-9
LSOURCE 3 7 1.29e-10
LSOURCE
CIN
8
SOURCE
3
7
RSOURCE
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RLSOURCE
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 17e-3
RGATE 9 20 685
RLDRAIN 2 5 10
RLGATE 1 9 10.4
RLSOURCE 3 7 1.29
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 17e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A
12
S2A
13
8
14
13
S1B
CA
RBREAK
15
17
18
RVTEMP
S2B
13
CB
6
8
EGS
19
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
-
IT
14
+
+
S1A
S1B
S2A
S2B
+
17
18
50
DPLCAP
LGATE
IT 8 17 1
-
10
VBAT
5
8
EDS
-
+
8
22
RVTHRES
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*120),2.1))}
.MODEL DBODYMOD D (IS = 2.4e-11 IKF = 0.08 RS = 1.55e-2 TRS1 = 1.7e-3 TRS2 = 2e-6 CJO = 3.2e-10 TT = 3e-9 M = 0.4)
.MODEL DBREAKMOD D (RS = 2e-1 TRS1 = 5e-3 TRS2 = 2e-6)
.MODEL DESD1MOD D (BV = 14.1 TBV1 = -1.21e-3 N = 9 RS = 160)
.MODEL DESD2MOD D (BV = 14 TBV1 = -1.21e-3 N = 9 RS = 180)
.MODEL DPLCAPMOD D (CJO = 3.7e-10 IS = 1e-30 N = 10 M = 0.5 VJ = 0.45)
.MODEL MMEDMOD PMOS (VTO = -0.95 KP = 1.7 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 685 RS = 0.1)
.MODEL MSTROMOD PMOS (VTO = -1.21 KP = 43.7 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD PMOS (VTO = -0.76 KP = 0.06 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 6850 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 8.5e-4 TC2 = -1.1e-6)
.MODEL RDRAINMOD RES (TC1 = 9e-3 TC2 = -1.5e-5)
.MODEL RSLCMOD RES (TC1 = 1e-3 TC2 = 1e-6)
.MODEL RSOURCEMOD RES (TC1 = 5e-4 TC2 = 1e-6)
.MODEL RVTHRESMOD RES (TC1 = 1.2e-3 TC2 = 2e-6)
.MODEL RVTEMPMOD RES (TC1 = -3.5e-4 TC2 = -1e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5
.MODEL S1BMOD VSWITCH (RON = 1e-5
.MODEL S2AMOD VSWITCH (RON = 1e-5
.MODEL S2BMOD VSWITCH (RON = 1e-5
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
VON = 2.5
VON = 1.5
VON = 0.8
VON = 0.1
VOFF= 1.5)
VOFF= 2.5)
VOFF= 0.1)
VOFF= 0.8)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
9
ITF87056DQT
SABER Electrical Model
REV January 2000
template ITF87056DQT n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl = 2.4e-11, ikf = 0.08, cjo = 3.2e-10, tt = 3e-9, m = 0.4, rs = 1.55e-2, trs1 = 1.7e-3, trs2 = 2e-6)
dp..model dbreakmod = (rs = 2e-1, trs1 = 5e-3, trs2 = 2e-6)
dp..model desd1mod = (bv = 14.1, tbv1 = -1.21e-3, nl = 9, rs = 160)
dp..model desd2mod = (bv = 14, tbv1 = -1.21e-3, nl = 9, rs = 180)
dp..model dplcapmod = (cjo = 3.7e-10, isl = 10e-30, nl = 10, m = 0.5, vj = 0.45)
m..model mmedmod = (type=_p, vto = -0.95, kp = 1.7, is = 1e-30, tox = 1, rs = 0.1)
m..model mstrongmod = (type=_p, vto = -1.21, kp = 43.7, is = 1e-30, tox = 1)
m..model mweakmod = (type=_p, vto = -0.76, kp = 0.06, is = 1e-30, tox = 1, rs = 0.1)
ESG
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = 2.5, voff = 1.5)
5
- 8 +
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = 1.5, voff = 2.5)
6
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = 0.8, voff = 0.1)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.1, voff = 0.8)
10
DRAIN
2
RLDRAIN
+
EBREAK 17
18
RSLC1
51
c.ca n12 n8 = 9.3e-10
c.cb n15 n14 = 10.5e-10
c.cin n6 n8 = 6.3e-10
LDRAIN
RSLC2
-
ISCL
11
dp.dbody n5 n7 = model=dbodymod
dp.dbreak n7 n11 = model=dbreakmod
dp.desd1 n91 n9 = model=desd1mod
dp.desd2 n91 n7 = model=desd2mod
dp.dplcap n10 n6 = model=dplcapmod
DBREAK
RDRAIN
LGATE
l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 1.04e-9
l.lsource n3 n7 = 1.29e-10
RLGATE
EVTHRES
+ 19 8
EVTEMP
RGATE
GATE
1
i.it n8 n17 = 1
50
DPLCAP
-
20
9
16
21
MWEAK
6
18 +
22
MSTRO
DESD1
LSOURCE
CIN
91
8
DESD2
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
res.rbreak n17 n18 = 1, tc1 = 8.5e-4, tc2 = -1.1e-6
res.rdrain n50 n16 = 17e-3, tc1 = 9e-3, tc2 = -1.5e-5
res.rgate n9 n20 = 685
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 10.4
res.rlsource n3 n7 = 1.29
res.rslc1 n5 n51 = 1e-6, tc1 = 1e-3, tc2 = 1e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 17e-3, tc1 = 5e-4, tc2 = 1e-6
res.rvtemp n18 n19 = 1, tc1 = -3.5e-4, tc2 = -1e-6
res.rvthres n22 n8 = 1, tc1 = 1.2e-3, tc2 = 2e-6
DBODY
MMED
7
RSOURCE
RLSOURCE
S1A
12
CA
S2A
RBREAK
13
8
15
14
13
S1B
17
18
RVTEMP
S2B
13
CB
6
8
EGS
19
-
-
IT
14
+
+
VBAT
5
8
EDS
-
+
8
22
RVTHRES
spe.ebreak n5 n11 n17 n18 = -28.75
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n5 n10 n8 n6 = 1
spe.evtemp n6 n20 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/120))** 2.1))
}
}
10
SOURCE
3
ITF87056DQT
SPICE Thermal Model
REV 26 January 2000
ITF87056DQT
Copper Area = 0.50 in2
CTHERM1 th 8 6.7e-4
CTHERM2 8 7 2.2e-3
CTHERM3 7 6 5.0e-3
CTHERM4 6 5 8.6e-3
CTHERM5 5 4 2.2e-2
CTHERM6 4 3 0.08
CTHERM7 3 2 0.32
CTHERM8 2 tl 1.9
th
JUNCTION
CTHERM1
RTHERM1
8
CTHERM2
RTHERM2
RTHERM1 th 8 0.267
RTHERM2 8 7 0.893
RTHERM3 7 6 2.23
RTHERM4 6 5 14.28
RTHERM5 5 4 21.42
RTHERM6 4 3 23.0
RTHERM7 3 2 27.0
RTHERM8 2 tl 29.0
7
CTHERM3
RTHERM3
6
RTHERM4
SABER Thermal Model
CTHERM4
5
Copper Area = 0.50 in2
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 8 = 6.7e-4
ctherm.ctherm2 8 7 = 2.2e-3
ctherm.ctherm3 7 6 = 5.0e-3
ctherm.ctherm4 6 5 = 8.6e-3
ctherm.ctherm5 5 4 = 2.2e-2
ctherm.ctherm6 4 3 = 0.08
ctherm.ctherm7 3 2 = 0.32
ctherm.ctherm8 2 tl = 1.9
CTHERM5
RTHERM5
4
RTHERM6
CTHERM6
3
CTHERM7
RTHERM7
rtherm.rtherm1 th 8 = 0.267
rtherm.rtherm2 8 7 = 0.893
rtherm.rtherm3 7 6 = 2.23
rtherm.rtherm4 6 5 = 14.28
rtherm.rtherm5 5 4 = 21.42
rtherm.rtherm6 4 3 = 23.0
rtherm.rtherm7 3 2 = 27.0
rtherm.rtherm8 2 tl = 29.0
}
2
CTHERM8
RTHERM8
tl
AMBIENT
TABLE 1. THERMAL MODELS
0.02 in2
0.14 in2
0.26 in2
0.38 in2
0.50 in2
CTHERM6
0.07
0.05
0.06
0.07
0.08
CTHERM7
0.15
0.24
0.25
0.28
0.32
CTHERM8
0.68
1.3
1.6
2.0
1.9
RTHERM6
22.8
21
21
25
23
RTHERM7
39.5
30
32
30
27
RTHERM8
56
45
38
34
29
COMPONENT
11
ITF87056DQT
MO-153AA (TSSOP-8)
8 LEAD JEDEC MO-153AA TSSOP PLASTIC PACKAGE
E
INCHES
A
E1
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.041
0.047
1.05
1.20
-
A1
0.002
0.006
0.05
0.15
-
b
0.010
0.012
0.25
0.30
-
8
A1
e
D
c
0.127
-
4
5
0.005
b
c
D
0.114
0.122
2.90
3.10
2
E
0.244
0.260
6.20
6.60
-
E1
0.170
0.177
4.30
4.50
3
e
0.004 IN
0.10mm
L
0o-8o
0.015
0.4
0.035
0.9
0.025
0.65
0.232
5.9
0.077
1.95
L
0.025 BSC
0.020
0.028
0.65 BSC
0.50
0.70
4
NOTES:
1. These dimensions are within allowable dimensions of Rev. E of
JEDEC MO-153AA outline dated 10-97.
2. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.006 inches (0.15mm) per side.
3. Dimension “E1” does not include inter-lead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.010 inches
(0.25mm) per side.
4. “L” is the length of terminal for soldering.
5. Controlling dimension: Millimeter
6. Revision 2 dated: 1-00.
MO-153AA (TSSOP-8)
12mm TAPE AND REEL
20.4mm
1.5mm
DIA. HOLE
4.0mm
2.0mm
13mm
1.75mm
CL
12mm
330mm
53.5mm
8.0mm
13.4mm
USER DIRECTION OF FEED
COVER TAPE
GENERAL INFORMATION
1. 3000 PIECES PER REEL.
2. ORDER IN MULTIPLES OF FULL REELS ONLY.
3. MEETS EIA-481 REVISION "A" SPECIFICATIONS.
12
ITF87056DQT
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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13
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