HUF75531SK8
TM
Data Sheet
April 2000
File Number
4848
6A, 80V, 0.030 Ohm, N-Channel,
UltraFET Power MOSFET
Packaging
JEDEC MS-012AA
Features
BRANDING DASH
• Ultra Low On-Resistance
- rDS(ON) = 0.030Ω, VGS = 10V
5
1
2
3
4
• Simulation Models
- Temperature Compensated PSPICE™ and SABER©
Electrical Models
- Spice and SABER© Thermal Impedance Models
- www.intersil.com
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
Symbol
SOURCE (1)
DRAIN (8)
SOURCE (2)
DRAIN (7)
SOURCE (3)
DRAIN (6)
GATE (4)
DRAIN (5)
Absolute Maximum Ratings
Ordering Information
PART NUMBER
HUF75531SK8
PACKAGE
MS-012AA
BRAND
75531SK8
NOTE: When ordering, use the entire part number. Add the suffix T
to obtain the variant in tape and reel, e.g., HUF75531SK8T.
TA = 25oC, Unless Otherwise Specified
HUF75531SK8
UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
80
V
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDGR
80
V
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
±20
V
Drain Current
Continuous (TA= 25oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID
Continuous (TA= 100oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM
6
4
Figure 4
A
A
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UIS
Figures 6, 14, 15
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5
20
W
mW/oC
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
Package Body for 10s, See Techbrief TB370 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg
-55 to 150
oC
300
260
oC
oC
NOTES:
1. TJ = 25oC to 125oC.
2. 50oC/W measured using FR-4 board with 0.76 in2 (490.3 mm2) copper pad at 10 second.
3. 152oC/W measured using FR-4 board with 0.054 in2 (34.8 mm2) copper pad at 1000 seconds
4. 189oC/W measured using FR-4 board with 0.0115 in2 (7.42 mm2) copper pad at 1000 seconds
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
1
CAUTION: These devices are sensitive to electrostatic discharge. Follow proper ESD Handling Procedures.
UltraFET™ is a trademark of Intersil Corporation. PSPICE® is a registered trademark of MicroSim Corporation.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000
HUF75531SK8
TA = 25oC, Unless Otherwise Specified
Electrical Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
80
-
-
V
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
BVDSS
IDSS
Gate to Source Leakage Current
IGSS
ID = 250µA, VGS = 0V (Figure 11)
VDS = 75V, VGS = 0V
-
-
1
µA
VDS = 70V, VGS = 0V, TA = 150oC
-
-
250
µA
VGS = ±20V
-
-
±100
nA
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250µA (Figure 10)
2
-
4
V
Drain to Source On Resistance
rDS(ON)
ID = 6A, VGS = 10V (Figure 9)
-
0.025
0.030
Ω
Pad Area = 0.76 in2 (490.3 mm2) (Note 2)
-
-
50
oC/W
Pad Area = 0.054 in2 (34.8 mm2) (Note 3)
-
-
152
oC/W
189
oC/W
THERMAL SPECIFICATIONS
Thermal Resistance Junction to
Ambient
RθJA
Pad Area = 0.0115 in2 (7.42 mm2)(Note 4)
SWITCHING SPECIFICATIONS (VGS = 10V)
Turn-On Time
tON
Turn-On Delay Time
td(ON)
Rise Time
Fall Time
Turn-Off Time
-
-
55
ns
-
10.5
-
ns
-
25
-
ns
td(OFF)
-
49
-
ns
tf
-
29
-
ns
tOFF
-
-
115
ns
-
68
82
nC
tr
Turn-Off Delay Time
VDD = 40V, ID = 6A
VGS = 10V,
RGS = 6.8Ω
(Figures 18, 19)
GATE CHARGE SPECIFICATIONS
Qg(TOT)
VGS = 0V to 20V
Gate Charge at 10V
Qg(10)
VGS = 0V to 10V
Threshold Gate Charge
Qg(TH)
VGS = 0V to 2V
Total Gate Charge
VDD = 40V,
ID = 6A,
Ig(REF) = 1.0mA
(Figures 13, 16, 17)
-
37
45
nC
-
2.4
2.9
nC
Gate to Source Gate Charge
Qgs
-
4.8
-
nC
Gate to Drain "Miller" Charge
Qgd
-
14
-
nC
-
1210
-
pF
-
385
-
pF
-
115
-
pF
CAPACITANCE SPECIFICATIONS
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
VDS = 25V, VGS = 0V,
f = 1MHz
(Figure 12)
Source to Drain Diode Specifications
PARAMETER
SYMBOL
Source to Drain Diode Voltage
VSD
Reverse Recovery Time
Reverse Recovered Charge
2
MIN
TYP
MAX
UNITS
ISD = 6A
TEST CONDITIONS
-
-
1.25
V
ISD = 4A
-
-
1.00
V
trr
ISD = 6A, dISD/dt = 100A/µs
-
-
105
ns
QRR
ISD = 6A, dISD/dt = 100A/µs
-
-
325
nC
HUF75531SK8
Typical Performance Curves
8
VGS = 10V, RθJA = 50oC/W
1.0
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
1.2
0.8
0.6
0.4
6
4
2
0.2
0
0
25
50
75
100
125
0
150
25
50
TA , AMBIENT TEMPERATURE (oC)
75
100
125
150
TA, AMBIENT TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs
CASE TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
3
ZθJA, NORMALIZED
THERMAL IMPEDANCE
1
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
RθJA = 50oC/W
0.1
PDM
t1
0.01
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
SINGLE PULSE
0.001
10-5
10-4
10-3
10-2
10-1
100
101
102
103
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
500
TA = 25oC
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
IDM, PEAK CURRENT (A)
RθJA = 50oC/W
100
VGS = 10V
I = I25
150 - TA
125
10
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
1
10-5
10-4
10-3
10-2
10-1
100
t, PULSE WIDTH (s)
FIGURE 4. PEAK CURRENT CAPABILITY
3
101
102
103
HUF75531SK8
Typical Performance Curves
(Continued)
200
RθJA = 50oC/W
100
ID, DRAIN CURRENT (A)
IAS, AVALANCHE CURRENT (A)
200
100µs
10
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
1
1ms
10ms
SINGLE PULSE
TJ = MAX RATED
TA = 25oC
100
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
STARTING TJ = 25oC
10
STARTING TJ = 150oC
1
0.01
0.1
1
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
100
200
0.1
1
100
10
tAV, TIME IN AVALANCHE (ms)
NOTE: Refer to Intersil Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
30
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
25
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
30
20
15
TJ = 150oC
10
TJ = -55oC
VGS = 20V
VGS = 10V
25
20
VGS = 7V
VGS = 6V
15
10
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TA = 25oC
5
5
TJ = 25oC
0
0
2.0
3.0
4.0
5.0
0
6.0
0.5
1.0
1.5
2.0
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS, GATE TO SOURCE VOLTAGE (V)
FIGURE 7. TRANSFER CHARACTERISTICS
FIGURE 8. SATURATION CHARACTERISTICS
2.5
1.2
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = VDS, ID = 250µA
NORMALIZED GATE
THRESHOLD VOLTAGE
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
VGS =5V
2.0
1.5
1.0
1.0
0.8
VGS = 10V, ID = 6A
0.5
-80
-40
0
40
80
120
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
4
160
0.6
-80
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
HUF75531SK8
Typical Performance Curves
(Continued)
3000
VGS = 0V, f = 1MHz
ID = 250µA
C, CAPACITANCE (pF)
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
1.2
1.1
1.0
CISS = CGS + CGD
1000
COSS ≅ CDS + CGD
100
CRSS = CGD
0.9
-80
-40
0
40
80
120
30
0.1
160
TJ , JUNCTION TEMPERATURE (oC)
1.0
10
80
VDS , DRAIN TO SOURCE VOLTAGE (V)
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
VGS , GATE TO SOURCE VOLTAGE (V)
10
VDD = 40V
8
6
4
WAVEFORMS IN
DESCENDING ORDER:
ID = 6A
ID = 1A
2
0
0
10
20
30
Qg, GATE CHARGE (nC)
40
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
Test Circuits and Waveforms
VDS
BVDSS
L
VARY tP TO OBTAIN
REQUIRED PEAK IAS
tP
+
RG
VDS
IAS
VDD
VDD
-
VGS
DUT
0V
tP
IAS
0
0.01Ω
tAV
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
5
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
HUF75531SK8
Test Circuits and Waveforms
(Continued)
VDS
VDD
RL
Qg(TOT)
VDS
VGS = 20V
VGS
Qg(10)
+
VDD
VGS = 10V
VGS
DUT
VGS = 2V
Ig(REF)
0
Qg(TH)
Qgs
Qgd
Ig(REF)
0
FIGURE 16. GATE CHARGE TEST CIRCUIT
FIGURE 17. GATE CHARGE WAVEFORMS
VDS
tON
tOFF
td(ON)
td(OFF)
tf
tr
RL
VDS
90%
90%
+
VGS
VDD
10%
10%
0
DUT
90%
RGS
VGS
VGS
0
FIGURE 18. SWITCHING TIME TEST CIRCUIT
10%
50%
50%
PULSE WIDTH
FIGURE 19. SWITCHING TIME WAVEFORM
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM, and the
thermal resistance of the heat dissipating path determines the
maximum allowable device power dissipation, PDM, in an
application. Therefore the application’s ambient temperature,
TA (oC), and thermal resistance RθJA (oC/W) must be reviewed
to ensure that TJM is never exceeded. Equation 1
mathematically represents the relationship and serves as the
basis for establishing the rating of the part.
dissipation ratings. Precise determination of PDM is complex
and influenced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the board.
3. The use of external heat sinks.
4. The use of thermal vias.
( T JM – T A )
P DM = ------------------------------Z θJA
(EQ. 1)
In using surface mount devices such as the SOP-8 package,
the environment in which it is applied will have a significant
influence on the part’s current and maximum power
6
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Intersil provides thermal information to assist the designer’s
preliminary application evaluation. Figure 20 defines the
HUF75531SK8
RθJA for the device as a function of the top copper
(component side) area. This is for a horizontally positioned
FR-4 board with 1oz copper after 1000 seconds of steady
state power with no air flow. This graph provides the
necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Intersil device Spice
thermal model or manually utilizing the normalized maximum
transient thermal impedance curve.
graph. Spice and SABER thermal models are provided for
each of the listed pad areas.
Copper pad area has no perceivable effect on transient
thermal impedance for pulse widths less than 100ms. For
pulse widths less than 100ms the transient thermal
impedance is determined by the die and package. Therefore,
CTHERM1 through CTHERM5 and RTHERM1 through
RTHERM5 remain constant for each of the thermal models. A
listing of the model component values is available in Table 1.
Displayed on the curve are RθJA values listed in the Electrical
Specifications table. The points were chosen to depict the
compromise between the copper board area, the thermal
resistance and ultimately the power dissipation, PDM.
R θJA = 83.2 – 23.6 ×
ln ( Area )
RθJA = 83.2 - 23.6*ln(AREA)
200
RθJA (oC/W)
Thermal resistances corresponding to other copper areas can
be obtained from Figure 20 or by calculation using Equation 2.
RθJA is defined as the natural log of the area times a coefficient
added to a constant. The area, in square inches is the top
copper area including the gate and source pads.
240
189oC/W - 0.0115in2
152oC/W - 0.054in2
160
120
(EQ. 2)
80
The transient thermal impedance (ZθJA) is also effected by
varied top copper board area. Figure 21 shows the effect of
copper pad area on single pulse transient thermal
impedance. Each trace represents a copper pad area in
square inches corresponding to the descending list in the
0.01
0.1
1.0
AREA, TOP COPPER AREA (in2)
FIGURE 20. THERMAL RESISTANCE vs MOUNTING PAD AREA
150
ZθJA, THERMAL
IMPEDANCE (oC/W)
120
90
COPPER BOARD AREA - DESCENDING ORDER
0.04 in2
0.28 in2
0.52 in2
0.76 in2
1.00 in2
60
30
0
10-1
100
101
t, RECTANGULAR PULSE DURATION (s)
FIGURE 21. THERMAL IMPEDANCE vs MOUNTING PAD AREA
7
102
103
HUF75531SK8
PSPICE Electrical Model
.SUBCKT HUF75531SK8 2 1 3 ;
rev 22 Feb 2000
CA 12 8 2.00e-9
CB 15 14 2.00e-9
CIN 6 8 1.09e-9
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
LDRAIN
DPLCAP
DRAIN
2
5
10
5
51
ESLC
11
-
RDRAIN
6
8
EVTHRES
+ 19 8
+
LGATE
GATE
1
EVTEMP
RGATE +
18 22
9
20
21
DBODY
-
16
MWEAK
6
MMED
MSTRO
RLGATE
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
+
17
EBREAK 18
50
-
IT 8 17 1
LSOURCE
CIN
8
SOURCE
3
7
RSOURCE
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 9.30e-3
RGATE 9 20 1.70
RLDRAIN 2 5 10
RLGATE 1 9 11.2
RLSOURCE 3 7 1.29
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 11.35e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A
S1B
S2A
S2B
DBREAK
+
RSLC2
ESG
LDRAIN 2 5 1.0e-9
LGATE 1 9 1.12e-9
LSOURCE 3 7 1.29e-10
RLDRAIN
RSLC1
51
EBREAK 11 7 17 18 86.60
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
RLSOURCE
S2A
S1A
12
S1B
CA
17
18
RVTEMP
S2B
13
CB
6
8
EGS
19
VBAT
5
8
EDS
-
-
IT
14
+
+
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
RBREAK
15
14
13
13
8
-
+
8
22
RVTHRES
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*125),2))}
.MODEL DBODYMOD D (IS = 1.06e-12 RS = 5.86e-3 TRS1 = 4.97e-5 TRS2 = 2.11e-6 CJO = 1.51e-9 TT = 1.05e-7 M = 0.53)
.MODEL DBREAKMOD D (RS = 4.45e-1 TRS1 = 1.02e-3 TRS2 = 0)
.MODEL DPLCAPMOD D (CJO = 1.48e-9 IS = 1e-30 M = 0.78)
.MODEL MMEDMOD NMOS (VTO = 3.18 KP = 2.55 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1.70)
.MODEL MSTROMOD NMOS (VTO = 3.67 KP = 55 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 2.83 KP = 0.1 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 17.0 Rs = 0.10)
.MODEL RBREAKMOD RES (TC1 = 1.21e-3 TC2 = 0)
.MODEL RDRAINMOD RES (TC1 = 1.32e-2 TC2 = 3.21e-5)
.MODEL RSLCMOD RES (TC1 = 4.00e-3 TC2 = 0)
.MODEL RSOURCEMOD RES (TC1 = 1.00e-3 TC2 = 0)
.MODEL RVTHRESMOD RES (TC1 = -2.56e-3 TC2 = -9.91e-6)
.MODEL RVTEMPMOD RES (TC1 = -2.44e-3 TC2 = 0)
.MODEL S1AMOD VSWITCH (RON = 1e-5
.MODEL S1BMOD VSWITCH (RON = 1e-5
.MODEL S2AMOD VSWITCH (RON = 1e-5
.MODEL S2BMOD VSWITCH (RON = 1e-5
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
VON = -6.0 VOFF= -4.0)
VON = -4.0 VOFF= -6.0)
VON = -3.0 VOFF= 0.0)
VON = 0.0 VOFF= -3.0)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
8
HUF75531SK8
SABER Electrical Model
REV 22 feb 2000
template huf75531sk8 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (is = 1.06e-12, rs=5.86e-3, trs1=4.97e-5, trs2=2.11e-6, cjo = 1.51e-9, tt = 1.05e-7, m = 0.53)
dp..model dbreakmod = (rs=4.45e-1, trs1=1.02e-3, trs2= 0)
dp..model dplcapmod = (cjo = 1.48e-9, is = 1e-30, m = 0.78)
m..model mmedmod = (type=_n, vto = 3.18, kp = 2.55, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 3.67, kp = 55, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 2.83, kp = 0.1, is = 1e-30, tox = 1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -6.0, voff = -4.0)
DPLCAP 5
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -.4.0, voff = -6.0)
10
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -3.0, voff = 0.0)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.0, voff = -3.0)
RSLC1
LDRAIN
DRAIN
2
RLDRAIN
51
c.ca n12 n8 = 2.00e-9
c.cb n15 n14 = 2.00e-9
c.cin n6 n8 = 1.09e-9
RSLC2
ISCL
EVTHRES
+ 19 8
+
i.it n8 n17 = 1
LGATE
GATE
1
l.ldrain n2 n5 = 1.00e-9
l.lgate n1 n9 = 1.12e-9
l.lsource n3 n7 = 1.29e-10
RDRAIN
6
8
ESG
EVTEMP
RGATE + 18 22
9
20
MWEAK
MSTRO
CIN
DBODY
EBREAK
+
17
18
MMED
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
-
8
LSOURCE
7
RSOURCE
RLSOURCE
S1A
12
S2A
13
8
S1B
CA
RBREAK
15
14
13
17
18
RVTEMP
S2B
13
CB
6
8
EGS
19
-
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/125))** 2))
}
}
-
IT
14
+
+
spe.ebreak n11 n7 n17 n18 = 86.60
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
9
21
11
16
6
RLGATE
res.rbreak n17 n18 = 1, tc1 = 1.21e-3, tc2 = 0
res.rdrain n50 n16 = 9.30e-3, tc1 = 1.32e-2, tc2 = 3.21e-5
res.rgate n9 n20 = 1.70
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 11.2
res.rlsource n3 n7 = 1.29
res.rslc1 n5 n51 = 1e-6, tc1 = 4.00e-3, tc2 = 0
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 11.35e-3, tc1 = 1.00e-3, tc2 = 0
res.rvtemp n18 n19 = 1, tc1 = -2.44e-3, tc2 = 0
res.rvthres n22 n8 = 1, tc1 = -2.56e-3, tc2 = -9.91e-6
DBREAK
50
-
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
VBAT
5
8
EDS
-
+
8
22
RVTHRES
SOURCE
3
HUF75531SK8
SPICE Thermal Model
REV 12 Feb 2000
HUF75531SK8
Copper Area = 0.04 in2
CTHERM1 th 8 2.0e-3
CTHERM2 8 7 5.0e-3
CTHERM3 7 6 1.0e-2
CTHERM4 6 5 4.0e-2
CTHERM5 5 4 9.0e-2
CTHERM6 4 3 1.2e-1
CTHERM7 3 2 0.5
CTHERM8 2 tl 1.3
JUNCTION
th
RTHERM1
CTHERM1
8
RTHERM1 th 8 0.1
RTHERM2 8 7 0.5
RTHERM3 7 6 1.0
RTHERM4 6 5 5.0
RTHERM5 5 4 8.0
RTHERM6 4 3 26
RTHERM7 3 2 39
RTHERM8 2 tl 55
RTHERM2
CTHERM2
7
RTHERM3
CTHERM3
C
SABER Thermal Model
6
Copper Area = 0.04 in2
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 8 = 2.0e-3
ctherm.ctherm2 8 7 = 5.0e-3
ctherm.ctherm3 7 6 = 1.0e-2
ctherm.ctherm4 6 5 = 4.0e-2
ctherm.ctherm5 5 4 = 9.0e-2
ctherm.ctherm6 4 3 = 1.2e-1
ctherm.ctherm7 3 2 = 0.5
ctherm.ctherm8 2 tl = 1.3
CTHERM4
RTHERM4
5
CTHERM5
RTHERM5
4
CTHERM6
RTHERM6
3
rtherm.rtherm1 th 8 = 0.1
rtherm.rtherm2 8 7 = 0.5
rtherm.rtherm3 7 6 = 1.0
rtherm.rtherm4 6 5 = 5.0
rtherm.rtherm5 5 4 = 8.0
rtherm.rtherm6 4 3 = 26
rtherm.rtherm7 3 2 = 39
rtherm.rtherm8 2 tl = 55
CTHERM7
RTHERM7
2
CTHERM8
RTHERM8
CASE
tl
TABLE 1. Thermal Models
0.04 in2
0.28 in2
0.52 in2
0.76 in2
1.0 in2
CTHERM6
1.2e-1
1.5e-1
2.0e-1
2.0e-1
2.0e-1
CTHERM7
0.5
1.0
1.0
1.0
1.0
CTHERM8
1.3
2.8
3.0
3.0
3.0
RTHERM6
26
20
15
13
12
RTHERM7
39
24
21
19
18
RTHERM8
55
38.7
31.3
29.7
25
COMPONENT
10
HUF75531SK8
MS-012AA
8 LEAD JEDEC MS-012AA SMALL OUTLINE PLASTIC PACKAGE
INCHES
E
E1
A
A1
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
NOTES
0.0532
0.0688
1.35
1.75
-
0.004
0.0098
0.10
0.25
-
b
0.013
0.020
0.33
0.51
-
c
0.0075
0.0098
0.19
0.25
-
D
0.189
0.1968
4.80
5.00
2
E
0.2284
0.244
5.80
6.20
-
E1
0.1497
0.1574
3.80
4.00
3
1
A
A1
e
2
6
D
5
b
e
h x 45o
c
0.004 IN
0.10 mm
L
0o-8o
0.060
1.52
0.050
1.27
0.024
0.6
0.155
4.0
0.275
7.0
MINIMUM RECOMMENDED FOOTPRINT FOR
SURFACE-MOUNTED APPLICATIONS
1.5mm
DIA. HOLE
0.050 BSC
1.27 BSC
-
H
0.0099
0.0196
0.25
0.50
-
L
0.016
0.050
0.40
1.27
4
NOTES:
1. All dimensions are within allowable dimensions of Rev. C of
JEDEC MS-012AA outline dated 5-90.
2. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.006 inches (0.15mm) per side.
3. Dimension “E1” does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 0.010 inches
(0.25mm) per side.
4. “L” is the length of terminal for soldering.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. Controlling dimension: Millimeter.
7. Revision 8 dated 5-99.
4.0mm
2.0mm
USER DIRECTION OF FEED
1.75mm
CL
MS-012AA
12mm
12mm TAPE AND REEL
8.0mm
40mm MIN.
ACCESS HOLE
18.4mm
COVER TAPE
13mm
330mm
GENERAL INFORMATION
1. 2500 PIECES PER REEL.
2. ORDER IN MULTIPLES OF FULL REELS ONLY.
3. MEETS EIA-481 REVISION “A” SPECIFICATIONS.
11
50mm
12.4mm
HUF75531SK8
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
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NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
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TEL: (321) 724-7000
FAX: (321) 724-7240
12
EUROPE
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TEL: (32) 2.724.2111
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