HUF76105SK8
Data Sheet
May 1999
5.5A, 30V, 0.050 Ohm, N-Channel, Logic
Level UltraFET Power MOSFET
• Logic Level Gate Drive
• 5.5A, 30V
• Ultra Low On-Resistance, rDS(ON) = 0.050Ω
• Simulation Models
- Temperature Compensated PSPICE® and SABER
Electrical Models
- SPICE and SABER Thermal Impedance Models
Available on the WEB at:
www.semi.Intersil.com/families/models.htm
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Transient Thermal Impedance Curve vs Board Mounting
Area
Formerly developmental type TA76105.
• Related Literature
- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”
Ordering Information
PART NUMBER
PACKAGE
MS-012AA
4719.1
Features
This N-Channel power MOSFET is
manufactured using the innovative
UltraFET™ process. This advanced
process technology achieves the
lowest possible on-resistance per silicon area, resulting in
outstanding performance. This device is capable of
withstanding high energy in the avalanche mode and the
diode exhibits very low reverse recovery time and stored
charge. It was designed for use in applications where power
efficiency is important, such as switching regulators, switching
converters, motor drivers, relay drivers, low-voltage bus
switches, and power management in portable and batteryoperated products.
HUF76105SK8
File Number
BRAND
76105SK8
Symbol
NOTE: When ordering, use the entire part number. Add the suffix T
to obtain the variant in tape and reel, e.g., HUF76105SK8T.
NC(1)
DRAIN(8)
SOURCE(2)
DRAIN(7)
SOURCE(3)
DRAIN(6)
GATE(4)
DRAIN(5)
Packaging
JEDEC MS-012AA
BRANDING DASH
5
1
2
3
8-1
4
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
UltraFET™ is a trademark of Intersil Corporation. PSPICE® is a registered trademark of MicroSim Corporation.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
HUF76105SK8
Absolute Maximum Ratings
TA = 25oC, Unless Otherwise Specified
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
Drain Current
Continuous (TA= 25oC, VGS = 10V) (Figure 2) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TA= 100oC, VGS = 5V) (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TA= 100oC, VGS = 4.5V) (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS
Power Dissipation (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
UNITS
V
V
V
30
30
±16
5.5
1.4
1.3
Figure 4
Figures 6, 17, 18
2.5
20
-55 to 150
A
A
A
W
mW/oC
oC
300
260
oC
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. TJ = 25oC to 125oC.
2. 50oC/W measured using FR-4 board at 1 second.
3. 212oC/W measured using FR-4 board with 0.0115 in2 copper pad at 1000 seconds.
Electrical Specifications
TA = 25oC, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
30
-
-
V
VDS = 25V, VGS = 0V
-
-
1
µA
VDS = 25V, VGS = 0V, TC = 150oC
-
-
250
µA
VGS = ±16V
-
-
±100
nA
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
BVDSS
IDSS
IGSS
ID = 250µA, VGS = 0V (Figure 12)
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250µA (Figure 11)
1
-
3
V
Drain to Source On Resistance
rDS(ON)
ID = 5.5A, VGS = 10V (Figures 9, 10)
-
0.040
0.050
Ω
ID = 1.4A, VGS = 5V (Figure 9)
-
0.055
0.072
Ω
ID = 1.3A, VGS = 4.5V (Figure 9)
-
0.060
0.078
Ω
Pad Area = 0.76 in2 (Note 2)
-
-
50
oC/W
Pad Area = 0.054 in2 (Figure 23)
-
-
175
oC/W
Pad Area = 0.0115 in2 (Figure 23)
-
-
212
oC/W
VDD = 15V, ID ≅ 1.3A, RL = 11.5Ω,
VGS = 4.5V, RGS = 27Ω
(Figures 15, 21, 22)
-
-
60
ns
-
12
-
ns
tr
-
28
-
ns
td(OFF)
-
31
-
ns
tf
-
21
-
ns
tOFF
-
-
80
ns
THERMAL SPECIFICATIONS
Thermal Resistance Junction to Ambient
RθJA
SWITCHING SPECIFICATIONS (VGS = 4.5V)
Turn-On Time
tON
Turn-On Delay Time
td(ON)
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
8-2
HUF76105SK8
Electrical Specifications
TA = 25oC, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
-
-
60
ns
-
17
-
ns
-
21
-
ns
td(OFF)
-
60
-
ns
tf
-
20
-
ns
tOFF
-
-
120
ns
-
9
11
nC
-
5.3
6.4
nC
-
0.35
0.45
nC
SWITCHING SPECIFICATIONS (VGS = 10V)
Turn-On Time
tON
Turn-On Delay Time
td(ON)
Rise Time
tr
Turn-Off Delay Time
Fall Time
Turn-Off Time
VDD = 15V, ID ≅ 5.5A, RL = 2.7Ω,
VGS = 10V,
RGS = 27Ω
(Figures 16, 21, 22)
GATE CHARGE SPECIFICATIONS
Total Gate Charge
Qg(TOT)
VGS = 0V to 10V
Gate Charge at 5V
Qg(5)
VGS = 0V to 5V
Qg(TH)
VGS = 0V to 1V
Threshold Gate Charge
VDD = 15V, ID ≅ 1.4A,
RL = 10.7Ω
Ig(REF) = 1.0mA
(Figures 14, 19, 20)
Gate to Source Gate Charge
Qgs
-
0.8
-
nC
Reverse Transfer Capacitance
Qgd
-
2.5
-
nC
-
325
-
pF
-
180
-
pF
-
35
-
pF
MIN
TYP
MAX
UNITS
-
-
1.25
V
1.00
V
CAPACITANCE SPECIFICATIONS
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
VDS = 25V, VGS = 0V,
f = 1MHz
(Figure 13)
Source to Drain Diode Specifications
PARAMETER
SYMBOL
Source to Drain Diode Voltage
VSD
TEST CONDITIONS
ISD = 5.5A
ISD = 1.4A
Reverse Recovery Time
Reverse Recovered Charge
trr
ISD = 1.4A, dISD/dt = 100A/µs
-
-
39
ns
QRR
ISD = 1.4A, dISD/dt = 100A/µs
-
-
42
nC
1.2
6
1.0
5
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
Typical Performance Curves
0.8
0.6
0.4
VGS = 10V, RθJA = 50oC/W
4
3
2
VGS = 4.5V, RθJA = 212oC/W
1
0.2
0
0
0
25
50
75
100
125
150
TA , AMBIENT TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT
TEMPERATURE
8-3
25
50
75
100
125
150
TA, AMBIENT TEMPERATURE (oC)
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
AMBIENT TEMPERATURE
HUF76105SK8
Typical Performance Curves
ZθJA, NORMALIZED
THERMAL IMPEDANCE
10
1
(Continued)
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
RθJA = 50oC/W
PDM
0.1
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
0.01
SINGLE PULSE
0.001
10-5
10-4
10-3
10-2
10-1
100
101
102
103
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
IDM, PEAK CURRENT (A)
500
RθJA = 50oC/W
TC = 25oC
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
100
VGS = 10V
150 - TA
I = I25
VGS = 5V
125
10
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
1
10-5
10-4
10-3
10-2
10-1
100
101
102
103
t, PULSE WIDTH (s)
FIGURE 4. PEAK CURRENT CAPABILITY
TJ = MAX RATED
TA = 25oC
ID, DRAIN CURRENT (A)
100
100µs
10
1ms
OPERATION IN THIS
AREA MAY BE
LIMITED BY rds(ON)
1
10ms
BVDSS MAX = 30V
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
100
STARTING TJ = 25oC
10
STARTING TJ = 150oC
1
0.1
1
IAS, AVALANCHE CURRENT (A)
20
200
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
0.01
0.1
1
tAV, TIME IN AVALANCHE (ms)
NOTE: Refer to Intersil Application Notes AN9321 and AN9322.
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
8-4
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
10
HUF76105SK8
Typical Performance Curves
25
250µs PULSE TEST
DUTY CYCLE = 0.5% MAX
VDD = 15V
20
VGS = 10V
25oC
-55oC
VGS = 5V
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
25
(Continued)
150oC
15
10
5
20
VGS = 4V
15
10
VGS = 3V
5
TA = 25oC
0
0
0
1
2
3
4
VGS, GATE TO SOURCE VOLTAGE (V)
0
5
FIGURE 7. TRANSFER CHARACTERISTICS
250µs PULSE TEST
DUTY CYCLE = 0.5% MAX
rDS(ON), DRAIN TO SOURCE
ON RESISTANCE (mΩ)
ID = 5.5A
1
2
3
4
VDS, DRAIN TO SOURCE VOLTAGE (V)
5
FIGURE 8. SATURATION CHARACTERISTICS
90
70
ID = 1.4A
50
1.8
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
110
30
VGS = 10V, ID = 5.5A
250µs PULSE TEST
DUTY CYCLE = 0.5% MAX
1.6
1.4
1.2
1.0
0.8
0.6
2
4
6
8
VGS, GATE TO SOURCE VOLTAGE (V)
10
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
-80
-40
0
40
80
120
TJ, JUNCTION TEMPERATURE (oC)
160
FIGURE 10. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
1.15
VGS = VDS, ID = 250µA
1.1
1.0
0.9
0.8
0.7
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
1.2
NORMALIZED GATE
THRESHOLD VOLTAGE
VGS = TEST
3.5V
250µs PULSE
DUTY CYCLE = 0.5% MAX
ID = 250µA
1.1
1.05
1.0
0.95
0.9
-80
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
8-5
-80
-40
0
40
80
120
160
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
HUF76105SK8
Typical Performance Curves
(Continued)
10
VGS , GATE TO SOURCE VOLTAGE (V)
600
VGS = 0V, f = 1MHz
C, CAPACITANCE (pF)
500
400
CISS
300
200
COSS
100
CRSS
VDD = 15V
8
6
4
WAVEFORMS IN
DESCENDING ORDER:
ID = 5.5A
ID = 1.4A
2
0
0
0
0
5
10
15
20
25
30
VDS , DRAIN TO SOURCE VOLTAGE (V)
2
4
6
Qg, GATE CHARGE (nC)
8
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
60
120
VGS = 10V, VDD = 15V, ID = 5.5A, RL= 2.7Ω
VGS = 4.5V, VDD = 15V, ID = 1.3A, RL= 11.5Ω
td(OFF)
SWITCHING TIME (ns)
td(OFF)
SWITCHING TIME (ns)
10
45
tr
30
tf
15
90
60
tr
30
td(ON)
td(ON)
tf
0
0
0
10
20
30
40
RGS, GATE TO SOURCE RESISTANCE (Ω)
0
50
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
10
20
30
40
RGS, GATE TO SOURCE RESISTANCE (Ω)
50
FIGURE 16. SWITCHING TIME vs GATE RESISTANCE
Test Circuits and Waveforms
VDS
BVDSS
L
VARY tP TO OBTAIN
REQUIRED PEAK IAS
tP
+
RG
VDS
IAS
VDD
VDD
-
VGS
DUT
0V
tP
IAS
0
0.01Ω
tAV
FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT
8-6
FIGURE 18. UNCLAMPED ENERGY WAVEFORMS
HUF76105SK8
Test Circuits and Waveforms
(Continued)
VDS
VDD
RL
Qg(TOT)
VDS
VGS = 10V
VGS
Qg(5)
+
VDD
VGS = 5V
VGS
-
VGS = 1V
DUT
0
Ig(REF)
Qg(TH)
Qgs
Qgd
Ig(REF)
0
FIGURE 19. GATE CHARGE TEST CIRCUIT
FIGURE 20. GATE CHARGE WAVEFORMS
VDS
tON
tOFF
td(ON)
td(OFF)
tf
tr
RL
VDS
90%
90%
+
VGS
VDD
10%
10%
0
DUT
90%
RGS
VGS
VGS
0
FIGURE 21. SWITCHING TIME TEST CIRCUIT
10%
50%
50%
PULSE WIDTH
FIGURE 22. SWITCHING TIME WAVEFORM
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM, and the thermal
resistance of the heat dissipating path determines the maximum
allowable device power dissipation, PDM, in an application.
Therefore the application’s ambient temperature, TA(oC), and
thermal resistance RθJA (oC/W) must be reviewed to ensure that
TJM is never exceeded. Equation 1 mathematically represents
the relationship and serves as the basis for establishing the rating of the part.
( T JM – T A )
P DM = ------------------------------Z θJA
(EQ. 1)
ratings. Precise determination of PDM is complex and influenced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
In using surface mount devices such as the SOP-8 package,
the environment in which it is applied will have a significant
influence on the part’s current and maximum power dissipation
8-7
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
HUF76105SK8
Displayed on the curve are RθJA values listed in the Electrical
Specifications table. The points were chosen to depict the
compromise between the copper board area, the thermal
resistance and ultimately the power dissipation, PDM.
Thermal resistances corresponding to other copper areas can
be obtained from Figure 23 or by calculation using Equation 2.
RθJA is defined as the natural log of the area times a coefficient
added to a constant. The area, in square inches is the top
copper area including the gate and source pads.
R θJA = 103.2 – 24.3 ×
ln ( Area )
ZθJA, THERMAL
IMPEDANCE (oC/W)
120
Copper pad area has no perceivable effect on transient thermal
impedance for pulse widths less than 100ms. For pulse widths
less than 100ms the transient thermal impedance is determined by the die and package. Therefore, CTHERM1 through
CTHERM5 and RTHERM1 through RTHERM5 remain constant for each of the thermal models. A listing of the model component values is available in Table 1.
300
250
212 oC/W - 0.0115in2
200
175 oC/W - 0.054in2
150
100
50
RθJA = 103.2 - 24.3 * ln(AREA)
(EQ. 2)
0
The transient thermal impedance (ZθJA) is also effected by varied top copper board area. Figure 24 shows the effect of copper
pad area on single pulse transient thermal impedance. Each
trace represents a copper pad area in square inches corre-
160
sponding to the descending list in the graph. SPICE and SABER
thermal models are provided for each of the listed pad areas.
RθJA (oC/W)
Intersil provides thermal information to assist the designer’s
preliminary application evaluation. Figure 23 defines the RθJA
for the device as a function of the top copper (component side)
area. This is for a horizontally positioned FR-4 board with 1oz
copper after 1000 seconds of steady state power with no air
flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Intersil
device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve.
0.001
0.01
0.1
1
AREA, TOP COPPER AREA (in2)
FIGURE 23. THERMAL RESISTANCE vs MOUNTING PAD AREA
COPPER BOARD AREA - DESCENDING ORDER
0.020 in2
0.140 in2
0.257 in2
0.380 in2
0.493 in2
80
40
0
10-1
100
101
t, RECTANGULAR PULSE DURATION (s)
FIGURE 24. THERMAL IMPEDANCE vs MOUNTING PAD AREA
8-8
102
103
HUF76105SK8
PSPICE Electrical Model
.SUBCKT HUF76105 2 1 3 ;
REV June 1998
CA 12 8 4.95e-10
CB 15 14 5.15e-10
CIN 6 8 2.9e-10
LDRAIN
DPLCAP
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
DRAIN
2
5
10
RLDRAIN
RSLC1
51
+
RSLC2
EBREAK 11 7 17 18 33.87
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
DBREAK
5
51
ESLC
11
-
RDRAIN
6
8
ESG
EVTHRES
+ 19 8
+
LGATE
IT 8 17 1
GATE
1
LDRAIN 2 5 1e-9
LGATE 1 9 9.2e-10
LSOURCE 3 7 3.2e-10
+
17
EBREAK 18
50
EVTEMP
RGATE +
18 22
9
20
21
DBODY
-
16
MWEAK
6
MMED
MSTRO
RLGATE
LSOURCE
CIN
8
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
SOURCE
3
7
RSOURCE
RLSOURCE
S1A
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 9e-3
RGATE 9 20 3.39
RLDRAIN 2 5 10
RLGATE 1 9 9.2
RLSOURCE 3 7 3.2
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 22e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
12
S2A
13
8
14
13
S1B
17
18
RVTEMP
S2B
13
CA
RBREAK
15
CB
6
8
-
-
IT
14
+
+
EGS
19
VBAT
5
8
EDS
-
+
8
22
RVTHRES
S1A
S1B
S2A
S2B
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*42),6))}
.MODEL DBODYMOD D (IS = 3.01e-13 IKF = 20 RS = 1.47e-2 TRS1 = -1.7e-3 TRS2 = 4e-5 CJO = 5.74e-10 TT = 2.88e-8 M = 0.43)
.MODEL DBREAKMOD D (RS = 3.94e-1 TRS1 = 9.94e-4 TRS2 = 9.12e-7)
.MODEL DPLCAPMOD D (CJO = 2.55e-10 IS = 1e-30 N = 10 M = 0.6)
.MODEL MMEDMOD NMOS (VTO = 1.92 KP = 2.1 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 3.39)
.MODEL MSTROMOD NMOS (VTO = 2.26 KP = 19 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.7 KP = 0.1 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 33.9 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 9.94e-4 TC2 = 9.84e-8)
.MODEL RDRAINMOD RES (TC1 = 8e-3 TC2 = 5.3e-5)
.MODEL RSLCMOD RES (TC1 = 1.0e-3 TC2 = 1e-6)
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 0)
.MODEL RVTHRESMOD RES (TC1 = -1.87e-3 TC2 = -1.2e-6)
.MODEL RVTEMPMOD RES (TC1 = -1.5e-3 TC2 = 1.7e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5
.MODEL S1BMOD VSWITCH (RON = 1e-5
.MODEL S2AMOD VSWITCH (RON = 1e-5
.MODEL S2BMOD VSWITCH (RON = 1e-5
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
VON = -6.2 VOFF= -2)
VON = -2 VOFF= -6.2)
VON = -0.5 VOFF= 0.5)
VON = 0.5 VOFF= -0.5)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
8-9
HUF76105SK8
SABER Electrical Model
REV July 1998
template huf76105 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
d..model dbodymod = (is = 3.01e-13, cjo = 5.74e-10, tt = 2.88e-8, xti = 4.5, m = 0.43)
d..model dbreakmod = ()
d..model dplcapmod = (cjo = 2.55e-10, is = 1e-30, n = 10, m = 0.6)
m..model mmedmod = (type=_n, vto = 1.92, kp = 2.1, is = 1e-30, tox = 1)
DPLCAP
m..model mstrongmod = (type=_n, vto = 2.26, kp = 19, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 1.7, kp = 0.1, is = 1e-30, tox = 1)
10
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -6.2, voff = -2)
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -2, voff = -6.2)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.5, voff = 0.5)
RSLC2
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.5, voff = -0.5)
c.ca n12 n8 = 4.95e-10
c.cb n15 n14 = 5.15e-10
c.cin n6 n8 = 2.9e-10
LDRAIN
RSLC1
51
d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = model=dbreakmod
d.dplcap n10 n5 = model=dplcapmod
i.it n8 n17 = 1
GATE
1
72
EVTHRES
+ 19 8
EVTEMP
RGATE + 18 22
9
20
21
MWEAK
MSTRO
CIN
DBODY
EBREAK
+
17
18
MMED
RLGATE
71
11
16
6
l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 9.2e-10
l.lsource n3 n7 = 3.2e-10
RDBODY
DBREAK
50
RDRAIN
6
8
+
LGATE
RLDRAIN
RDBREAK
ISCL
ESG
DRAIN
2
5
-
8
LSOURCE
7
RSOURCE
RLSOURCE
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
res.rbreak n17 n18 = 1, tc1 = 9.94e-4, tc2 = 9.84e-8
res.rdbody n71 n5 = 1.47e-2, tc1 = -1.7e-3, tc2 = 4e-5
res.rdbreak n72 n5 = 3.94e-1, tc1 = 9.94e-4, tc2 = 9.12e-7
res.rdrain n50 n16 = 9e-3, tc1 = 8e-3, tc2 = 5.3e-5
res.rgate n9 n20 = 3.39
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 9.2
res.rlsource n3 n7 = 3.2
res.rslc1 n5 n51 = 1e-6, tc1 = 1e-3, tc2 = 1e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 22e-3, tc1 = 1e-3, tc2 = 0
res.rvtemp n18 n19 = 1, tc1 = -1.5e-3, tc2 = 1.7e-6
res.rvthres n22 n8 = 1, tc1 = -1.87e-3, tc2 = -1.2e-6
S1A
12
S2A
13
8
S1B
CA
17
18
RVTEMP
S2B
13
CB
6
8
EGS
-
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/42))** 6))
}
}
19
-
IT
14
+
+
spe.ebreak n11 n7 n17 n18 = 33.87
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
8-10
RBREAK
15
14
13
VBAT
5
8
EDS
-
+
8
22
RVTHRES
SOURCE
3
HUF76105SK8
SPICE Thermal Model
REV June 1998
HUF76105SK8
Copper Area = 0.02 in2
CTHERM1 th 8 8.5e-4
CTHERM2 8 7 1.8e-3
CTHERM3 7 6 5.0e-3
CTHERM4 6 5 1.3e-2
CTHERM5 5 4 4.0e-2
CTHERM6 4 3 9.0e-2
CTHERM7 3 2 4.0e-1
CTHERM8 2 tl 1.4
th
JUNCTION
CTHERM1
RTHERM1
8
CTHERM2
RTHERM2
RTHERM1 th 8 3.5e-2
RTHERM2 8 7 6.0e-1
RTHERM3 7 6 2
RTHERM4 6 5 8
RTHERM5 5 4 18
RTHERM6 4 3 39
RTHERM7 3 2 42
RTHERM8 2 tl 48
7
CTHERM3
RTHERM3
6
RTHERM4
SABER Thermal Model
CTHERM4
5
Copper Area = 0.02 in2
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 8 = 8.5e-4
ctherm.ctherm2 8 7 = 1.8e-3
ctherm.ctherm3 7 6 = 5.0e-3
ctherm.ctherm4 6 5 = 1.3e-2
ctherm.ctherm5 5 4 = 4.0e-2
ctherm.ctherm6 4 3 = 9.0e-2
ctherm.ctherm7 3 2 = 4.0e-1
ctherm.ctherm8 2 tl = 1.4
CTHERM5
RTHERM5
4
RTHERM6
CTHERM6
3
RTHERM7
rtherm.rtherm1 th 8 = 3.5e-2
rtherm.rtherm2 8 7 = 6.0e-1
rtherm.rtherm3 7 6 = 2
rtherm.rtherm4 6 5 = 8
rtherm.rtherm5 5 4 = 18
rtherm.rtherm6 4 3 = 39
rtherm.rtherm7 3 2 = 42
rtherm.rtherm8 2 tl = 48
}
CTHERM7
2
RTHERM8
CTHERM8
tl
CASE
TABLE 1. Thermal Models
0.02 in2
0.14 in2
0.257 in2
0.38 in2
0.493 in2
CTHERM6
9.0e-2
1.3e-1
1.5e-1
1.5e-1
1.5e-1
CTHERM7
4.0e-1
6.0e-1
4.5e-1
6.5e-1
7.5e-1
CTHERM8
1.4
2.5
2.2
3
3
RTHERM6
39
26
20
20
20
RTHERM7
42
32
31
29
23
RTHERM8
48
35
38
31
25
COMPONANT
8-11
HUF76105SK8
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (407) 724-7000
FAX: (407) 724-7240
8-12
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
Intersil (Taiwan) Ltd.
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029