HUF76112SK8
Data Sheet
December 2001
7.5A, 30V, 0.026 Ohm, N-Channel, Logic
Level Power MOSFET
The HUF76112SK8 is an Application-Specific MOSFET
optimized for switching when used as the upper switch in
synchronous buck applications. The low gate charge and low
input capacitance results in lower driver and lower switching
losses, thereby increasing the overall system efficiency.
Symbol
Features
• 7.5A, 30V
- rDS(ON) = 0.026Ω, VGS = 10V
- rDS(ON) = 0.033Ω, VGS = 5V
SOURCE (1)
DRAIN (8)
• PWM Optimized for Synchronous Buck Applications
SOURCE (2)
DRAIN (7)
• Fast Switching
SOURCE (3)
DRAIN (6)
GATE (4)
DRAIN (5)
• Low Gate Charge
- Qg Total 15nC (Typ)
• Low Capacitance
- CISS 725pF (Typ)
- CRSS 36pF (Typ)
Packaging
SO8 (JEDEC MS-012AA)
BRANDING DASH
Ordering Information
PART NUMBER
5
1
HUF76112SK8
2
3
PACKAGE
MS-012AA
BRAND
76112SK8
NOTE: When ordering, use the entire part number. Add the suffix T
to obtain the HUF76112SK8 in tape and reel, e.g., HUF76112SK8T.
4
Absolute Maximum Ratings
TA = 25oC, Unless Otherwise Specified
SYMBOL
PARAMETER
HUF76112SK8
UNITS
VDSS
Drain to Source Voltage (Note 1)
30
V
VDGR
Drain to Gate Voltage (RGS = 20kΩ) (Note 1)
30
V
Gate to Source Voltage
±16
V
7.5
4.0
Figure 4
A
A
A
2.5
20
W
mW/oC
-55 to 150
oC
300
260
oC
oC
Measured using FR-4 board with 0.76 in 2 (490.3 mm2) copper pad at 10
second.
50
oC/W
Measured using FR-4 board with 0.054 in 2 (34.8 mm2) copper pad at 1000
seconds. (Figure 23)
152
oC/W
Measured using FR-4 board with 0.0115 in2 (7.42 mm2) copper pad at 1000
seconds. (Figure 23)
189
oC/W
VGS
ID
ID
IDM
PD
TJ, TSTG
TL
Tpkg
Drain Current
Continuous (TA = 25oC, VGS = 10V) (Figure 2) (Note 2)
Continuous (TA = 100oC, VGS = 5V) (Note 2)
Pulsed Drain Current
Power Dissipation (Note 2)
Derate Above 25oC
Operating and Storage Temperature
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s
Package Body for 10s, See Techbrief TB334
THERMAL SPECIFICATIONS
RθJA
Thermal Resistance Junction to Ambient
NOTES:
1. TJ = 25oC to 125oC.
2. RθJA = 50 oC/W
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
©2001 Fairchild Semiconductor Corporation
HUF76112SK8 Rev. B
HUF76112SK8
Electrical Specifications
TA = 25oC, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
BVDSS
Zero Gate Voltage Drain Current
IDSS
Gate to Source Leakage Current
IGSS
ID = 250µA, VGS = 0V (Figure 12)
30
-
-
V
VDS = 25V, VGS = 0V
-
-
1
µA
VDS = 25V, VGS = 0V, TA = 150oC
-
-
250
µA
VGS = ±16V
-
-
±100
nA
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250µA (Figure 11)
1
-
3
V
Drain to Source On Resistance
rDS(ON)
ID = 7.5A, V GS = 10V (Figures 9, 10)
-
0.022
0.026
Ω
ID = 4.0A, V GS = 5V (Figure 9)
-
0.027
0.033
Ω
VDD = 15V, ID = 4.0A
VGS = 5V,
RGS = 20Ω
(Figures 15, 21, 22)
-
-
77
ns
-
11
-
ns
-
40
-
ns
td(OFF)
-
35
-
ns
tf
-
32
-
ns
tOFF
-
-
100
ns
-
-
75
ns
-
7.2
-
ns
-
43
-
ns
td(OFF)
-
52
-
ns
tf
-
45
-
ns
tOFF
-
-
145
ns
-
15
18
nC
-
7.2
8.7
nC
-
0.74
0.9
nC
SWITCHING SPECIFICATIONS (VGS = 5V)
Turn-On Time
Turn-On Delay Time
tON
td(ON)
Rise Time
tr
Turn-Off Delay Time
Fall Time
Turn-Off Time
SWITCHING SPECIFICATIONS (VGS = 10V)
Turn-On Time
Turn-On Delay Time
Rise Time
tON
td(ON)
tr
Turn-Off Delay Time
Fall Time
Turn-Off Time
VDD = 15V, ID = 7.5A
VGS = 10V,
RGS = 20Ω
(Figures 16, 21, 22)
GATE CHARGE SPECIFICATIONS
Total Gate Charge at 10V
Qg(TOT)
VGS = 0V to 10V
Total Gate Charge at 5V
Qg(TOT)
VGS = 0V to 5V
Threshold Gate Charge
Qg(TH)
VGS = 0V to 1V
VDD = 15V,
ID = 7.5A,
Ig(REF) = 1.0mA
(Figures 14, 19, 20)
Gate to Source Gate Charge
Qgs
-
2.1
-
nC
Gate to Drain “Miller” Charge
Qgd
-
2.9
-
nC
-
725
-
pF
-
325
-
pF
-
36
-
pF
MIN
TYP
MAX
UNITS
ISD = 7.5A
-
-
1.25
V
CAPACITANCE SPECIFICATIONS
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
VDS = 25V, VGS = 0V,
f = 1MHz
(Figures 13)
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage
Reverse Recovery Time
Reverse Recovered Charge
©2001 Fairchild Semiconductor Corporation
SYMBOL
VSD
TEST CONDITIONS
ISD = 4A
-
-
1.00
V
trr
ISD = 7.5A, dISD/dt = 100A/µs
-
-
25
ns
QRR
ISD = 7.5A, dISD/dt = 100A/µs
-
-
14
nC
HUF76112SK8 Rev. B
HUF76112SK8
Typical Performance Curves
8
1.0
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
1.2
0.8
0.6
0.4
VGS = 10V, RθJA = 50oC/W
6
4
VGS = 5V, RθJA = 189oC/W
2
0.2
0
0
0
25
50
75
125
100
150
50
25
TA , AMBIENT TEMPERATURE (oC)
75
100
125
150
TA, AMBIENT TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
AMBIENT TEMPERATURE
3
ZθJA, NORMALIZED
THERMAL IMPEDANCE
1
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
RθJA = 50oC/W
0.1
PDM
t1
0.01
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
SINGLE PULSE
0.001
10-5
10-4
10-3
10-2
10-1
100
101
102
103
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
IDM, PEAK CURRENT (A)
1000
RθJA = 50oC/W
TA = 25oC
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
100
VGS = 5V
I = I25
150 - TA
125
VGS = 10V
10
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
1
10-5
10-4
10-3
10-2
10-1
100
101
102
103
t, PULSE WIDTH (s)
FIGURE 4. PEAK CURRENT CAPABILITY
©2001 Fairchild Semiconductor Corporation
HUF76112SK8 Rev. B
HUF76112SK8
Typical Performance Curves
(Continued)
500
200
SINGLE PULSE
TJ = MAX RATED
TA = 25oC
100
IAS , AVALANCHE CURRENT (A)
ID, DRAIN CURRENT (A)
RθJA = 50oC/W
100µs
10
1ms
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
10ms
1
10
1
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
100
STARTING TJ = 25oC
10
STARTING TJ = 150oC
1
0.01
100
0.1
VDS , DRAIN TO SOURCE VOLTAGE (V)
10
1
100
tAV, TIME IN AVALANCHE (ms)
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
25
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
20
VGS =
10V
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
25
15
10
TJ = 25oC
TJ = 150oC
5
VGS = 4.5V
15
VGS = 4V
VGS = 3.5V
10
VGS = 3V
5
TJ = -55oC
0
TA = 25oC
0
1.5
2.5
2.0
3.0
3.5
0
4.0
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
0.5
VGS , GATE TO SOURCE VOLTAGE (V)
1.5
1.0
2.0
VDS , DRAIN TO SOURCE VOLTAGE (V)
FIGURE 7. TRANSFER CHARACTERISTICS
FIGURE 8. SATURATION CHARACTERISTICS
50
40
ID = 7.5A
30
ID = 1A
20
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
1.6
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
rDS(ON), DRAIN TO SOURCE
ON RESISTANCE (mΩ)
VGS = 5V
20
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = 10V, ID = 7.5A
1.3
1.0
0.7
10
2
4
6
8
VGS , GATE TO SOURCE VOLTAGE (V)
10
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
©2001 Fairchild Semiconductor Corporation
-80
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 10. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
HUF76112SK8 Rev. B
HUF76112SK8
Typical Performance Curves
(Continued)
1.2
1.2
1.0
0.8
0.6
-80
-40
0
40
80
120
ID = 250µA
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
NORMALIZED GATE
THRESHOLD VOLTAGE
VGS = VDS, ID = 250µA
1.1
1.0
0.9
-80
160
-40
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
40
80
120
160
FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
10
VGS , GATE TO SOURCE VOLTAGE (V)
2000
CISS = CGS + CGD
1000
C, CAPACITANCE (pF)
0
TJ , JUNCTION TEMPERATURE (oC)
COSS ≅ C DS + CGD
100
CRSS = CGD
VGS = 0V, f = 1MHz
8
6
4
WAVEFORMS IN
DESCENDING ORDER:
ID = 7.5A
ID = 1A
2
0
20
0.1
VDD = 15V
1.0
10
0
30
3
6
9
12
15
Qg , GATE CHARGE (nC)
VDS , DRAIN TO SOURCE VOLTAGE (V)
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
80
FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
120
td(OFF)
VGS = 5V, VDD = 15V, ID = 4.0A
VGS = 10V, V DD = 15V, ID = 7.5A
60
SWITCHING TIME (ns)
SWITCHING TIME (ns)
100
tf
40
tr
20
td(ON)
td(OFF)
80
tf
60
tr
40
20
0
td(ON)
0
0
10
20
30
40
RGS, GATE TO SOURCE RESISTANCE (Ω)
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
©2001 Fairchild Semiconductor Corporation
50
0
10
20
30
40
50
RGS , GATE TO SOURCE RESISTANCE (Ω)
FIGURE 16. SWITCHING TIME vs GATE RESISTANCE
HUF76112SK8 Rev. B
HUF76112SK8
Test Circuits and Waveforms
VDS
BVDSS
L
tP
VARY tP TO OBTAIN
REQUIRED PEAK IAS
RG
-
VGS
VDS
IAS
+
VDD
VDD
DUT
tP
0V
IAS
0
0.01Ω
tAV
FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 18. UNCLAMPED ENERGY WAVEFORMS
VDS
VDD
RL
Qg(TOT)
VDS
VGS = 10V
VGS
Qg(TOT)
+
VDD
VGS = 5V
VGS
DUT
VGS = 1V
Ig(REF)
0
Qg(TH)
Qgs
Qgd
Ig(REF)
0
FIGURE 19. GATE CHARGE TEST CIRCUIT
FIGURE 20. GATE CHARGE WAVEFORMS
VDS
tON
tOFF
td(ON)
td(OFF)
tr
RL
VDS
tf
90%
90%
+
VGS
-
VDD
10%
0
10%
DUT
90%
RGS
VGS
VGS
0
FIGURE 21. SWITCHING TIME TEST CIRCUIT
©2001 Fairchild Semiconductor Corporation
10%
50%
50%
PULSE WIDTH
FIGURE 22. SWITCHING TIME WAVEFORM
HUF76112SK8 Rev. B
HUF76112SK8
The maximum rated junction temperature, TJM , and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, PDM , in an
application. Therefore the application’s ambient temperature,
TA (oC), and thermal resistance RθJA (oC/W) must be
reviewed to ensure that TJM is never exceeded. Equation 1
mathematically represents the relationship and serves as
the basis for establishing the rating of the part.
P
( T JM – TA )
= ------------------------------DM
Z
θJA
(EQ. 1)
In using surface mount devices such as the SO8 package,
the environment in which it is applied will have a significant
influence on the part’s current and maximum power
dissipation ratings. Precise determination of PDM is complex
and influenced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Fairchild provides thermal information to assist the designer’s
preliminary application evaluation. Figure 23 defines the RθJA
for the device as a function of the top copper (component side)
area. This is for a horizontally positioned FR-4 board with 1oz
copper after 1000 seconds of steady state power with no air
flow. This graph provides the necessary information for
calculation of the steady state junction temperature or power
dissipation. Pulse applications can be evaluated using the
Fairchild device Spice thermal model or manually utilizing the
normalized maximum transient thermal impedance curve.
Displayed on the curve are RθJA values listed in the Electrical
Specifications table. The points were chosen to depict the
compromise between the copper board area, the thermal
resistance and ultimately the power dissipation, PDM .
Thermal resistances corresponding to other copper areas can
be obtained from Figure 23 or by calculation using Equation 2.
RθJA is defined as the natural log of the area times a coefficient
added to a constant. The area, in square inches is the top
copper area including the gate and source pads.
R θJA = 83.2 – 23.6 ×
ln ( Area )
(EQ. 2)
The transient thermal impedance (ZθJA) is also effected by
varied top copper board area. Figure 24 shows the effect of
copper pad area on single pulse transient thermal
impedance. Each trace represents a copper pad area in
square inches corresponding to the descending list in the
graph. Spice and SABER thermal models are provided for
each of the listed pad areas.
Copper pad area has no perceivable effect on transient
thermal impedance for pulse widths less than 100ms. For
pulse widths less than 100ms the transient thermal
impedance is determined by the die and package. Therefore,
CTHERM1 through CTHERM5 and RTHERM1 through
RTHERM5 remain constant for each of the thermal models. A
listing of the model component values is available in Table 1.
240
RθJA = 83.2 - 23.6*ln(AREA)
200
RθJA (oC/W)
Thermal Resistance vs Mounting Pad Area
189oC/W - 0.0115in2
152oC/W - 0.054in2
160
120
80
0.01
0.1
1.0
AREA, TOP COPPER AREA (in2)
FIGURE 23. THERMAL RESISTANCE vs MOUNTING PAD AREA
150
COPPER BOARD AREA - DESCENDING ORDER
ZθJA, THERMAL
IMPEDANCE (oC/W)
120
90
0.04 in2
0.28 in2
0.52 in2
0.76 in2
1.00 in2
60
30
0
10-1
100
101
102
103
t, RECTANGULAR PULSE DURATION (s)
FIGURE 24. THERMAL IMPEDANCE vs MOUNTING PAD AREA
©2001 Fairchild Semiconductor Corporation
HUF76112SK8 Rev. B
HUF76112SK8
PSPICE Electrical Model
.SUBCKT HUF76112SK8 2 1 3 ;
REV 9 Mar 2000
CA 12 8 8.00e-10
CB 15 14 7.40e-10
CIN 6 8 6.90e-10
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
LDRAIN
DPLCAP
DRAIN
2
5
10
5
51
ESLC
11
-
RDRAIN
6
8
EVTHRES
+ 19 8
+
LGATE
GATE
1
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
+
50
ESG
EVTEMP
RGATE +
18 22
9
20
21
EBREAK
17
18
DBODY
-
16
MWEAK
6
MMED
MSTRO
RLGATE
LSOURCE
CIN
8
SOURCE
3
7
RSOURCE
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 5.00e-3
RGATE 9 20 2.82
RLDRAIN 2 5 10
RLGATE 1 9 9 11.2
RLSOURCE 3 7 1.29
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 10.00e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A
S1B
S2A
S2B
DBREAK
+
RSLC2
IT 8 17 1
LDRAIN 2 5 1.00e-9
LGATE 1 9 1.12e-9
LSOURCE 3 7 1.29e-10
RLDRAIN
RSLC1
51
EBREAK 11 7 17 18 31.89
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
RLSOURCE
S1A
12
S2A
S1B
CA
17
18
RVTEMP
S2B
13
CB
6
8
EGS
19
VBAT
5
8
EDS
-
-
IT
14
+
+
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
RBREAK
15
14
13
13
8
-
+
8
22
RVTHRES
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*215),2))}
.MODEL DBODYMOD D (IS = 7.75e-13 RS = 8.08e-3 TRS1 = -1.89e-4 TRS2 = 0 CJO = 1.17e-9 TT = 1.41e-8 M = 0.43)
.MODEL DBREAKMOD D (RS = 1.34e- 1TRS1 = 0TRS2 = 0)
..MODEL DPLCAPMOD D (CJO = 3.72e-10 IS = 1e-30 M = 0.72)
.MODEL MMEDMOD NMOS (VTO = 1.90 KP = 1.75 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 2.82)
.MODEL MSTROMOD NMOS (VTO = 2.25 KP = 43 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.70 KP = 0.10 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 28.2 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 9.15e- 4TC2 = -2.97e-7)
.MODEL RDRAINMOD RES (TC1 = 7.40e-3 TC2 = 2.00e-5)
.MODEL RSLCMOD RES (TC1 = 4.93e-3 TC2 = 1.01e-6)
.MODEL RSOURCEMOD RES (TC1 = 1.00e-3 TC2 = 0)
.MODEL RVTHRESMOD RES (TC1 = -1.85e-3 TC2 = -5.28e-6)
.MODEL RVTEMPMOD RES (TC1 = -1.55e- 3TC2 = 0)
.MODEL S1AMOD VSWITCH (RON = 1e-5
.MODEL S1BMOD VSWITCH (RON = 1e-5
.MODEL S2AMOD VSWITCH (RON = 1e-5
.MODEL S2BMOD VSWITCH (RON = 1e-5
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
VON = -6.50 VOFF= -2.50)
VON = -2.50 VOFF= -6.50)
VON = -2.20 VOFF= 0)
VON = 0 VOFF= -2.20)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
©2001 Fairchild Semiconductor Corporation
HUF76112SK8 Rev. B
HUF76112SK8
SABER Electrical Model
REV 9 Mar 2000
template huf76112SK8 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (is = 7.75e-13,rs=8.08e-3,trs1=-1.89e-4,trs2=0, cjo = 1.17e-9, tt = 1.41e-8, m = 0.43)
dp..model dbreakmod = (rs=1.34e-1,trs1=0,trs2=0)
dp..model dplcapmod = (cjo = 3.72e-10, is = 1e-30, m = 0.72)
m..model mmedmod = (type=_n, vto = 1.90, kp = 1.75, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 2.25, kp = 43, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 1.70, kp = 0.10, is = 1e-30, tox = 1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -6.5, voff = -2.5)
DPLCAP 5
sw_vcsp..model s1bmod = (ron = 1e-5, roff = 0.1, von = -2.5, voff = -6.5)
10
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -2.2, voff = 0)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0, voff = -2.2)
DRAIN
2
RLDRAIN
RSLC1
51
c.ca n12 n8 = 8.00e-10
c.cb n15 n14 = 7.40e-10
c.cin n6 n8 = 6.90e-10
RSLC2
ISCL
i.it n8 n17 = 1
RDRAIN
6
8
ESG
EVTHRES
+ 19 8
+
LGATE
GATE
1
EVTEMP
RGATE + 18 22
9
20
DBREAK
50
-
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
l.ldrain n2 n5 = 1.00e-9
l.lgate n1 n9 = 1.12e-9
l.lsource n3 n7 = 1.29e-10
LDRAIN
21
11
16
MWEAK
6
MSTRO
RLGATE
CIN
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
DBODY
EBREAK
+
17
18
MMED
-
8
LSOURCE
7
SOURCE
3
RSOURCE
RLSOURCE
S1A
S2A
res.rbreak n17 n18 = 1, tc1 = 9.15e-4, tc2 = -2.97e-7
12
15
14
13
res.rdrain n50 n16 = 5.00e-3, tc1 = 7.40e-3, tc2 = 2.00e-5
13
8
res.rgate n9 n20 = 2.82
res.rldrain n2 n5 = 10
S1B
S2B
res.rlgate n1 n9 = 11.2
13
CB
CA
res.rlsource n3 n7 = 1.29
+ 14
+
res.rslc1 n5 n51 = 1e-6, tc1 = 4.93e-3, tc2 = 1.01e-6
6
5
res.rslc2 n5 n50 = 1e3
EGS 8
EDS 8
res.rsource n8 n7 = 10.00e-3, tc1 = 1.00e-3, tc2 = 0
res.rvtemp n18 n19 = 1, tc1 = -1.55e-3, tc2 = 0
res.rvthres n22 n8 = 1, tc1 = -1.85e-3, tc2 = -5.28e-6
RBREAK
17
18
RVTEMP
19
-
IT
VBAT
+
8
22
RVTHRES
spe.ebreak n11 n7 n17 n18 = 31.89
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/215))** 2))
}
}
©2001 Fairchild Semiconductor Corporation
HUF76112SK8 Rev. B
HUF76112SK8
SPICE Thermal Model
REV 11 Nov 1999
ITF86130SK8T
Copper Area = 0.04 in2
JUNCTION
th
CTHERM1 th 8 2.0e-3
CTHERM2 8 7 5.0e-3
CTHERM3 7 6 1.0e-2
CTHERM4 6 5 4.0e-2
CTHERM5 5 4 9.0e-2
CTHERM6 4 3 1.2e-1
CTHERM7 3 2 0.5
CTHERM8 2 tl 1.3
RTHERM1
CTHERM1
8
RTHERM2
RTHERM1 th 8 0.1
RTHERM2 8 7 0.5
RTHERM3 7 6 1.0
RTHERM4 6 5 5.0
RTHERM5 5 4 8.0
RTHERM6 4 3 26
RTHERM7 3 2 39
RTHERM8 2 tl 55
CTHERM2
7
RTHERM3
CTHERM3
6
RTHERM4
SABER Thermal Model
Copper Area = 0.04 in2
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 8 = 2.0e-3
ctherm.ctherm2 8 7 = 5.0e-3
ctherm.ctherm3 7 6 = 1.0e-2
ctherm.ctherm4 6 5 = 4.0e-2
ctherm.ctherm5 5 4 = 9.0e-2
ctherm.ctherm6 4 3 = 1.2e-1
ctherm.ctherm7 3 2 = 0.5
ctherm.ctherm8 2 tl = 1.3
CTHERM4
5
RTHERM5
CTHERM5
4
RTHERM6
CTHERM6
3
CTHERM7
RTHERM7
rtherm.rtherm1 th 8 = 0.1
rtherm.rtherm2 8 7 = 0.5
rtherm.rtherm3 7 6 = 1.0
rtherm.rtherm4 6 5 = 5.0
rtherm.rtherm5 5 4 = 8.0
rtherm.rtherm6 4 3 = 26
rtherm.rtherm7 3 2 = 39
rtherm.rtherm8 2 tl = 55
}
2
CTHERM8
RTHERM8
CASE
tl
TABLE 1. THERMAL MODELS
0.04in2
0.28in2
0.52in2
0.76in2
1.0in2
CTHERM6
1.2e-1
1.5e-1
2.0e-1
2.0e-1
2.0e-1
CTHERM7
0.5
1.0
1.0
1.0
1.0
CTHERM8
1.3
2.8
3.0
3.0
3.0
RTHERM6
26
20
15
13
12
RTHERM7
39
24
21
19
18
RTHERM8
55
38.7
31.3
29.7
25
COMPONENT
©2001 Fairchild Semiconductor Corporation
HUF76112SK8 Rev. B
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
ACEx™
Bottomless™
CoolFET™
CROSSVOLT™
DenseTrench™
DOME™
EcoSPARK™
E2CMOSTM
EnSignaTM
FACT™
FACT Quiet Series™
FAST
FASTr™
FRFET™
GlobalOptoisolator™
GTO™
HiSeC™
ISOPLANAR™
LittleFET™
MicroFET™
MicroPak™
MICROWIRE™
OPTOLOGIC™
OPTOPLANAR™
PACMAN™
POP™
Power247™
PowerTrench
QFET™
QS™
QT Optoelectronics™
Quiet Series™
SILENT SWITCHER
SMART START™
STAR*POWER™
Stealth™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
TinyLogic™
TruTranslation™
UHC™
UltraFET
VCX™
STAR*POWER is used under license
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
2. A critical component is any component of a life
systems which, (a) are intended for surgical implant into
support device or system whose failure to perform can
the body, or (b) support or sustain life, or (c) whose
be reasonably expected to cause the failure of the life
failure to perform when properly used in accordance
support device or system, or to affect its safety or
with instructions for use provided in the labeling, can be
effectiveness.
reasonably expected to result in significant injury to the
user.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Obsolete
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. H4