HUF76121SK8
Data Sheet
April 1999
8A, 30V, 0.023 Ohm, N-Channel, Logic
Level UltraFET Power MOSFET
Features
• Logic Level Gate Drive
This N-Channel power MOSFET is
manufactured using the innovative
UltraFET™ process. This advanced
process technology achieves the
lowest possible on-resistance per silicon area, resulting in
outstanding performance. This device is capable of
withstanding high energy in the avalanche mode and the
diode exhibits very low reverse recovery time and stored
charge. It was designed for use in applications where power
efficiency is important, such as switching regulators, switching
converters, motor drivers, relay drivers, low-voltage bus
switches, and power management in portable and batteryoperated products.
• 8A, 30V
• Simulation Models
- Temperature Compensated PSPICE™ and SABER©
Electrical Models
- Spice and SABER© Thermal Impedance Models
- www.Intersil.com
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Transient Thermal Impedance Curve vs Board Mounting
Area
• Related Literature
- TB370, “Guidelines for Soldering Surface Mount
Components to PC Boards”
Formerly developmental type TA76121.
Ordering Information
PART NUMBER
HUF76121SK8
PACKAGE
MS-012AA
File Number 4737
Symbol
BRAND
76121SK8
NOTE: When ordering, use the entire part number. Add the suffix T
to obtain the variant in tape and reel, e.g., HUF76121SK8T.
NC (1)
DRAIN(8)
SOURCE(2)
DRAIN(7)
SOURCE(3)
DRAIN(6)
GATE(4)
DRAIN(5)
Packaging
JEDEC MS-012AA
BRANDING DASH
5
1
2
3
1
4
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
UltraFET™ is a trademark of Intersil Corporation. PSPICE™ is a trademark of MicroSim Corporation.
SABER© is a Copyright of Analogy Inc. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
HUF76121SK8
Absolute Maximum Ratings
TA = 25oC, Unless Otherwise Specified
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
Drain Current
Continuous (TA= 25oC, VGS = 10V) (Figure 2) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TA= 100oC, VGS = 5V) (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TA= 100oC, VGS = 4.5V) (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS
Power Dissipation (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
UNITS
V
V
V
30
30
±16
8
2.5
2.3
Figure 4
Figures 6, 17, 18
2.5
20
-55 to 150
A
A
A
W
mW/oC
oC
300
260
oC
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. TJ = 25oC to 125oC.
2. 50oC/W measured using FR-4 board with 0.76 in2 footprint at 10 seconds.
3. 189oC/W measured using FR-4 board with 0.0115 in2 footprint at 1000 seconds.
TA = 25oC, Unless Otherwise Specified
Electrical Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
30
-
-
V
VDS = 25V, VGS = 0V
-
-
1
µA
VDS = 25V, VGS = 0V, TC = 150oC
-
-
250
µA
VGS = ±16V
-
-
±100
nA
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
BVDSS
IDSS
Gate to Source Leakage Current
IGSS
ID = 250µA, VGS = 0V (Figure 12)
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250µA (Figure 11)
1
-
3
V
Drain to Source On Resistance
rDS(ON)
ID = 8A, VGS = 10V (Figures 9, 10)
-
0.018
0.023
Ω
ID = 2.5A, VGS = 5V (Figure 9)
-
0.021
0.028
Ω
ID = 2.3A, VGS = 4.5V (Figure 9)
-
0.022
0.031
Ω
Pad Area = 0.76 in2 (Note 2)
-
-
50
oC/W
Pad Area = 0.054 in2 (Figure 23)
-
-
152
oC/W
Pad Area = 0.0115 in2 (Figure 23)
-
-
189
oC/W
VDD = 15V, ID ≅ 2.3A, RL = 6.5Ω,
VGS = 4.5V, RGS = 10Ω
(Figures 15, 21, 22)
-
-
85
ns
-
17
-
ns
tr
-
40
-
ns
td(OFF)
-
40
-
ns
tf
-
30
-
ns
tOFF
-
-
105
ns
THERMAL SPECIFICATIONS
Thermal Resistance Junction to Ambient
RθJA
SWITCHING SPECIFICATIONS (VGS = 4.5V)
Turn-On Time
tON
Turn-On Delay Time
td(ON)
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
2
HUF76121SK8
TA = 25oC, Unless Otherwise Specified
Electrical Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
tON
VDD = 15V, ID ≅ 8A, RL =1.9Ω, VGS = 10V,
RGS = 12Ω
(Figures 16, 21, 22)
-
-
60
ns
-
10
-
ns
tr
-
29
-
ns
td(OFF)
-
64
-
ns
tf
-
40
-
ns
tOFF
-
-
155
ns
-
24
29
nC
-
14
17
nC
-
0.8
1.0
nC
SWITCHING SPECIFICATIONS (VGS = 10V)
Turn-On Time
Turn-On Delay Time
td(ON)
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
GATE CHARGE SPECIFICATIONS
Total Gate Charge
Qg(TOT)
VGS = 0V to 10V
Gate Charge at 5V
Qg(5)
VGS = 0V to 5V
Qg(TH)
VGS = 0V to 1V
Threshold Gate Charge
VDD = 15V, ID ≅ 2.5A,
RL = 6.0Ω
Ig(REF) = 1.0mA
(Figures 14, 19, 20)
Gate to Source Gate Charge
Qgs
-
1.9
-
nC
Reverse Transfer Capacitance
Qgd
-
7
-
nC
-
850
-
pF
-
465
-
pF
-
100
-
pF
MIN
TYP
MAX
UNITS
-
-
1.25
V
1.10
V
CAPACITANCE SPECIFICATIONS
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
VDS = 25V, VGS = 0V,
f = 1MHz
(Figure 13)
Source to Drain Diode Specifications
PARAMETER
SYMBOL
Source to Drain Diode Voltage
VSD
TEST CONDITIONS
ISD = 8A
ISD = 2.5A
Reverse Recovery Time
Reverse Recovered Charge
trr
ISD = 2.5A, dISD/dt = 100A/µs
-
-
65
ns
QRR
ISD = 2.5A, dISD/dt = 100A/µs
-
-
100
nC
Typical Performance Curves
10
1.0
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
1.2
0.8
0.6
0.4
8
VGS = 10V, RθJA = 50oC/W
6
4
2
0.2
VGS = 4.5V, RθJA = 189oC/W
0
0
0
25
50
75
100
125
150
TA , AMBIENT TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT
TEMPERATURE
3
25
50
75
100
125
150
TA, AMBIENT TEMPERATURE (oC)
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
AMBIENT TEMPERATURE
HUF76121SK8
Typical Performance Curves
ZθJA, NORMALIZED
THERMAL IMPEDANCE
10
1
(Continued)
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
RθJA = 50oC/W
PDM
0.1
t1
t2
0.01
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
SINGLE PULSE
0.001
10-5
10-4
10-3
10-2
10-1
100
101
102
103
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
IDM, PEAK CURRENT (A)
1000
RθJA = 50oC/W
TC = 25oC
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
VGS = 10V
I = I25
100
150 - TA
125
VGS = 5V
10
5
10-5
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
10-4
10-3
10-2
10-1
t, PULSE WIDTH (s)
100
101
102
103
FIGURE 4. PEAK CURRENT CAPABILITY
ID, DRAIN CURRENT (A)
TJ = MAX RATED
TA = 25oC
100
100µs
1ms
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
10
10ms
1
BVDSS MAX = 30V
1
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
100
IAS, AVALANCHE CURRENT (A)
100
500
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
STARTING TJ = 25oC
10
STARTING TJ = 150oC
1
0.01
0.1
1
10
100
tAV, TIME IN AVALANCHE (ms)
NOTE: Refer to Intersil Application Notes AN9321 and AN9322.
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
4
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
HUF76121SK8
Typical Performance Curves
(Continued)
40
40
VGS = 10V
VGS = 5V
VGS = 4V
VDD = 15V
30
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
PULSE DURATION = 250µs
DUTY CYCLE = 0.5% MAX
20
10
150oC
25oC
30
VGS = 3.5V
20
VGS = 3V
10
TA = 25oC
-55oC
0
0
0
1
2
3
4
0
1
VGS, GATE TO SOURCE VOLTAGE (V)
1.6
PULSE DURATION = 250µs
DUTY CYCLE = 0.5% MAX
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
rDS(ON), DRAIN TO SOURCE
ON RESISTANCE (mΩ)
3
4
FIGURE 8. SATURATION CHARACTERISTICS
40
ID = 8A
2
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 7. TRANSFER CHARACTERISTICS
35
30
ID = 2.3A
25
20
PULSE DURATION = 250µs
DUTY CYCLE = 0.5% MAX
VGS = 10V, ID = 8A
1.4
1.2
1.0
0.8
0.6
15
2
4
6
8
-80
10
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
0
40
80
120
160
FIGURE 10. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
1.2
1.0
0.8
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
5
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
1.2
VGS = VDS, ID = 250µA
0.6
-80
-40
TJ, JUNCTION TEMPERATURE (oC)
VGS, GATE TO SOURCE VOLTAGE (V)
NORMALIZED GATE
THRESHOLD VOLTAGE
PULSE DURATION = 250µs
DUTY CYCLE = 0.5% MAX
ID = 250µA
1.1
1.0
0.9
-80
-40
0
40
80
120
160
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
HUF76121SK8
Typical Performance Curves
(Continued)
1200
VGS , GATE TO SOURCE VOLTAGE (V)
10
C, CAPACITANCE (pF)
VGS = 0V, f = 1MHz
CISS
900
600
COSS
300
CRSS
0
VDD = 15V
8
6
4
WAVEFORMS IN
DESCENDING ORDER:
ID = 8A
ID = 2.5A
2
0
0
5
10
15
20
25
30
5
0
VDS , DRAIN TO SOURCE VOLTAGE (V)
10
15
20
25
Qg, GATE CHARGE (nC)
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
200
150
VGS = 10V, VDD = 15V, ID = 8A, RL= 1.9Ω
VGS = 4.5V, VDD = 15V, ID = 2.3A, RL= 6.5Ω
tr
td(OFF)
SWITCHING TIME (ns)
SWITCHING TIME (ns)
125
100
tf
75
50
td(ON)
160
td(OFF)
120
tf
80
tr
40
25
td(ON)
0
0
0
10
20
30
40
RGS, GATE TO SOURCE RESISTANCE (Ω)
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
6
50
0
10
20
30
40
RGS, GATE TO SOURCE RESISTANCE (Ω)
FIGURE 16. SWITCHING TIME vs GATE RESISTANCE
50
HUF76121SK8
Test Circuits and Waveforms
VDS
BVDSS
L
tP
VARY tP TO OBTAIN
REQUIRED PEAK IAS
+
RG
VDS
IAS
VDD
VDD
-
VGS
DUT
tP
0V
IAS
0
0.01Ω
tAV
FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT
VDS
FIGURE 18. UNCLAMPED ENERGY WAVEFORMS
VDD
RL
Qg(TOT)
VDS
VGS = 10V
VGS
Qg(5)
+
VDD
VGS = 5V
VGS
-
VGS = 1V
DUT
0
Ig(REF)
Qg(TH)
Qgs
Qgd
Ig(REF)
0
FIGURE 19. GATE CHARGE TEST CIRCUIT
FIGURE 20. GATE CHARGE WAVEFORMS
VDS
tON
tOFF
td(ON)
td(OFF)
tf
tr
RL
VDS
90%
90%
+
VGS
-
VDD
10%
10%
0
DUT
90%
RGS
VGS
VGS
0
FIGURE 21. SWITCHING TIME TEST CIRCUIT
7
10%
50%
50%
PULSE WIDTH
FIGURE 22. SWITCHING TIME WAVEFORM
HUF76121SK8
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM, and the thermal resistance of the heat dissipating path determines the
maximum allowable device power dissipation, PDM, in an
application. Therefore the application’s ambient temperature, TA (oC), and thermal resistance RθJA (oC/W) must be
reviewed to ensure that TJM is never exceeded. Equation 1
mathematically represents the relationship and serves as
the basis for establishing the rating of the part.
( T JM – T A )
P DM = ------------------------------Z θJA
(EQ. 1)
In using surface mount devices such as the SOP-8 package,
the environment in which it is applied will have a significant
influence on the part’s current and maximum power
dissipation ratings. Precise determination of PDM is complex
and influenced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
Thermal resistances corresponding to other copper areas can
be obtained from Figure 23 or by calculation using Equation 2.
RθJA is defined as the natural log of the area times a cofficient
added to a constant. The area, in square inches is the top
copper area including the gate and source pads.
R θJA = 83.2 – 23.6 ×
ln ( Area )
(EQ. 2)
The transient thermal impedance (ZθJA) is also effected by
varied top copper board area. Figure 24 shows the effect of
copper pad area on single pulse transient thermal
impedance. Each trace represents a copper pad area in
square inches corresponding to the descending list in the
graph. Spice and SABER thermal models are provided for
each of the listed pad areas.
Copper pad area has no perceivable effect on transient thermal impedance for pulse widths less than 100ms. For pulse
widths less than 100ms the transient thermal impedance is
determined by the die and package. Therefore, CTHERM1
through CTHERM5 and RTHERM1 through RTHERM5
remain constant for each of the thermal models. A listing of
the model component values is available in Table 1.
3. The use of external heat sinks.
240
4. The use of thermal vias.
RθJA = 83.2 - 23.6*ln(AREA)
5. Air flow and board orientation.
Intersil provides thermal information to assist the designer’s
preliminary application evaluation. Figure 23 defines the
RθJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4
board with 1oz copper after 1000 seconds of steady state
power with no air flow. This graph provides the necessary
information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be
evaluated using the Intersil device Spice thermal model or
manually utilizing the normalized maximum transient thermal
impedance curve.
200
RθJA (oC/W)
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
189oC/W - 0.0115in2
152oC/W - 0.054in2
160
120
80
0.01
0.1
1.0
AREA, TOP COPPER AREA (in2)
FIGURE 23. THERMAL RESISTANCE vs MOUNTING PAD AREA
150
ZθJA, THERMAL
IMPEDANCE (oC/W)
120
90
COPPER BOARD AREA - DESCENDING ORDER
0.04 in2
0.28 in2
0.52 in2
0.76 in2
1.00 in2
60
30
0
10-1
100
101
t, RECTANGULAR PULSE DURATION (s)
FIGURE 24. THERMAL IMPEDANCE vs MOUNTING PAD AREA
8
102
103
HUF76121SK8
PSPICE Electrical Model
.SUBCKT HUF76121SK8 2 1 3 ;
REV January 1999
CA 12 8 1.3e-9
CB 15 14 1.28e-9
CIN 6 8 7.6e-10
LDRAIN
DPLCAP
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
DRAIN
2
5
10
RLDRAIN
RSLC1
51
+
RSLC2
5
51
EBREAK 11 7 17 18 33.4
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
DBREAK
ESLC
11
-
RDRAIN
6
8
ESG
EVTHRES
+ 19 8
+
LGATE
IT 8 17 1
EVTEMP
RGATE +
18 22
9
20
GATE
1
LDRAIN 2 5 1e-9
LGATE 1 9 2.98e-9
LSOURCE 3 7 6.8e-10
+
17
EBREAK 18
50
-
21
16
MWEAK
6
MMED
MSTRO
RLGATE
LSOURCE
CIN
8
SOURCE
3
7
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RSOURCE
RLSOURCE
S1A
12
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 5.7e-3
RGATE 9 20 4
RLDRAIN 2 5 10
RLGATE 1 9 29.8
RLSOURCE 3 7 6.8
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 9.8e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A
S1B
S2A
S2B
DBODY
-
S2A
13
8
14
13
S1B
17
18
RVTEMP
S2B
13
CA
RBREAK
15
CB
6
8
EGS
-
19
-
IT
14
+
+
VBAT
5
8
EDS
-
+
8
22
RVTHRES
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*181),4))}
.MODEL DBODYMOD D (IS = 2e-13 RS = 9.5e-3 TRS1 = 1e-3 TRS2 = 3e-6 CJO = 1.33e-9 TT = 2.8e-8 M = 0.4 XTI = 4.3 N = 0.95 IKF = 5)
.MODEL DBREAKMOD D (RS = 1.05e-1 TRS1 = 0 TRS2 = 2.5e-5)
.MODEL DPLCAPMOD D (CJO = 8.2e-10 IS = 1e-30 N = 10 M = 0.63)
.MODEL MMEDMOD NMOS (VTO = 1.9 KP = 4 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 4)
.MODEL MSTROMOD NMOS (VTO = 2.23 KP = 42.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.64 KP = 0.1 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 40 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 9.7e-4 TC2 = 7e-7)
.MODEL RDRAINMOD RES (TC1 = 6.5e-3 TC2 = 1.8e-5)
.MODEL RSLCMOD RES (TC1 = 5e-3 TC2 = 8e-6)
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6)
.MODEL RVTHRESMOD RES (TC = -1.5e-3 TC2 = -4.8e-6)
.MODEL RVTEMPMOD RES (TC1 = -1.6e-3 TC2 = 1e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5
.MODEL S1BMOD VSWITCH (RON = 1e-5
.MODEL S2AMOD VSWITCH (RON = 1e-5
.MODEL S2AMOD VSWITCH (RON = 1e-5
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
VON = -5 VOFF= -3)
VON = -3 VOFF= -5)
VON = -1 VOFF= 1.2)
VON = 1.2 VOFF= -1)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
9
HUF76121SK8
SABER Electrical Model
REV January 1999
template huf76121sk8 n2, n1, n3
electrical n2, n1, n3
{
var i iscl
d..model dbodymod = (is = 2e-13, xti = 4.3, cjo = 1.33e-9, tt = 2.8e-8, n = 0.95, m = 0.4)
d..model dbreakmod = ()
d..model dplcapmod = (cjo = 8.2e-10, is = 1e-30, n = 10, m = 0.63)
DPLCAP
m..model mmedmod = (type=_n, vto = 1.9, kp = 4, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 2.23, kp = 42.5, is = 1e-30, tox = 1)
10
m..model mweakmod = (type=_n, vto = 1.64, kp = 0.1, is = 1e-30, tox = 1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -5, voff = -3)
sw_vcsp..model s1bmod = (ron = 1e-5, roff = 0.1, von = -3, voff = -5)
RSLC2
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -1, voff = 1.2)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 1.2, voff = -1)
c.ca n12 n8 = 1.3e-9
c.cb n15 n14 = 1.28e-9
c.cin n6 n8 = 7.6e-10
LDRAIN
d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = model=dbreakmod
d.dplcap n10 n5 = model=dplcapmod
GATE
1
i.it n8 n17 = 1
RDBREAK
72
ISCL
6
8
EVTHRES
+ 19 8
EVTEMP
RGATE +
18 22
9
20
21
71
11
16
MWEAK
DBODY
6
EBREAK
+
17
18
MMED
MSTRO
RLGATE
l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 2.98e-9
l.lsource n3 n7 = 6.8e-10
RDBODY
DBREAK
50
RDRAIN
+
LGATE
RLDRAIN
RSLC1
51
ESG
DRAIN
2
5
CIN
-
8
LSOURCE
SOURCE
3
7
RSOURCE
RLSOURCE
m.mmed n16 n6 n8 n8 = model=mmedmod, l = 1u, w = 1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l = 1u, w = 1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l = 1u, w = 1u
res.rbreak n17 n18 = 1, tc1 = 9.7e-4, tc2 = 7e-7
res.rdbody n71 n5 = 9.5e-3, tc1 = 1e-3, tc2 = 3e-6
res.rdbreak n72 n5 = 1.05e-1, tc1 = 0, tc2 = 2.5e-5
res.rdrain n50 n16 = 5.7e-3, tc1 = 6.5e-3, tc2 = 1.8e-5
res.rgate n9 n20 = 4
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 29.8
res.rlsource n3 n7 = 6.8
res.rslc1 n5 n51 = 1e-6, tc1 = 5e-3, tc2 = 8e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 9.8e-3, tc1 = 1e-3, tc2 = 1e-6
res.rvtemp n18 n19 = 1, tc1 = -1.6e-3, tc2 = 1e-6
res.rvthres n22 n8 = 1, tc1 = -1.5e-3, tc2 = -4.8e-6
S1A
12
S2A
13
8
14
13
S1B
CA
17
18
RVTEMP
S2B
13
CB
6
8
EGS
19
-
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc = 1
equations {
i (n51->n50) + = iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/181))** 4))
}
}
-
IT
14
+
+
spe.ebreak n11 n7 n17 n18 = 33.4
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
10
RBREAK
15
VBAT
5
8
EDS
-
+
8
22
RVTHRES
HUF76121SK8
SPICE Thermal Model
REV November 1998
HUF76121SK8
Copper Area = 0.04 in2
CTHERM1 th 8 2.0e-3
CTHERM2 8 7 5.0e-3
CTHERM3 7 6 1.0e-2
CTHERM4 6 5 4.0e-2
CTHERM5 5 4 9.0e-2
CTHERM6 4 3 1.2e-1
CTHERM7 3 2 0.5
CTHERM8 2 tl 1.3
th
JUNCTION
CTHERM1
RTHERM1
8
CTHERM2
RTHERM2
RTHERM1 th 8 0.1
RTHERM2 8 7 0.5
RTHERM3 7 6 1.0
RTHERM4 6 5 5.0
RTHERM5 5 4 8.0
RTHERM6 4 3 26
RTHERM7 3 2 39
RTHERM8 2 tl 55
7
CTHERM3
RTHERM3
6
RTHERM4
SABER Thermal Model
CTHERM4
5
Copper Area = 0.04 in2
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 8 = 2.0e-3
ctherm.ctherm2 8 7 = 5.0e-3
ctherm.ctherm3 7 6 = 1.0e-2
ctherm.ctherm4 6 5 = 4.0e-2
ctherm.ctherm5 5 4 = 9.0e-2
ctherm.ctherm6 4 3 = 1.2e-1
ctherm.ctherm7 3 2 = 0.5
ctherm.ctherm8 2 tl = 1.3
CTHERM5
RTHERM5
4
RTHERM6
CTHERM6
3
RTHERM7
CTHERM7
2
rtherm.rtherm1 th 8 = 0.1
rtherm.rtherm2 8 7 = 0.5
rtherm.rtherm3 7 6 = 1.0
rtherm.rtherm4 6 5 = 5.0
rtherm.rtherm5 5 4 = 8.0
rtherm.rtherm6 4 3 = 26
rtherm.rtherm7 3 2 = 39
rtherm.rtherm8 2 tl = 55
}
RTHERM8
CTHERM8
tl
CASE
TABLE 1. Thermal Models
0.04 in2
0.28 in2
0.52 in2
0.76 in2
1.0 in2
CTHERM6
1.2e-1
1.5e-1
2.0e-1
2.0e-1
2.0e-1
CTHERM7
0.5
1.0
1.0
1.0
1.0
CTHERM8
1.3
2.8
3.0
3.0
3.0
RTHERM6
26
20
15
13
12
RTHERM7
39
24
21
19
18
RTHERM8
55
38.7
31.3
29.7
25
COMPONANT
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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11