HUF76113T3ST
TM
Data Sheet
June 2000
4.7A, 30V, 0.031 Ohm, N-Channel, Logic
Level UltraFET Power MOSFET
File Number
4388.3
Features
• Logic Level Gate Drive
This N-Channel power MOSFET is
® manufactured using the innovative
UltraFET process. This advanced
process technology achieves the
lowest possible on-resistance per silicon area, resulting in
outstanding performance. This device is capable of
withstanding high energy in the avalanche mode and the
diode exhibits very low reverse recovery time and stored
charge. It was designed for use in applications where power
efficiency is important, such as switching regulators, switching
converters, motor drivers, relay drivers, low-voltage bus
switches, and power management in portable and batteryoperated products.
• 4.7A, 30V
• Ultra Low On-Resistance, rDS(ON) = 0.031Ω
• Temperature Compensating PSPICE® Model
• Temperature Compensating SABER™ Model
• Thermal Impedance SPICE Model
• Thermal Impedance SABER Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
Formerly developmental type TA76113.
• Related Literature
- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”
Ordering Information
Symbol
PART NUMBER
PACKAGE
BRAND
D
HUF76113T3ST
SOT-223
76113
NOTE: HUF76113T3ST is available only in tape and reel.
G
S
Packaging
SOT-223
DRAIN
(FLANGE)
SOURCE
DRAIN
GATE
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
UltraFET® is a registered trademark of Intersil Corporation.
PSPICE® is a registered trademark of MicroSim Corporation. SABER™ is a trademark of Analogy, Inc.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000
HUF76113T3ST
Absolute Maximum Ratings
TA = 25oC, Unless Otherwise Specified
HUF76113T3ST
UNITS
30
30
±16
V
V
V
4.7
2.7
2.6
Figure 4
Figure 6
1.1
0.0091
-55 to 150
A
A
A
W
W/oC
oC
300
260
oC
oC
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
Drain Current
Continuous (TA= 25oC, VGS = 10V) (Figure 2) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TA= 100oC, VGS = 5V) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TA= 100oC, VGS = 4.5V) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS
Power Dissipation (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 150oC.
TA = 25oC, Unless Otherwise Specified
Electrical Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
30
-
-
V
VDS = 25V, VGS = 0V
-
-
1
µA
VDS = 25V, VGS = 0V, TC = 150oC
-
-
250
µA
VGS = ±16V
-
-
±100
nA
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
BVDSS
Zero Gate Voltage Drain Current
IDSS
Gate to Source Leakage Current
IGSS
ID = 250µA, VGS = 0V (Figure 12)
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250µA (Figure 11)
1
-
3
V
Drain to Source On Resistance
rDS(ON)
ID = 4.7A, VGS = 10V (Figure 9, 10)
-
0.027
0.031
W
ID = 2.7A, VGS = 5V (Figure 9)
-
0.033
0.038
W
ID = 2.6A, VGS = 4.5V (Figure 9)
-
0.035
0.040
W
Pad Area = 0.173 in2 (Note 2)
-
-
110
oC/W
Pad Area = 0.068 in2 (See TB377)
-
-
133
oC/W
Pad Area = 0.026 in2 (See TB377)
-
-
157
oC/W
VDD = 15V, ID ≅ 2.6A,
RL = 5.8Ω, VGS = 4.5V,
RGS = 18Ω
(Figure 15)
-
-
90
ns
-
12
-
ns
-
46
-
ns
td(OFF)
-
31
-
ns
tf
-
31
-
ns
tOFF
-
-
95
ns
THERMAL SPECIFICATIONS
Thermal Resistance Junction to Ambient
RθJA
SWITCHING SPECIFICATIONS (VGS = 4.5V)
Turn-On Time
tON
Turn-On Delay Time
td(ON)
Rise Time
tr
Turn-Off Delay Time
Fall Time
Turn-Off Time
2
HUF76113T3ST
TA = 25oC, Unless Otherwise Specified
Electrical Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
-
-
40
ns
-
4
-
ns
-
21
-
ns
td(OFF)
-
31
-
ns
tf
-
25
-
ns
tOFF
-
-
85
ns
-
17.0
20.5
nC
-
9.5
11.5
nC
-
0.73
0.90
nC
SWITCHING SPECIFICATIONS (VGS = 10V)
Turn-On Time
tON
Turn-On Delay Time
td(ON)
Rise Time
tr
Turn-Off Delay Time
Fall Time
Turn-Off Time
VDD = 15V, ID ≅ 4.7A,
RL = 3.2Ω, VGS = 10V,
RGS = 9.1Ω
(Figure 16)
GATE CHARGE SPECIFICATIONS
Total Gate Charge
Qg(TOT)
VGS = 0V to 10V
Gate Charge at 5V
Qg(5)
VGS = 0V to 5V
Qg(TH)
VGS = 0V to 1V
Threshold Gate Charge
VDD = 15V, ID ≅ 2.7A,
RL = 5.5Ω
Ig(REF) = 1.0mA
(Figure 14)
Gate to Source Gate Charge
Qgs
-
1.50
-
nC
Gate to Drain “Miller” Charge
Qgd
-
4.30
-
nC
-
625
-
pF
-
310
-
pF
-
60
-
pF
MIN
TYP
MAX
UNITS
ISD = 4.7A
-
-
1.25
V
ISD = 2.7A
-
-
1.00
V
trr
ISD = 2.7A, dISD/dt = 100A/µs
-
-
44
ns
QRR
ISD = 2.7A, dISD/dt = 100A/µs
-
-
46
nC
CAPACITANCE SPECIFICATIONS
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
VDS = 25V, VGS = 0V,
f = 1MHz
(Figure 13)
NOTES:
2. Rated with RθJA=110oC/W measured using FR-4 board with 0.173 in2 copper at 1000 seconds.
Source to Drain Diode Specifications
PARAMETER
SYMBOL
Source to Drain Diode Voltage
VSD
Reverse Recovery Time
Reverse Recovered Charge
TEST CONDITIONS
Typical Performance Curves
5
VGS = 10V, RθJA = 110oC/W
1.0
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
1.2
0.8
0.6
0.4
0.2
4
3
VGS = 4.5V, RθJA = 110oC/W
2
1
0
0
0
25
50
75
100
125
150
TA , AMBIENT TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT
TEMPERATURE
3
25
50
75
100
125
150
TA, AMBIENT TEMPERATURE (oC)
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
AMBIENT TEMPERATURE
HUF76113T3ST
Typical Performance Curves
2
ZθJA, NORMALIZED
THERMAL IMPEDANCE
1
0.1
(Continued)
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
RθJA = 110oC/W
PDM
t1
0.01
t2
SINGLE PULSE
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
0.001
10-5
10-4
10-3
10-2
10-1
100
101
102
103
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
IDM, PEAK CURRENT (A)
500
RθJA = 110oC/W
100
TC = 25oC
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
I
VGS = 5V
= I25
150 - TA
125
VGS = 10V
10
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
1
10-5
10-4
10-3
10-2
10-1
100
101
102
103
t, PULSE WIDTH (s)
FIGURE 4. PEAK CURRENT CAPABILITY
TJ = MAX RATED
TA = 25oC
ID, DRAIN CURRENT (A)
100
100µs
10
1ms
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
10ms
VDSS(MAX) = 30V
1
1
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
IAS, AVALANCHE CURRENT (A)
40
200
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
10
STARTING TJ = 25oC
STARTING TJ = 150oC
1
100
0.01
0.1
1
10
100
tAV, TIME IN AVALANCHE (ms)
NOTE: Refer to Intersil Application Notes AN9321 and AN9322.
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
4
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
HUF76113T3ST
Typical Performance Curves
30
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
25
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
30
(Continued)
20
15
10
150oC
VGS = 3.5V
20
15
10
VGS = 3V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TA = 25oC
5
5
25oC
VGS = 10V
VGS = 5V
VGS = 4V
25
-55oC
0
0
0
1
2
3
4
VGS, GATE TO SOURCE VOLTAGE (V)
0
5
FIGURE 7. TRANSFER CHARACTERISTICS
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
rDS(ON), DRAIN TO SOURCE
ON RESISTANCE (mΩ)
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
70
60
ID = 4.7A
50
40
ID = 0.5A
30
1.6
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = 10V, ID = 4.7A
1.4
1.2
1.0
0.8
0.6
20
2
4
6
8
10
-80
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
VGS, GATE TO SOURCE VOLTAGE (V)
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
FIGURE 10. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
1.2
1.1
1.0
0.9
0.8
0.7
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
1.2
VGS = VDS, ID = 250µA
NORMALIZED GATE
THRESHOLD VOLTAGE
4
FIGURE 8. SATURATION CHARACTERISTICS
1.8
80
1
2
3
VDS, DRAIN TO SOURCE VOLTAGE (V)
ID = 250µA
1.1
1.0
0.9
0.6
-80
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
5
-80
-40
0
40
80
120
160
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
HUF76113T3ST
Typical Performance Curves
(Continued)
10
VGS , GATE TO SOURCE VOLTAGE (V)
C, CAPACITANCE (pF)
1000
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS = CDS + CGD
800
CISS
600
400
COSS
200
CRSS
0
0
5
10
15
20
25
VDS , DRAIN TO SOURCE VOLTAGE (V)
VDD = 15V
8
6
4
WAVEFORMS IN
DESCENDING ORDER:
ID = 4.7A
ID = 0.5A
2
0
0
30
10
15
20
Qg, GATE CHARGE (nC)
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
150
100
VGS = 4.5V, VDD = 15V, ID = 2.6A, RL = 5.8Ω
VGS = 10V, VDD = 15V, ID = 4.7A, RL = 3.2Ω
tr
80
SWITCHING TIME (ns)
SWITCHING TIME (ns)
5
td(OFF)
60
tf
40
td(ON)
120
td(OFF)
90
tf
60
tr
30
20
td(ON)
0
0
0
10
20
30
40
0
50
RGS, GATE TO SOURCE RESISTANCE (Ω)
10
20
30
40
50
RGS, GATE TO SOURCE RESISTANCE (Ω)
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
FIGURE 16. SWITCHING TIME vs GATE RESISTANCE
Test Circuits and Waveforms
VDS
BVDSS
L
VARY tP TO OBTAIN
REQUIRED PEAK IAS
tP
+
RG
VDS
IAS
VDD
VDD
-
VGS
DUT
0V
tP
IAS
0
0.01Ω
tAV
FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT
6
FIGURE 18. UNCLAMPED ENERGY WAVEFORMS
HUF76113T3ST
Test Circuits and Waveforms
(Continued)
VDS
VDD
RL
Qg(TOT)
VDS
VGS = 10
VGS
Qg(5)
+
VDD
VGS = 5V
VGS
DUT
VGS = 1V
Ig(REF)
0
Qg(TH)
Ig(REF)
0
FIGURE 19. GATE CHARGE TEST CIRCUIT
FIGURE 20. GATE CHARGE WAVEFORMS
VDS
tON
tOFF
td(ON)
td(OFF)
tf
tr
RL
VDS
90%
90%
+
VGS
-
VDD
10%
10%
0
DUT
90%
RGS
VGS
VGS
0
FIGURE 21. SWITCHING TIME TEST CIRCUIT
10%
50%
50%
PULSE WIDTH
FIGURE 22. SWITCHING TIME WAVEFORM
Thermal Resistance vs. Mounting
Pad Area
The maximum rated junction temperature, TJM, and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, PDM, in an
application. Therefore the application’s ambient temperature,
TA (oC), and thermal resistance RθJA (oC/W) must be
reviewed to ensure that TJM is never exceeded. Equation 1
mathematically represents the relationship and serves as
the basis for establishing the rating of the part.
In using surface mount devices such as the SOT-223
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
power dissipation ratings. Precise determination of PDM is
complex and influenced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
( T JM – T A )
P DM = ------------------------------Z θJA
(EQ. 1)
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
7
HUF76113T3ST
Intersil provides thermal information to assist the designer’s
preliminary application evaluation. Figure 23 defines the
RθJA for the device as a function of the top copper
(component side) area. This is for a horizontally positioned
FR-4 board with 1oz copper after 1000 seconds of steady
state power with no air flow. This graph provides the
necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Intersil device Spice
thermal model or manually utilizing the normalized maximum
transient thermal impedance curve. Displayed on the curve
are RθJA values listed in the Electrical Specifications table.
The points were chosen to depict the compromise between
the copper board area, the thermal resistance and ultimately
the power dissipation, PDM. The smallest areas represent
200
RθJA (oC/W)
157oC/W - 0.026in2
150
133oC/W - 0.068in2
100
RθJA = 65.3 - 25 * ln(AREA)
0.1
Thermal resistances corresponding to other copper areas
can be obtained from Figure 23 or by calculation using
Equation 2. RθJA is defined as the natural log of the area
times a coefficient added to a constant. The area, in square
inches is the top copper area including the gate and source
pads.
R θJA = 65.3 – 25 ×
ln ( Area )
(EQ. 2)
The transient thermal impedance (ZθJA) is also effected by
varied top copper board area. Figure 24 shows the effect of
copper pad area on single pulse transient thermal
impedance. Each trace represents a copper pad area in
square inches corresponding to the descending list in the
graph. Spice and SABER thermal models are provided for
each of the listed pad areas.
Copper pad area has no perceivable effect on transient
thermal impedance for pulse widths less than 100ms. For
pulse widths less than 100ms the transient thermal
impedance is determined by the die and package.
Therefore, CTHERM1 through CTHERM5 and RTHERM1
through RTHERM5 remain constant for each of the thermal
models. A listing of the model component values is
available in Table 1.
110oC/W - 0.173in2
50
0.01
the minimum bond pad area and the package outline area
respectively as determined from the package diagram
1
AREA, TOP COPPER AREA (in2)
FIGURE 23. THERMAL RESISTANCE vs MOUNTING PAD AREA
120
COPPER BOARD AREA - DESCENDING ORDER
0.077 in2
0.308 in2
0.535 in2
0.760 in2
0.996 in2
IMPEDANCE (oC/W)
ZθJA, THERMAL
100
80
60
40
20
0
10-1
100
101
t, RECTANGULAR PULSE DURATION (s)
FIGURE 24. THERMAL IMPEDANCE vs MOUNTING PAD AREA
8
102
103
HUF76113T3ST
PSPICE Electrical Model
.SUBCKT HUF76113T3 2 1 3 ;
REV August 1998
CA 12 8 8.7e-10
CB 15 14 8.7e-10
CIN 6 8 5.6e-10
LDRAIN
DPLCAP
DRAIN
2
5
10
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
ESLC
11
-
EBREAK 11 7 17 18 34.3
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
RDRAIN
6
8
ESG
EVTHRES
+ 19 8
+
LGATE
GATE
1
+
17
EBREAK 18
50
-
EVTEMP
RGATE +
18 22
9
20
21
DBODY
-
16
MWEAK
6
MMED
MSTRO
RLGATE
LDRAIN 2 5 1e-9
LGATE 1 9 1.69e-9
LSOURCE 3 7 4.1e-10
LSOURCE
CIN
8
SOURCE
3
7
RSOURCE
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RLSOURCE
S1A
12
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 9.2e-3
RGATE 9 20 2.5
RLDRAIN 2 5 10
RLGATE 1 9 16.9
RLSOURCE 3 7 4.1
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 12.5e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A
S1B
S2A
S2B
DBREAK
+
RSLC2
5
51
IT 8 17 1
RLDRAIN
RSLC1
51
S2A
13
8
14
13
S1B
CA
RBREAK
15
17
18
RVTEMP
S2B
13
CB
6
8
EGS
19
VBAT
5
8
EDS
-
-
IT
14
+
+
-
+
8
22
RVTHRES
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*180),2.5))}
.MODEL DBODYMOD D (IS = 9.35e-13 RS = 1.39e-2 TRS1 = 1.12e-6 TRS2 = 1.05e-6 CJO = 9.85e-10 TT = 2.82e-8 M = 0.42)
.MODEL DBREAKMOD D (RS = 1.5e-1 TRS1 = 3.51e-3 TRS2 = -5e-5)
.MODEL DPLCAPMOD D (CJO = 4.4e-10 IS = 1e-30 N = 10 M = 0.6)
.MODEL MMEDMOD NMOS (VTO = 1.95 KP = 3.55 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 2.5)
.MODEL MSTROMOD NMOS (VTO = 2.23 KP = 29 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.68 KP = 0.095 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 25 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 9.7e-4 TC2 = -5e-7)
.MODEL RDRAINMOD RES (TC1 = 5.8e-3 TC2 = 1.12e-5)
.MODEL RSLCMOD RES (TC1 = -9.92e-3 TC2 = -2.06e-5)
.MODEL RSOURCEMOD RES (TC1 = 3e-3 TC2 = 0)
.MODEL RVTHRESMOD RES (TC = -1.2e-3 TC2 = -5.42e-6)
.MODEL RVTEMPMOD RES (TC1 = -1.9e-3 TC2 = 1e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5
.MODEL S1BMOD VSWITCH (RON = 1e-5
.MODEL S2AMOD VSWITCH (RON = 1e-5
.MODEL S2AMOD VSWITCH (RON = 1e-5
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
VON = -7.0 VOFF = -1.5)
VON = -1.5 VOFF = -7.0)
VON = -0.8 VOFF = 0.6)
VON = 0.6 VOFF = -0.8)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
9
HUF76113T3ST
SABER Electrical Model
REV October 1998
template huf76113T3 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
d..model dbodymod = (is = 9.35e-13, cjo = 9.85e-10, tt = 2.82e-8, m = 0.42)
d..model dbreakmod = ()
d..model dplcapmod = (cjo = 4.4e-10, is = 1e-30, n = 10, m = 0.6)
m..model mmedmod = (type=_n, vto = 1.95, kp = 3.55, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 2.23, kp = 29, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 1.68, kp = 0.095, is = 1e-30, tox = 1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -7.0, voff = -1.5)
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -1.5, voff = -7.0)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.8, voff = 0.6)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.6, voff = -0.8)
LDRAIN
DPLCAP
DRAIN
2
5
10
RSLC1
51
RLDRAIN
RDBREAK
RSLC2
c.ca n12 n8 = 8.7e-10
c.cb n15 n14 = 8.7e-10
c.cin n6 n8 = 5.6e-10
72
ISCL
d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = model=dbreakmod
d.dplcap n10 n5 = model=dplcapmod
EVTHRES
+ 19 8
+
LGATE
i.it n8 n17 = 1
RDRAIN
6
8
ESG
GATE
1
l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 1.69e-9
l.lsource n3 n7 = 4.1e-10
EVTEMP
RGATE + 18 22
9
20
21
MSTRO
-
8
LSOURCE
7
RLSOURCE
S1A
S2A
13
8
S1B
CA
RBREAK
15
14
13
17
18
RVTEMP
S2B
13
CB
6
8
EGS
19
-
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/180))** 2.5))
}
}
-
IT
14
+
+
spe.ebreak n11 n7 n17 n18 = 34.3
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
10
DBODY
EBREAK
+
17
18
RSOURCE
12
res.rbreak n17 n18 = 1, tc1 = 9.7e-4, tc2 = -5e-7
res.rdbody n71 n5 = 1.39e-2, tc1 = 1.12e-6, tc2 = 1.05e-6
res.rdbreak n72 n5 = 1.5e-1, tc1 = 3.51e-3, tc2 = -5e-5
res.rdrain n50 n16 = 9.2e-3, tc1 = 5.8e-3, tc2 = 1.12e-5
res.rgate n9 n20 = 2.5
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 16.9
res.rlsource n3 n7 = 4.1
res.rslc1 n5 n51 = 1e-6, tc1 = -9.92e-3, tc2 = -2.06e-5
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 12.5e-3, tc1 = 3e-3, tc2 = 0
res.rvtemp n18 n19 = 1, tc1 = -1.9e-3, tc2 = 1e-6
res.rvthres n22 n8 = 1, tc1 = -1.2e-3, tc2 = -5.42e-6
MWEAK
MMED
CIN
71
11
16
6
RLGATE
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
DBREAK
50
-
RDBODY
VBAT
5
8
EDS
-
+
8
22
RVTHRES
SOURCE
3
HUF76113T3ST
SPICE Thermal Model
th
REV August 1998
HUF76113T3ST
Copper Area = 0.077 in2
CTHERM1 th 8 1.9e-5
CTHERM2 8 7 9.5e-4
CTHERM3 7 6 1.9e-3
CTHERM4 6 5 3.5e-3
CTHERM5 5 4 2.0e-2
CTHERM6 4 3 6.5e-2
CTHERM7 3 2 2.4e-1
CTHERM8 2 tl 9.0e-1
JUNCTION
CTHERM1
RTHERM1
8
CTHERM2
RTHERM2
7
RTHERM1 th 8 3.5e-3
RTHERM2 8 7 3.1e-2
RTHERM3 7 6 2.0e-1
RTHERM4 6 5 8.0e-1
RTHERM5 5 4 2.1
RTHERM6 4 3 11
RTHERM7 3 2 32
RTHERM8 2 tl 66
RTHERM3
SABER Thermal Model
RTHERM5
CTHERM3
6
CTHERM4
RTHERM4
5
Copper Area = 0.077 in2
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 8 = 1.9e-5
ctherm.ctherm2 8 7 = 9.5e-4
ctherm.ctherm3 7 6 = 1.9e-3
ctherm.ctherm4 6 5 = 3.5e-3
ctherm.ctherm5 5 4 = 2.0e-2
ctherm.ctherm6 4 3 = 6.5e-2
ctherm.ctherm7 3 2 = 2.4e-1
ctherm.ctherm8 2 tl = 9.0e-1
CTHERM5
4
CTHERM6
RTHERM6
3
CTHERM7
RTHERM7
2
CTHERM8
RTHERM8
rtherm.rtherm1 th 8 = 3.5e-3
rtherm.rtherm2 8 7 = 3.1e-2
rtherm.rtherm3 7 6 = 2.0e-1
rtherm.rtherm4 6 5 = 8.0e-1
rtherm.rtherm5 5 4 = 2.1
rtherm.rtherm6 4 3 = 11
rtherm.rtherm7 3 2 = 32
rtherm.rtherm8 2 tl = 66
}
tl
AMBIENT
TABLE 1. THERMAL MODELS
0.077 in2
0.308 in2
0.535 in2
0.76 in2
0.996 in2
CTHERM6
6.5e-2
6.7e-2
6.7e-2
6.7e-2
6.7e-2
CTHERM7
2.4e-1
3.5e-1
3.5e-1
3.5e-1
3.5e-1
CTHERM8
9.0e-1
1.7
1.9
2
2.4
RTHERM6
11
9
9
9
9
RTHERM7
32
18
16
15.5
14.5
RTHERM8
66
45.5
40
36
31.5
COMPONENT
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
11
HUF76113T3ST
SOT-223 (TO-261AA)
SMALL OUTLINE TRANSISTOR
D
INCHES
A
D1
E
A1
E1
c
e
L
b
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.063
0.070
1.60
1.78
-
A1
0.0008
0.004
0.02
0.10
-
b
0.026
0.033
0.65
0.85
-
c
0.010
0.014
0.25
0.35
-
D
0.248
0.264
6.30
6.70
D1
0.116
0.124
2.95
3.15
E
0.264
0.287
6.70
7.30
-
E1
0.130
0.146
3.30
3.70
2
e
0-10
MILLIMETERS
L
0.0905 BSC
0.036
-
2.30 BSC
0.91
-
3
NOTES:
1. All dimensions are within the allowable dimensions of Rev. A of
JEDEC TO-261 outline dated 1-90.
2. Dimension "E1" does not include inter-lead flash or gate burr protrusions. Inter-lead flash and protrusions shall not exceed 0.010
inches (.25mm) per side.
3. "L" is the length of terminal for soldering.
4. Controlling dimension: Millimeter.
5. Revision 5 dated 5-99.
0.003 IN
0.08 mm
0.15
3.8
0.079
2.0
0.244
6.2
0.079
2.0
0.059
1.5
0.091
2.3
0.181
4.6
MINIMUM RECOMMENDED FOOTPRINT FOR
SURFACE MOUNTED APPLICATIONS
SOT-223
1.5mm
DIA. HOLE
4.0mm
USER DIRECTION OF FEED
1.75mm
2.0mm
C
L
16mm TAPE AND REEL
16mm
8.0mm
COVER TAPE
ACCESS HOLE
22.4mm
13mm
330mm
100mm
GENERAL INFORMATION
1. 3500 PIECES PER REEL.
2. ORDER IN MULTIPLES OF FULL REELS ONLY.
3. MEETS EIA-481 REVISION "A" SPECIFICATIONS.
12
16.4mm