PWM Optimized
ISL9N303AP3 / ISL9N303AS3ST / ISL9N303AS3
N-Channel Logic Level UltraFET® Trench MOSFETs
30V, 75A, 3.2mΩ
General Description
Features
This device employs a new advanced trench MOSFET
technology and features low gate charge while maintaining
low on-resistance.
• Fast switching
Optimized for switching applications, this device improves
the overall efficiency of DC/DC converters and allows
operation to higher switching frequencies.
• rDS(ON) = 0.004Ω (Typ), VGS = 4.5V
• Qg (Typ) = 61nC, VGS = 5V
Applications
• Qgd (Typ) = 17nC
• DC/DC converters
• CISS (Typ) = 7000pF
DRAIN
(FLANGE)
SOURCE
DRAIN
DRAIN
(FLANGE)
SOURCE
DRAIN
• rDS(ON) = 0.0026Ω (Typ), VGS = 10V
GATE
D
GATE
G
GATE
SOURCE
TO-220AB
TO-263AB
DRAIN
(FLANGE)
S
TO-262AB
MOSFET Maximum Ratings TC= 25°C unless otherwise noted
Symbol
VDSS
Drain to Source Voltage
Parameter
Ratings
30
Units
V
VGS
Gate to Source Voltage
±20
V
Drain Current
ID
Continuous (TC = 25oC, VGS = 10V)
75
A
Continuous (TC = 100oC, VGS = 4.5V)
75
A
Continuous (TC = 25oC, VGS = 10V, RθJA = 43oC/W)
25
A
Pulsed
Figure 4
PD
Power dissipation
Derate above
TJ, TSTG
Operating and Storage Temperature
215
1.43
W
W/oC
-55 to 175
o
C
Thermal Characteristics
RθJC
Thermal Resistance Junction to Case TO-220, TO-262, TO-263
0.7
oC/W
RθJA
Thermal Resistance Junction to Ambient TO-220, TO-262, TO-263
62
o
RθJA
Thermal Resistance Junction to Ambient TO-263, 1in2 copper pad area
43
o
C/W
C/W
Package Marking and Ordering Information
Device Marking
N303AS
Device
ISL9N303AS3ST
Package
TO-263AB
Reel Size
330mm
Tape Width
24mm
Quantity
800 units
N303AP
ISL9N303AP3
TO-220AB
Tube
N/A
50 units
N303AS
ISL9N303AS3
TO-262AA
Tube
N/A
50 units
©2002 Fairchild Semiconductor Corporation
ISL9N303AP3 / ISL9N303AS3ST / ISL9N303AS3, Rev. C1
ISL9N303AP3 / ISL9N303AS3ST / ISL9N303AS3
September 2002
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
30
-
-
-
V
-
1
-
-
250
µA
VGS = ±20V
-
-
±100
nA
-
3
V
Off Characteristics
BVDSS
Drain to Source Breakdown Voltage
IDSS
Zero Gate Voltage Drain Current
IGSS
Gate to Source Leakage Current
ID = 250µA, VGS = 0V
VDS = 25V
VGS = 0V
TC = 150o
On Characteristics
VGS(TH)
rDS(ON)
Gate to Source Threshold Voltage
Drain to Source On Resistance
VGS = VDS, ID = 250µA
1
ID = 75A, VGS = 10V
-
0.0026 0.0032
ID = 75A, VGS = 4.5V
-
0.004
0.005
-
7000
-
pF
-
1350
-
pF
-
570
-
pF
115
172
nC
Ω
Dynamic Characteristics
CISS
Input Capacitance
COSS
Output Capacitance
CRSS
Reverse Transfer Capacitance
Qg(TOT)
Total Gate Charge at 10V
VGS = 0V to 10V
VGS = 0V to 5V V = 15V
DD
VGS = 0V to 1V ID = 75A
Ig = 1.0mA
Qg(5)
Total Gate Charge at 5V
Qg(TH)
Threshold Gate Charge
Qgs
Gate to Source Gate Charge
Qgd
Gate to Drain “Miller” Charge
Switching Characteristics
VDS = 15V, VGS = 0V,
f = 1MHz
-
61
92
nC
-
6.5
9.8
nC
-
14
-
nC
-
17
-
nC
(VGS = 4.5V)
tON
Turn-On Time
-
-
155
ns
td(ON)
Turn-On Delay Time
-
22
-
ns
tr
Rise Time
-
80
-
ns
td(OFF)
Turn-Off Delay Time
-
35
-
ns
tf
Fall Time
-
25
-
ns
tOFF
Turn-Off Time
-
-
90
ns
Switching Characteristics
VDD = 15V, ID = 24A
VGS = 4.5V, RG = 2.4Ω
(VGS = 10V)
tON
Turn-On Time
-
-
123
ns
td(ON)
Turn-On Delay Time
-
12
-
ns
tr
Rise Time
-
69
-
ns
td(OFF)
Turn-Off Delay Time
-
51
-
ns
tf
Fall Time
-
21
-
ns
tOFF
Turn-Off Time
-
-
107
ns
275
-
-
µs
V
VDD = 15V, ID = 24A
VGS = 10V, RG = 2.4Ω
Unclamped Inductive Switching
tAV
Avalanche Time
ID = 4.1A L = 3.0 mH
Drain-Source Diode Characteristics
ISD = 75A
-
-
1.25
ISD = 35A
-
-
1.0
V
Reverse Recovery Time
ISD = 75A, dISD/dt = 100A/µs
-
-
31
ns
Reverse Recovered Charge
ISD = 75A, dISD/dt = 100A/µs
-
-
20
nC
VSD
Source to Drain Diode Voltage
trr
QRR
©2002 Fairchild Semiconductor Corporation
ISL9N303AP3 / ISL9N303AS3ST / ISL9N303AS3, Rev. C1
ISL9N303AP3 / ISL9N303AS3ST / ISL9N303AS3
Electrical Characteristics TC = 25°C unless otherwise noted
POWER DISSIPATION MULTIPLIER
1.2
80
1
ID, DRAIN CURRENT (A)
VGS = 10V
0.8
0.6
0.4
60
VGS = 4.5V
40
20
0.2
0
0
0
25
50
75
100
150
125
25
175
50
75
TC , CASE TEMPERATURE (oC)
100
125
150
175
TC, CASE TEMPERATURE (oC)
Figure 1. Normalized Power Dissipation vs
Ambient Temperature
Figure 2. Maximum Continuous Drain Current vs
Case Temperature
2
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
ZθJC, NORMALIZED
THERMAL IMPEDANCE
1
PDM
0.1
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
SINGLE PULSE
0.01
10-5
10-4
10-3
10-2
10-1
100
101
t, RECTANGULAR PULSE DURATION (s)
Figure 3. Normalized Maximum Transient Thermal Impedance
IDM, PEAK CURRENT (A)
3000
TC = 25oC
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
1000
VGS = 10V
175 - TC
I = I25
150
VGS = 5V
100
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
50
10-5
10-4
10-3
10-2
10-1
10-0
101
t, PULSE WIDTH (s)
Figure 4. Peak Current Capability
©2002 Fairchild Semiconductor Corporation
ISL9N303AP3 / ISL9N303AS3ST / ISL9N303AS3, Rev. C1
ISL9N303AP3 / ISL9N303AS3ST / ISL9N303AS3
Typical Characteristics
150
150
VGS = 10V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
120
90
TJ = 175oC
60
TJ = -55oC
TJ = 25oC
30
VGS = 4.5V
ID, DRAIN CURRENT (A)
ID , DRAIN CURRENT (A)
120
VGS = 3.5V
90
60
VGS = 3V
TC = 25oC
30
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
0
0
1.5
2
2.5
3
0
3.5
0.2
VGS , GATE TO SOURCE VOLTAGE (V)
Figure 5. Transfer Characteristics
0.6
0.8
1
Figure 6. Saturation Characteristics
10
2
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
rDS(ON), DRAIN TO SOURCE
ON RESISTANCE (mΩ)
0.4
VDS , DRAIN TO SOURCE VOLTAGE (V)
8
ID = 75A
6
ID = 24A
4
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
1.5
1
VGS = 10V, ID =75A
0.5
2
2
4
6
8
-80
10
-40
Figure 7. Drain to Source On Resistance vs Gate
Voltage and Drain Current
40
80
120
160
200
Figure 8. Normalized Drain to Source On
Resistance vs Junction Temperature
1.4
1.2
ID = 250µA
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
VGS = VDS, ID = 250µA
1.2
NORMALIZED GATE
THRESHOLD VOLTAGE
0
TJ, JUNCTION TEMPERATURE (oC)
VGS, GATE TO SOURCE VOLTAGE (V)
1
0.8
0.6
0.4
1.1
1.0
0.9
0.2
-80
-40
0
40
80
120
160
200
TJ, JUNCTION TEMPERATURE (oC)
Figure 9. Normalized Gate Threshold Voltage vs
Junction Temperature
©2002 Fairchild Semiconductor Corporation
-80
-40
0
40
80
120
160
200
TJ , JUNCTION TEMPERATURE (oC)
Figure 10. Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
ISL9N303AP3 / ISL9N303AS3ST / ISL9N303AS3, Rev. C1
ISL9N303AP3 / ISL9N303AS3ST / ISL9N303AS3
Typical Characteristics
10
VGS , GATE TO SOURCE VOLTAGE (V)
10000
C, CAPACITANCE (pF)
CISS = CGS + CGD
COSS ≅ CDS + CGD
CRSS = CGD
1000
VGS = 0V, f = 1MHz
300
0.1
VDD = 15V
8
6
4
WAVEFORMS IN
DESCENDING ORDER:
ID = 75A
ID = 10A
2
0
1
10
30
0
50
100
Qg, GATE CHARGE (nC)
VDS , DRAIN TO SOURCE VOLTAGE (V)
Figure 11. Capacitance vs Drain to Source
Voltage
Figure 12. Gate Charge Waveforms for Constant
Gate Currents
800
500
VGS = 10V, VDD = 15V, ID = 24A
VGS = 4.5V, VDD = 15V, ID = 24A
400
tr
SWITCHING TIME (ns)
SWITCHING TIME (ns)
150
td(OFF)
300
tf
200
td(ON)
600
td(OFF)
400
tf
200
tr
100
td(ON)
0
0
0
10
20
30
40
0
50
RGS, GATE TO SOURCE RESISTANCE (Ω)
10
20
30
40
50
RGS, GATE TO SOURCE RESISTANCE (Ω)
Figure 13. Switching Time vs Gate Resistance
Figure 14. Switching Time vs Gate Resistance
Test Circuits and Waveforms
VDS
BVDSS
tP
VDS
L
IAS
VDD
VARY tP TO OBTAIN
REQUIRED PEAK IAS
+
RG
VDD
-
VGS
DUT
tP
0V
IAS
0
0.01Ω
tAV
Figure 15. Unclamped Energy Test Circuit
©2002 Fairchild Semiconductor Corporation
Figure 16. Unclamped Energy Waveforms
ISL9N303AP3 / ISL9N303AS3ST / ISL9N303AS3, Rev. C1
ISL9N303AP3 / ISL9N303AS3ST / ISL9N303AS3
Typical Characteristics
VDS
VDD
Qg(TOT)
RL
VDS
VGS = 10V
VGS
Qg(5)
+
VDD
VGS = 5V
VGS
-
VGS = 1V
DUT
0
Ig(REF)
Qg(TH)
Qgs
Qgd
Ig(REF)
0
Figure 17. Gate Charge Test Circuit
Figure 18. Gate Charge Waveforms
VDS
tON
tOFF
td(ON)
td(OFF)
tr
RL
VDS
tf
90%
90%
+
VGS
VDD
-
10%
0
10%
DUT
90%
RGS
VGS
50%
50%
PULSE WIDTH
VGS
0
Figure 19. Switching Time Test Circuit
©2002 Fairchild Semiconductor Corporation
10%
Figure 20. Switching Time Waveforms
ISL9N303AP3 / ISL9N303AS3ST / ISL9N303AS3, Rev. C1
ISL9N303AP3 / ISL9N303AS3ST / ISL9N303AS3
Test Circuits and Waveforms (Continued)
P
DM
(T
–T )
JM
A
= ----------------------------Z
θJA
(EQ. 1)
In using surface mount devices such as the TO-263
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
power dissipation ratings. Precise determination of PDM is
complex and influenced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
80
RθJA = 26.51+ 19.84/(0.262+Area)
60
RθJA (oC/W)
The maximum rated junction temperature, TJM, and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, PDM, in an
application.
Therefore the application’s ambient
temperature, TA (oC), and thermal resistance RθJA (oC/W)
must be reviewed to ensure that TJM is never exceeded.
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
40
20
0.1
1
10
AREA, TOP COPPER AREA (in2)
Figure 21. Thermal Resistance vs Mounting
Pad Area
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 21
defines the RθJA for the device as a function of the top
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.
Displayed on the curve are RθJA values listed in the
Electrical Specifications table. The points were chosen to
depict the compromise between the copper board area, the
thermal resistance and ultimately the power dissipation,
PDM.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 21 or by calculation using
Equation 2. RθJA is defined as the natural log of the area
times a coefficient added to a constant. The area, in square
inches is the top copper area including the gate and source
pads.
19.84
( 0.262 + Area )
R θ JA = 26.51 + -------------------------------------
©2002 Fairchild Semiconductor Corporation
(EQ. 2)
ISL9N303AP3 / ISL9N303AS3ST / ISL9N303AS3, Rev. C1
ISL9N303AP3 / ISL9N303AS3ST / ISL9N303AS3
Thermal Resistance vs. Mounting Pad Area
rev May 2001
LDRAIN
DPLCAP
10
Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD
RSLC2
5
51
-
Lgate 1 9 5.618e-9
Ldrain 2 5 1.0e-9
Lsource 3 7 1.98e-9
RLDRAIN
RSLC1
51
Ebreak 11 7 17 18 30.6
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1
It 8 17 1
DRAIN
2
5
EVTHRES
+ 19 8
+
LGATE
GATE
1
ESLC
11
+
17
EBREAK 18
-
50
RDRAIN
6
8
ESG
DBREAK
+
.SUBCKT ISL9N303AP3 2 1 3 ;
Ca 12 8 6.3e-9
Cb 15 14 3.8e-9
Cin 6 8 6.7e-9
EVTEMP
RGATE + 18 22
9
20
21
16
DBODY
MWEAK
6
MMED
MSTRO
RLGATE
LSOURCE
CIN
8
SOURCE
3
7
RSOURCE
RLSOURCE
RLgate 1 9 56.1
RLdrain 2 5 15
RLsource 3 7 19.8
Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD
S1A
12
S2A
13
8
14
13
S1B
CA
15
17
18
RVTEMP
S2B
13
CB
19
6
8
VBAT
5
8
EDS
-
IT
14
+
+
EGS
Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 0.9e-3
Rgate 9 20 0.639
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
Rsource 8 7 RsourceMOD 1.8e-3
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
RBREAK
-
+
8
22
RVTHRES
Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*500),3))}
.MODEL DbodyMOD D (IS=8e-11 N=1.06 RS=2.3e-3 TRS1=1.1e-3 TRS2=3e-6
+ CJO=2.6e-9 M=0.43 TT=3e-10 XTI=0.1)
.MODEL DbreakMOD D (RS=0.3 TRS1=1.8e-3 TRS2=-8.9e-6)
.MODEL DplcapMOD D (CJO=2.05e-9 IS=1e-30 N=10 M=0.46)
.MODEL MstroMOD NMOS (VTO=2.16 KP=270 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MmedMOD NMOS (VTO=1.65 KP=20 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=0.639)
.MODEL MweakMOD NMOS (VTO=1.29 KP=0.1 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=6.39 RS=0.1)
.MODEL RbreakMOD RES (TC1=1.05e-3 TC2=-7e-7)
.MODEL RdrainMOD RES (TC1=1e-2 TC2=1.8e-5)
.MODEL RSLCMOD RES (TC1=3.5e-4 TC2=5e-6)
.MODEL RsourceMOD RES (TC1=1e-3 TC2=1e-6)
.MODEL RvthresMOD RES (TC1=-3e-3 TC2=-11e-6)
.MODEL RvtempMOD RES (TC1=-1.5e-3 TC2=1.4e-6)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-5 VOFF=-4)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-5)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.9 VOFF=0.2)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0.2 VOFF=-0.9)
.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
©2002 Fairchild Semiconductor Corporation
ISL9N303AP3 / ISL9N303AS3ST / ISL9N303AS3, Rev. C1
ISL9N303AP3 / ISL9N303AS3ST / ISL9N303AS3
PSPICE Electrical Model
REV May 20011
template ISL9N303AP3 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl=8e-11,nl=1.06,rs=2.3e-3,trs1=1.1e-3,trs2=3e-6,cjo=2.6e-9,m=0.43,tt=3e-10,xti=0.1)
dp..model dbreakmod = (rs=0.3,trs1=1.8e-3,trs2=-8.9e-6)
dp..model dplcapmod = (cjo=2.05e-9,isl=10e-30,nl=10,m=0.46)
m..model mstrongmod = (type=_n,vto=2.16,kp=270,is=1e-30, tox=1)
m..model mmedmod = (type=_n,vto=1.65,kp=20,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=1.29,kp=0.1,is=1e-30, tox=1,rs=0.1)
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-5,voff=-4)
DPLCAP 5
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-4,voff=-5)
10
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-0.9,voff=0.2)
RSLC1
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0.2,voff=-0.9)
51
c.ca n12 n8 = 6.3e-9
RSLC2
c.cb n15 n14 = 3.8e-9
ISCL
c.cin n6 n8 = 6.7e-9
spe.ebreak n11 n7 n17 n18 = 30.6
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evthres n6 n21 n19 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
RDRAIN
6
8
ESG
EVTHRES
+ 19 8
+
LGATE
GATE
1
EVTEMP
RGATE + 18 22
9
20
21
11
DBODY
MWEAK
EBREAK
+
17
18
-
MMED
MSTRO
CIN
RLDRAIN
16
6
RLGATE
DRAIN
2
DBREAK
50
-
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
LDRAIN
8
LSOURCE
7
SOURCE
3
RSOURCE
RLSOURCE
i.it n8 n17 = 1
S1A
12
l.lgate n1 n9 = 5.618e-9
l.ldrain n2 n5 = 1.0e-9
l.lsource n3 n7 = 1.98e-9
S2A
13
8
14
13
S1B
CA
res.rlgate n1 n9 = 56.1
res.rldrain n2 n5 = 15
res.rlsource n3 n7 = 19.8
RBREAK
15
17
18
RVTEMP
S2B
13
CB
6
8
EGS
-
19
IT
14
+
+
VBAT
5
8
EDS
-
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
+
8
22
RVTHRES
res.rbreak n17 n18 = 1, tc1=1.05e-3,tc2=-7e-7
res.rdrain n50 n16 = 0.9e-3, tc1=1e-2,tc2=1.8e-5
res.rgate n9 n20 = 0.639
res.rslc1 n5 n51 = 1e-6, tc1=3.5e-4,tc2=5e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 1.8e-3, tc1=1e-3,tc2=1e-6
res.rvthres n22 n8 = 1, tc1=-3e-3,tc2=-11e-6
res.rvtemp n18 n19 = 1, tc1=-1.5e-3,tc2=1.4e-6
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/500))** 3))
}
©2002 Fairchild Semiconductor Corporation
ISL9N303AP3 / ISL9N303AS3ST / ISL9N303AS3, Rev. C1
ISL9N303AP3 / ISL9N303AS3ST / ISL9N303AS3
SABER Electrical Model
th
JUNCTION
REV May 2001
ISL9N303AP3
CTHERM1 TH 6 3.9e-3
CTHERM2 6 5 7.1e-3
CTHERM3 5 4 8.7e-3
CTHERM4 4 3 9.6e-3
CTHERM5 3 2 1e-2
CTHERM6 2 TL 2.4e-2
RTHERM1
CTHERM1
6
RTHERM1 TH 6 3.9e-5
RTHERM2 6 5 7.5e-4
RTHERM3 5 4 4.8e-3
RTHERM4 4 3 2.7e-2
RTHERM5 3 2 1.6e-1
RTHERM6 2 TL 3.7e-1
CTHERM2
RTHERM2
5
SABER Thermal Model
SABER thermal model ISL9N303AP3
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 =3.9e-3
ctherm.ctherm2 6 5 =7.1e-3
ctherm.ctherm3 5 4 =8.7e-3
ctherm.ctherm4 4 3 =9.6e-3
ctherm.ctherm5 3 2 =1e-2
ctherm.ctherm6 2 tl =2.4e-2
rtherm.rtherm1 th 6 =3.9e-5
rtherm.rtherm2 6 5 =7.5e-4
rtherm.rtherm3 5 4 =4.8e-3
rtherm.rtherm4 4 3 =2.7e-2
rtherm.rtherm5 3 2 =1.6e-1
rtherm.rtherm6 2 tl =3.7e-1
}
RTHERM3
CTHERM3
4
RTHERM4
CTHERM4
3
RTHERM5
CTHERM5
2
RTHERM6
CTHERM6
tl
©2002 Fairchild Semiconductor Corporation
CASE
ISL9N303AP3 / ISL9N303AS3ST / ISL9N303AS3, Rev. C1
ISL9N303AP3 / ISL9N303AS3ST / ISL9N303AS3
SPICE Thermal Model
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not
intended to be an exhaustive list of all such trademarks.
ACEx™
FACT™
ActiveArray™
FACT Quiet Series™
Bottomless™
FAST®
CoolFET™
FASTr™
CROSSVOLT™ FRFET™
DOME™
GlobalOptoisolator™
EcoSPARK™
GTO™
E2CMOS™
HiSeC™
EnSigna™
I2C™
Across the board. Around the world.™
The Power Franchise™
Programmable Active Droop™
ImpliedDisconnect™
ISOPLANAR™
LittleFET™
MicroFET™
MicroPak™
MICROWIRE™
MSX™
MSXPro™
OCX™
OCXPro™
OPTOLOGIC®
OPTOPLANAR™
PACMAN™
POP™
Power247™
PowerTrench®
QFET™
QS™
QT Optoelectronics™
Quiet Series™
RapidConfigure™
RapidConnect™
SILENT SWITCHER®
SMART START™
SPM™
Stealth™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
TinyLogic™
TruTranslation™
UHC™
UltraFET®
VCX™
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR
CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, or (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or In
Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Obsolete
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. I1