ISL9N7030BLP3, ISL9N7030BLS3ST
Data Sheet
January2002
30V, 0.009 Ohm, 75A, N-Channel Logic
Level UltraFET® Trench Power MOSFETs
This device employs a new advanced trench MOSFET
technology and features low gate charge while maintaining
low on-resistance.
Optimized for switching applications, this device improves
the overall efficiency of DC/DC converters and allows
operation to higher switching frequencies.
Packaging
ISL9N7030BLS3ST
JEDEC TO-263AB
ISL9N7030BLP3
JEDEC TO-220AB
SOURCE
DRAIN
GATE
DRAIN
(FLANGE)
PWM
Optimized
Features
•
•
•
•
•
•
Fast Switching
rDS(ON) = 0.0064Ω (Typ), VGS = 10V
rDS(ON) = 0.010Ω (Typ), VGS = 4.5V
Qg Total 24nC (Typ), VGS = 5V
Qgd (Typ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11nC
CISS (Typ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2600pF
Symbol
D
G
GATE
SOURCE
DRAIN
(FLANGE)
S
Ordering Information
PART NUMBER
Absolute Maximum Ratings
SYMBOL
PACKAGE
BRAND
ISL9N7030BLP3
TO-220AB
7030BL
ISL9N7030BLS3ST
TO-263AB (Tape and Reel)
7030BL
TC = 25oC, Unless Otherwise Specified
ISL9N7030BLP3, ISL9N7030BLS3ST
UNITS
VDSS
Drain to Source Voltage (Note 1)
30
V
VDGR
Drain to Gate Voltage (RGS = 20kΩ) (Note 1)
30
V
Gate to Source Voltage
±20
V
75
48
15
Figure 4
A
A
A
A
100
0.67
W
W/oC
-55 to 175
oC
300
260
oC
oC
VGS
ID
ID
ID
IDM
PD
TJ, TSTG
TL
Tpkg
PARAMETER
Drain Current
Continuous (TC = 25oC, VGS = 10V) (Figure 2)
Continuous (TC = 100oC, VGS = 4.5V) (Figure 2)
Continuous (TC = 25oC, VGS = 10V, RθJA = 43oC/W)
Pulsed Drain Current
Power Dissipation
Derate Above 25oC
Operating and Storage Temperature
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s
Package Body for 10s, See Techbrief TB334
THERMAL SPECIFICATIONS
RθJC
Thermal Resistance Junction to Case, TO-220, TO-263
1.5
oC/W
RθJA
Thermal Resistance Junction to Ambient, TO-220, TO-263
62
oC/W
RθJA
Thermal Resistance Junction to Ambient, TO-263, 1in 2 copper pad area
43
oC/W
NOTE:
1. TJ = 25oC to 150oC.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Product reliability information can be found at http://www.fairchildsemi.com/products/discrete/reliability/index.html
For severe environments, see our Automotive products.
All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.
©2002 Fairchild Semiconductor Corporation
ISL9N7030BLP3, ISL9N7030BLS3ST Rev. B
ISL9N7030BLP3, ISL9N7030BLS3ST
Electrical Specifications
TC = 25oC, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
30
-
-
V
VDS = 25V, VGS = 0V
-
-
1
µA
VDS = 25V, VGS = 0V, TC = 150oC
-
-
250
µA
VGS = ±20V
-
-
±100
nA
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
BVDSS
IDSS
IGSS
ID = 250µA, VGS = 0V (Figure 10)
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250µA (Figure 9
1
-
3
V
Drain to Source On Resistance
rDS(ON)
ID = 75A, VGS = 10V (Figures 7, 8)
-
0.007
0.009
Ω
ID = 48A, VGS = 4.5V (Figure 7)
-
0.010
0.012
Ω
VDD = 15V, ID = 15A
VGS = 4.5V, RGS = 6.2Ω
(Figures 13, 17, 18)
-
-
122
ns
-
15
-
ns
tr
-
67
-
ns
td(OFF)
-
35
-
ns
tf
-
32
-
ns
tOFF
-
-
100
ns
-
-
71
ns
-
8
-
ns
tr
-
40
-
ns
td(OFF)
-
64
-
ns
tf
-
31
-
ns
tOFF
-
-
142
ns
-
45
68
nC
-
24
37
nC
-
2.6
4.0
nC
SWITCHING SPECIFICATIONS (VGS = 4.5V)
Turn-On Time
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
tON
td(ON)
SWITCHING SPECIFICATIONS (VGS = 10V)
Turn-On Time
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
tON
td(ON)
VDD = 15V, ID = 15A,
VGS = 10V, RGS = 6.2Ω,
(Figures 14, 17, 18)
GATE CHARGE SPECIFICATIONS
Total Gate Charge at 10V
Qg(TOT)
VGS = 0V to 10V
Total Gate Charge at 5V
Qg(5)
VGS = 0V to 5V
Threshold Gate Charge
Qg(TH)
VGS = 0V to 1V
VDD = 15V,
ID = 48A,
Ig(REF) = 1.0mA
(Figures 12, 15, 16)
Gate to Source Gate Charge
Qgs
-
7
-
nC
Gate to Drain “Miller” Charge
Qgd
-
8
-
nC
-
2600
-
pF
-
520
-
pF
-
225
-
pF
MIN
TYP
MAX
UNITS
ISD = 48A
-
-
1.25
V
ISD = 20A
-
-
1.0
V
trr
ISD = 48A, dISD/dt = 100A/µs
-
-
26
ns
QRR
ISD = 48A, dISD/dt = 100A/µs
-
-
14
nC
CAPACITANCE SPECIFICATIONS
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
VDS = 15V, VGS = 0V,
f = 1MHz
(Figure 11)
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage
Reverse Recovery Time
Reverse Recovered Charge
©2002 Fairchild Semiconductor Corporation
SYMBOL
VSD
TEST CONDITIONS
ISL9N7030BLP3, ISL9N7030BLS3ST Rev. B
ISL9N7030BLP3, ISL9N7030BLS3ST
Typical Performance Curves
80
1.0
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
1.2
0.8
0.6
0.4
60
VGS = 10V
VGS = 4.5V
40
20
0.2
0
25
0
0
25
50
75
100
125
150
175
50
75
100
125
150
175
TC , CASE TEMPERATURE (oC)
TC , CASE TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
2
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
THERMAL IMPEDANCE
ZθJC, NORMALIZED
1
0.1
PDM
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
SINGLE PULSE
0.01
10-5
10-4
10-3
10-2
10-1
t1
t2
100
101
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
1000
IDM , PEAK CURRENT (A)
TC = 25oC
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
175 - TC
I = I25
150
VGS = 10V
VGS = 5V
100
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
50
10-5
10-4
10-3
10-2
10-1
100
101
t, PULSE WIDTH (s)
FIGURE 4. PEAK CURRENT CAPABILITY
©2002 Fairchild Semiconductor Corporation
ISL9N7030BLP3, ISL9N7030BLS3ST Rev. B
ISL9N7030BLP3, ISL9N7030BLS3ST
Typical Performance Curves
(Continued)
150
TC = 25oC
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
125
ID, DRAIN CURRENT (A)
ID , DRAIN CURRENT (A)
150
100
75
50
TJ = 175oC
TJ = -55oC
TJ = 25oC
25
2
3
VGS = 4.5V
100
75
VGS = 3.5V
50
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
25
0
1
VGS = 3V
0
5
4
0
0.5
VGS , GATE TO SOURCE VOLTAGE (V)
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
rDS(ON), DRAIN TO SOURCE
ON RESISTANCE (mΩ)
15
ID = 75A
10
4
6
8
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
1.5
1.0
VGS = 10V, ID = 75A
0.5
-80
5
2
10
-40
FIGURE 7. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
40
80
120
160
200
FIGURE 8. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
1.2
1.2
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
VGS = VDS, ID = 250µA
NORMALIZED GATE
THRESHOLD VOLTAGE
0
TJ, JUNCTION TEMPERATURE (oC)
VGS, GATE TO SOURCE VOLTAGE (V)
1.0
0.8
0.6
0.4
-80
2.0
2.0
20
ID = 14A
1.5
FIGURE 6. SATURATION CHARACTERISTICS
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TC = 25oC
ID = 50A
1.0
VDS , DRAIN TO SOURCE VOLTAGE (V)
FIGURE 5. TRANSFER CHARACTERISTICS
25
VGS = 10V
125
-40
0
40
80
120
160
200
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 9. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
©2002 Fairchild Semiconductor Corporation
ID = 250µA
1.1
1.0
0.9
-80
-40
0
40
80
120
160
200
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
ISL9N7030BLP3, ISL9N7030BLS3ST Rev. B
ISL9N7030BLP3, ISL9N7030BLS3ST
Typical Performance Curves
(Continued)
10
VGS , GATE TO SOURCE VOLTAGE (V)
4000
C, CAPACITANCE (pF)
CISS = CGS + CGD
COSS ≅ CDS + CGD
1000
CRSS = CGD
VGS = 0V, f = 1MHz
100
0.1
1
10
VDD = 15V
8
6
4
WAVEFORMS IN
DESCENDING ORDER:
ID = 48A
ID = 14A
2
0
30
0
10
VDS , DRAIN TO SOURCE VOLTAGE (V)
20
30
Qg, GATE CHARGE (nC)
40
50
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
FIGURE 12. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
350
250
VGS = 10V, VDD = 15V, ID = 15A
300
200
tr
150
SWITCHING TIME (ns)
SWITCHING TIME (ns)
VGS = 4.5V, VDD = 15V, ID = 15A
td(OFF)
tf
100
td(ON)
50
250
td(OFF)
200
150
tf
100
tr
50
td(ON)
0
0
0
10
20
30
40
0
50
10
20
30
40
50
RGS, GATE TO SOURCE RESISTANCE (Ω)
RGS, GATE TO SOURCE RESISTANCE (Ω)
FIGURE 13. SWITCHING TIME vs GATE RESISTANCE
FIGURE 14. SWITCHING TIME vs GATE RESISTANCE
Test Circuits and Waveforms
VDS
VDD
RL
Qg(TOT)
VDS
VGS = 10V
VGS
Qg(5)
+
VDD
DUT
Ig(REF)
VGS = 5V
VGS
-
VGS = 1V
0
Qg(TH)
Qgs
Qgd
Ig(REF)
0
FIGURE 15. GATE CHARGE TEST CIRCUIT
©2002 Fairchild Semiconductor Corporation
FIGURE 16. GATE CHARGE WAVEFORMS
ISL9N7030BLP3, ISL9N7030BLS3ST Rev. B
ISL9N7030BLP3, ISL9N7030BLS3ST
Test Circuits and Waveforms
(Continued)
VDS
tON
tOFF
td(ON)
td(OFF)
tr
RL
VDS
tf
90%
90%
+
VGS
VDD
10%
0
-
10%
DUT
90%
RGS
VGS
VGS
0
50%
10%
FIGURE 17. SWITCHING TIME TEST CIRCUIT
50%
PULSE WIDTH
FIGURE 18. SWITCHING TIME WAVEFORM
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM , and the
thermal resistance of the heat dissipating path determines the
maximum allowable device power dissipation, PDM , in an
application. Therefore the application’s ambient temperature,
TA (oC), and thermal resistance RθJA (oC/W) must be reviewed
to ensure that TJM is never exceeded. Equation 1
mathematically represents the relationship and serves as the
basis for establishing the rating of the part.
( T JM – TA )
P DM = -----------------------------Z θJA
(EQ. 1)
In using surface mount devices such as the TO-263
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
power dissipation ratings. Precise determination of PDM is
complex and influenced by many factors:
can be evaluated using the Fairchild device Spice thermal
model or manually utilizing the normalized maximum
transient thermal impedance curve.
Displayed on the curve are RθJA values listed in the Electrical
Specifications table. The points were chosen to depict the
compromise between the copper board area, the thermal
resistance and ultimately the power dissipation, PDM .
Thermal resistances corresponding to other copper areas can
be obtained from Figure 19 or by calculation using Equation 2.
RθJA is defined as the natural log of the area times a coefficient
added to a constant. The area, in square inches is the top
copper area including the gate and source pads.
R
19.84
θJA = 26.51 + --------------------------------------( 0.262 + Area )
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
(EQ. 2)
80
RθJA = 26.51+ 19.84/(0.262+Area)
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 19
defines the RθJA for the device as a function of the top
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse applications
©2002 Fairchild Semiconductor Corporation
RθJA (oC/W)
2. The number of copper layers and the thickness of the board.
60
40
20
0.1
1
10
AREA, TOP COPPER AREA (in2)
FIGURE 19. THERMAL RESISTANCE vs MOUNTING PAD AREA
ISL9N7030BLP3, ISL9N7030BLS3ST Rev. B
ISL9N7030BLP3, ISL9N7030BLS3ST
PSPICE Electrical Model
.SUBCKT ISL9N7030BL 2 1 3 ;
rev Dec2000
CA 12 8 1.5e-9
CB 15 14 1.75e-9
CIN 6 8 2.35e-9
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
LDRAIN
DPLCAP
DRAIN
2
5
10
5
51
ESLC
11
-
RDRAIN
6
8
EVTHRES
+ 19 8
+
LGATE
GATE
1
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
+
50
-
IT 8 17 1
EVTEMP
RGATE + 18 22
9
20
21
EBREAK
17
18
DBODY
-
16
MWEAK
6
MMED
MSTRO
RLGATE
LSOURCE
CIN
8
SOURCE
3
7
RSOURCE
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 2.5e-3
RGATE 9 20 3.4
RLDRAIN 2 5 10
RLGATE 1 9 45.8
RLSOURCE 3 7 14.7
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 2.55e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A
S1B
S2A
S2B
DBREAK
+
RSLC2
ESG
LDRAIN 2 5 1e-9
LGATE 1 9 4.58e-9
LSOURCE 3 7 1.47e-9
RLDRAIN
RSLC1
51
EBREAK 11 7 17 18 32.7
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
RLSOURCE
S1A
12
S2A
14
13
13
8
S1B
CA
17
18
RVTEMP
S2B
13
CB
6
8
EGS
19
-
-
IT
14
+
+
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
RBREAK
15
VBAT
5
8
EDS
-
+
8
22
RVTHRES
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*200),5))}
.MODEL DBODYMOD D (IS = 1.9e-11 N=1.075 RS = 4.2e-3 TRS1 = 9e-4 TRS2 = 1e-6 XTI=2.2 CJO = 1.1e-9 TT = 8e-11 M = 0.49)
.MODEL DBREAKMOD D (RS = 1.7e- 1TRS1 = 1e- 3TRS2 = -8.9e-6)
.MODEL DPLCAPMOD D (CJO = 8.2e-1 0IS = 1e-3 0N = 10 M = 0.45)
.MODEL MMEDMOD NMOS (VTO = 1.9 KP = 3 IS=1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 3.4)
.MODEL MSTROMOD NMOS (VTO = 2.35KP = 90 IS = 1e-30 N= 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.6 KP = 0.05 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 34 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 1e- 3TC2 = -7e-7)
.MODEL RDRAINMOD RES (TC1 = 7e-3 TC2 = 1e-5)
.MODEL RSLCMOD RES (TC1 = 1e-3 TC2 = 1e-6)
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6)
.MODEL RVTHRESMOD RES (TC1 = -2.7e-3 TC2 = -1e-5)
.MODEL RVTEMPMOD RES (TC1 = -1.8e- 3TC2 = 1e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5
.MODEL S1BMOD VSWITCH (RON = 1e-5
.MODEL S2AMOD VSWITCH (RON = 1e-5
.MODEL S2BMOD VSWITCH (RON = 1e-5
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
VON = -4.0 VOFF= -0.8)
VON = -0.8 VOFF= -4.0)
VON = -0.3 VOFF= 0.2)
VON = 0.2 VOFF= -0.3)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
©2002 Fairchild Semiconductor Corporation
ISL9N7030BLP3, ISL9N7030BLS3ST Rev. B
ISL9N7030BLP3, ISL9N7030BLS3ST
SABER Electrical Model
REV Dec 2000
template ISL9N7030BL n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl = 1.9e-11, nl=1.075 , rs = 4.2e-3, trs1 = 9e-4, trs2 = 1e-6, xti=2.2, cjo = 1.1e-9, tt = 8e-11, m = 0.49,)
dp..model dbreakmod = (rs =0.17, trs1 = 1e-3, trs2 = -8.9e-6)
dp..model dplcapmod = (cjo = 8.2e-10, isl=10e-30, nl=10, m=0.45)
m..model mmedmod = (type=_n, vto = 1.9, kp=3, is=1e-30, tox=1)
m..model mstrongmod = (type=_n, vto = 2.35, kp = 90, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 1.6, kp = 0.05, is = 1e-30, tox = 1, rs=0.1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -4.0, voff = -0.8)
DPLCAP 5
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -0.8, voff = -4.0)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.3, voff = 0.2)
10
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.2, voff = -0.3)
DRAIN
2
RLDRAIN
RSLC1
51
c.ca n12 n8 = 1.5e-9
c.cb n15 n14 = 1.75e-9
c.cin n6 n8 = 2.35e-9
RSLC2
ISCL
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
RDRAIN
6
8
ESG
i.it n8 n17 = 1
LGATE
GATE
1
EVTHRES
+ 19 8
EVTEMP
RGATE + 18 22
9
20
21
11
DBODY
16
MWEAK
6
EBREAK
+
17
18
MMED
MSTRO
RLGATE
CIN
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
res.rbreak n17 n18 = 1, tc1 = 1e-3, tc2 = -7e-7
res.rdrain n50 n16 = 2.5e-3, tc1 = 7e-3, tc2 = 1e-5
res.rgate n9 n20 = 3.4
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 45.8
res.rlsource n3 n7 = 14.7
res.rslc1 n5 n51= 1e-6, tc1 = 1e-3, tc2 =1e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 2.55e-3, tc1 = 1e-3, tc2 =1e-6
res.rvtemp n18 n19 = 1, tc1 = -1.8e-3, tc2 = -1e-6
res.rvthres n22 n8 = 1, tc1 = -2.7e-3, tc2 = -1e-5
DBREAK
50
+
l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 4.58e-9
l.lsource n3 n7 = 1.47e-9
LDRAIN
-
8
LSOURCE
7
SOURCE
3
RSOURCE
RLSOURCE
S1A
12
S2A
S1B
CA
RBREAK
15
14
13
13
8
17
18
RVTEMP
S2B
13
CB
+
+
6
8
EGS
-
19
-
IT
14
VBAT
5
8
EDS
-
+
8
22
RVTHRES
spe.ebreak n11 n7 n17 n18 = 32.7
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e-6/200))** 5))
}
}
©2002 Fairchild Semiconductor Corporation
ISL9N7030BLP3, ISL9N7030BLS3ST Rev. B
ISL9N7030BLP3, ISL9N7030BLS3ST
SPICE Thermal Model
th
REV 23 Sept 2000
JUNCTION
ISL9N7030BL
CTHERM1 th 6 2.0e-4
CTHERM2 6 5 3.0e-3
CTHERM3 5 4 3.4e-3
CTHERM4 4 3 4.0e-3
CTHERM5 3 2 1.0e-2
CTHERM6 2 tl 5.0e-2
RTHERM1 th 6 1.5e-3
RTHERM2 6 5 5.5e-3
RTHERM3 5 4 5.2e-2
RTHERM4 4 3 3.5e-1
RTHERM5 3 2 3.8e-1
RTHERM6 2 tl 4.1e-1
SABER Thermal Model
CTHERM1
RTHERM1
6
CTHERM2
RTHERM2
5
CTHERM3
RTHERM3
SABER thermal model ISL9N7030BL
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 2.0e-4
ctherm.ctherm2 6 5 = 3.0e-3
ctherm.ctherm3 5 4 = 3.4e-3
ctherm.ctherm4 4 3 = 4.0e-3
ctherm.ctherm5 3 2 = 1.0e-2
ctherm.ctherm6 2 tl = 5.0e-2
rtherm.rtherm1 th 6 = 1.5e-3
rtherm.rtherm2 6 5 = 5.5e-3
rtherm.rtherm3 5 4 = 5.2e-2
rtherm.rtherm4 4 3 = 3.5e-1
rtherm.rtherm5 3 2 = 3.8e-1
rtherm.rtherm6 2 tl = 4.1e-1
}
4
CTHERM4
RTHERM4
3
CTHERM5
RTHERM5
2
CTHERM6
RTHERM6
tl
©2002 Fairchild Semiconductor Corporation
CASE
ISL9N7030BLP3, ISL9N7030BLS3ST Rev. B
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Rev. H4