SFP50N06
SemiWell Semiconductor
N-Channel MOSFET
Features
Symbol
■
Low RDS(on) (0.023 Ω )@VGS=10V
■
Low Gate Charge (Typical 39nC)
Low Crss (Typical 110pF)
Improved dv/dt Capability
100% Avalanche Tested
Maximum Junction Temperature Range (175°C)
■
■
■
■
{
2. Drain
●
◀
1. Gate
{
▲
●
●
{
General Description
This Power MOSFET is produced using SemiWell’s advanced
planar stripe, DMOS technology. This latest technology has been
especially designed to minimize on-state resistance, have a low
gate charge with superior switching performance, and rugged
avalanche characteristics. This Power MOSFET is well suited
for synchronous DC-DC Converters and Power Management in
portable and battery operated products.
3. Source
TO-220
1 2
3
Absolute Maximum Ratings
Symbol
VDSS
ID
Value
Units
Drain to Source Voltage
Parameter
60
V
Continuous Drain Current(@TC = 25°C)
50
A
Continuous Drain Current(@TC = 100°C)
35.2
A
200
A
±20
V
IDM
Drain Current Pulsed
VGS
Gate to Source Voltage
(Note 1)
EAS
Single Pulsed Avalanche Energy
(Note 2)
470
mJ
EAR
Repetitive Avalanche Energy
(Note 1)
13
mJ
IAR
Avalnche Current
(Note 1)
50
A
Peak Diode Recovery dv/dt
(Note 3)
7
V/ns
130
W
dv/dt
PD
TSTG, TJ
TL
Total Power Dissipation(@TC = 25 °C)
Derating Factor above 25 °C
Operating Junction Temperature & Storage Temperature
Maximum Lead Temperature for soldering purpose,
1/8 from Case for 5 seconds.
0.87
W/°C
- 55 ~ 175
°C
300
°C
Thermal Characteristics
Symbol
Parameter
Value
Min.
Typ.
Max.
Units
RθJC
Thermal Resistance, Junction-to-Case
-
-
1.15
°C/W
RθCS
Thermal Resistance, Case to Sink
-
0.5
-
°C/W
RθJA
Thermal Resistance, Junction-to-Ambient
-
-
62.5
°C/W
1/7
December, 2002. Rev. 1.
Copyright@SemiWell Semiconductor Co., Ltd., All rights reserved.
SFP50N06
Electrical Characteristics
Symbol
( TC = 25 °C unless otherwise noted )
Parameter
Test Conditions
Min
Typ
Max
Units
60
-
-
V
Off Characteristics
BVDSS
Drain-Source Breakdown Voltage
VGS = 0V, ID = 250uA
Δ BVDSS/
Δ TJ
Breakdown Voltage Temperature
coefficient
ID = 250uA, referenced to 25 °C
-
0.06
-
V/°C
IDSS
Drain-Source Leakage Current
VDS = 60V, VGS = 0V
-
-
1
uA
IGSS
VDS = 48V, TC = 150 °C
-
-
10
uA
Gate-Source Leakage, Forward
VGS = 20V, VDS = 0V
-
-
100
nA
Gate-source Leakage, Reverse
VGS = -20V, VDS = 0V
-
-
-100
nA
2.0
-
4.0
V
-
0.018
0.023
Ω
-
880
1140
-
430
560
-
110
140
On Characteristics
VGS(th)
Gate Threshold Voltage
VDS = VGS, ID = 250uA
RDS(ON)
Static Drain-Source On-state Resistance
VGS =10 V, ID = 25A
Dynamic Characteristics
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
VGS =0 V, VDS =25V, f = 1MHz
pF
Dynamic Characteristics
td(on)
tr
td(off)
tf
Turn-on Delay Time
VDD =30V, ID =25A, RG =50Ω
Rise Time
Turn-off Delay Time
Fall Time
※ see fig. 13.
(Note 4, 5)
-
60
130
-
185
380
-
75
160
-
60
130
-
39
45
ns
Qg
Total Gate Charge
Qgs
Gate-Source Charge
VDS =48V, VGS =10V, ID =50A
-
9.5
-
Qgd
Gate-Drain Charge(Miller Charge)
※ see fig. 12.
-
13
-
Min.
Typ.
Max.
-
-
50
-
-
200
IS =50A, VGS =0V
-
-
1.5
-
54
-
ns
IS=50A,VGS=0V,dIF/dt=100A/us
-
81
-
nC
(Note 4, 5)
nC
Source-Drain Diode Ratings and Characteristics
Symbol
Parameter
IS
Continuous Source Current
ISM
Pulsed Source Current
VSD
Diode Forward Voltage
trr
Reverse Recovery Time
Qrr
Reverse Recovery Charge
Test Conditions
Integral Reverse p-n Junction
Diode in the MOSFET
※ NOTES
1. Repeativity rating : pulse width limited by junction temperature, δ <1％
2. L = 220uH, IAS =50A, VDD = 25V, RG = 0Ω , Starting TJ = 25°C
3. ISD ≤ 50A, di/dt ≤ 300A/us, VDD ≤ BVDSS, Starting TJ = 25°C
4. Pulse Test : Pulse Width ≤ 300us, Duty Cycle ≤ 2%
5. Essentially independent of operating temperature.
2/7
Unit.
A
V
SFP50N06
Fig 1. On-State Characteristics
Fig 2. Transfer Characteristics
VGS
15.0 V
10.0 V
8.0 V
7.0 V
6.0 V
5.5 V
5.0 V
Bottom : 4.5 V
Top :
ID, Drain Current[A]
2
10
ID, Drain Current [A]
2
10
1
10
o
175 C
1
10
o
25 C
o
-55 C
※ Notes :
1. 250µ s Pulse Test
2. TC = 25℃
※ Notes :
1. VDS = 30V
2. 250µ s Pulse Test
0
10
0
10
-1
10
0
2
1
10
10
4
6
8
10
VGS, Gate-Source Voltage [V]
VDS, Drain-Source Voltage[V]
Fig 4. On State Current vs.
Allowable Case Temperature
Fig 3. On Resistance Variation vs.
Drain Current and Gate Voltage
2
10
60
IDR, Reverse Drain Current[A]
RDS(ON),
Drain to Source on Resistance[mΩ ]
70
50
40
VGS=10V
30
20
VGS=20V
10
o
1
10
o
175 C
o
25 C
※ Notes :
1. VGS = 0V
2. 250µ s Pulse Test
※ Note TJ = 25 C
0
0
0
20
40
60
80
100
120
140
160
180
10
200
0.2
0.4
0.6
ID, Drain Current[ A ]
1.0
1.2
1.4
1.8
12
3000
2000
VGS, Gate-Source Voltage [V]
Ciss=Cgs+Cgd(Cds=shorted)
Coss=Cds+Cgd
Crss=Cgd
2500
※ Notes :
1. VGS = 0V
2. f=1MHz
1500
Ciss
1000
Coss
500
10
VDS = 30V
VDS = 48V
8
6
4
2
Crss
0
1.6
Fig 6. Gate Charge Characteristics
Fig 5. Capacitance Characteristics
Capacitance [pF]
0.8
VSD, Source-Drain voltage[V]
5
10
※ Note : ID = 50A
15
20
25
VDS, Drain-Source Voltage [V]
30
35
0
0
5
10
15
20
25
30
35
40
45
Qg, Total Gate Charge [nC]
3/7
SFP50N06
Fig 7. Breakdown Voltage Variation
vs. Junction Temperature
Fig 8. On-Resistance Variation
vs. Junction Temperature
3.0
RDS(ON), (Normalized)
Drain-Source On-Resistance
BVDSS, (Normalized)
Drain-Source Breakdown Voltage
1.2
1.1
1.0
※ Notes :
1. VGS = 0 V
2. ID = 250 µ A
0.9
0.8
-100
-50
0
50
100
150
2.5
2.0
1.5
1.0
※ Notes :
1. VGS = 10 V
2. ID = 25 A
0.5
0.0
-100
200
-50
0
50
100
150
200
150
175
o
o
TJ, Junction Temperature [ C]
TJ, Junction Temperature [ C]
Fig 10. Maximum Drain Current
vs. Case Temperature
Fig 9. Maximum Safe Operating Area
50
3
10
Operation in This Area
is Limited by R DS(on)
1 ms
ID' Drain Current [A]
ID, Drain Current [A]
40
100 µs
2
10
10 ms
DC
1
10
0
10
※ Notes :
30
20
10
o
1. TC = 25 C
o
2. TJ = 150 C
3. Single Pulse
-1
10
-1
10
0
1
10
0
25
2
10
10
50
VDS, Drain-Source Voltage [V]
75
100
125
o
TC' Case Temperature [ C]
Fig 11. Transient Thermal Response Curve
Zθ JC(t), Thermal Response
10
0
D = 0 .5
※ N o te s :
1 . Z θ J C(t) = 1 .1 5 ℃ /W M a x .
2 . D u ty F a c to r, D = t 1 /t 2
3 . T J M - T C = P D M * Z θ J C(t)
0 .2
10
0 .1
-1
0 .0 5
0 .0 2
0 .0 1
10
s in g le p u ls e
-2
10
-5
10
-4
10
-3
10
-2
10
-1
t 1 , S q u a re W a v e P u ls e D u ra tio n [s e c ]
4/7
10
0
10
1
SFP50N06
Fig. 12. Gate Charge Test Circuit & Waveforms
VGS
Same Type
as DUT
50KΩ
200nF
12V
Qg
10V
300nF
VDS
VGS
Qgs
Qgd
DUT
1mA
Charge
Fig 13. Switching Time Test Circuit & Waveforms
RL
VDS
VDS
90%
VDD
( 0.5 rated V DS )
10V
V
Pulse
Generator
Vin
DUT
RG
10%
tr
td(on)
td(off)
t on
tf
t off
Fig 14. Unclamped Inductive Switching Test Circuit & Waveforms
L
VDS
VDD
ID
BVDSS
1
EAS = ---- LL IAS2 -------------------2
BVDSS -- VDD
BVDSS
IAS
RG
10V
ID (t)
DUT
VDS (t)
VDD
tp
Time
5/7
SFP50N06
Fig. 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms
DUT
+
VDS
_
IS
L
Driver
RG
VGS
VGS
( Driver )
Same Type
as DUT
VDD
• dv/dt controlled by RG
• IS controlled by pulse period
Gate Pulse Width
D = -------------------------Gate Pulse Period
10V
IFM , Body Diode Forward Current
IS
( DUT )
di/dt
IRM
Body Diode Reverse Current
VDS
( DUT )
Body Diode Recovery dv/dt
Vf
Body Diode
Forward Voltage Drop
6/7
VDD
SFP50N06
TO-220 Package Dimension
Dim.
mm
Typ.
Min.
9.7
6.3
9.0
12.8
1.2
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
Max.
10.1
6.7
9.47
13.3
1.4
Inch
Typ.
Min.
0.382
0.248
0.354
0.504
0.047
1.7
2.5
0.067
0.098
3.0
1.25
2.4
5.0
2.2
1.25
0.45
0.6
3.4
1.4
2.7
5.15
2.6
1.55
0.6
1.0
0.118
0.049
0.094
0.197
0.087
0.049
0.018
0.024
0.134
0.055
0.106
0.203
0.102
0.061
0.024
0.039
3.6
Ø
E
B
0.142
H
A
φ
I
F
C
M
L
G
1
D
2
1. Gate
2. Drain
3. Source
3
J
N
K
7/7
Max.
0.398
0.264
0.373
0.524
0.055
O