NEC UPA2452

DATA SHEET
MOS FIELD EFFECT TRANSISTOR
µ PA2452
N-CHANNEL MOS FIELD EFFECT TRANSISTOR
FOR SWITCHING
6
2
5
3
4
2.0±0.1
0.5±0.1 0.5±0.1
excellent switching characteristics, and is suitable for
applications such as power switch of portable machine and
so on.
1
0.25 +0.1
-0.05
The µ PA2452 is a switching device which can be driven
directly by a 2.5 V power source.
This µ PA2452 features a low on-state resistance and
1.85±0.1
PACKAGE DRAWING (Unit: mm)
DESCRIPTION
0.8 MAX.
4.4±0.1
5.0±0.1
0.145±0.05
FEATURES
• 2.5 V drive available
• Low on-state resistance
RDS(on)1 = 17.5 mΩ TYP. (VGS = 4.5 V, ID = 4.0 A)
RDS(on)2 = 18.5 mΩ TYP. (VGS = 4.0 V, ID = 4.0 A)
RDS(on)3 = 21.0 mΩ TYP. (VGS = 3.1 V, ID = 4.0 A)
RDS(on)4 = 25.0 mΩ TYP. (VGS = 2.5 V, ID = 4.0 A)
• Built-in G-S protection diode against ESD
0.05 +0
-0.05
7
(1.45)
(0.9)
ORDERING INFORMATION
(0.15)
(3.05)
PART NUMBER
PACKAGE
µ PA2452TL
6PIN HWSON (4521)
(0.50)
Each lead has same dimensions
5,6: Source 2
1,2: Source 1
4: Gate 2
3: Gate 1
7: Drain
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)
Drain to Source Voltage (VGS = 0 V)
VDSS
24.0
V
Gate to Source Voltage (VDS = 0 V)
VGSS
±12.0
V
ID(DC)
±7.8
A
Drain Current (DC)
Note1
Note2
ID(pulse)
±80.0
A
Note1
PT1
2.5
W
Total Power Dissipation (2 units) Note3
PT2
0.7
W
Drain Current (pulse)
Total Power Dissipation (2 units)
Channel Temperature
Tch
150
°C
Storage Temperature
Tstg
−55 to +150
°C
EQUIVALENT CIRCUIT
Drain1
Gate1
Drain2
Body
Diode
Gate2
Gate
Protection
Diode
Source1
Body
Diode
Gate
Protection
Diode
Source2
2
Notes 1. Mounted on ceramic substrate of 50 cm x 1.1 mm
2. PW ≤ 10 µs, Duty Cycle ≤ 1%
2
3. Mounted on FR-4 board of 50 cm x 1.6 mm
Remark The diode connected between the gate and source of the transistor serves as a protector against ESD.
When this device actually used, an additional protection circuit is externally required if a voltage exceeding
the rated voltage may be applied to this device.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. G16272EJ1V0DS00 (1st edition)
Date Published October 2003 NS CP(K)
Printed in Japan
2003
µ PA2452
ELECTRICAL CHARACTERISTICS (TA = 25°C)
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Zero Gate Voltage Drain Current
IDSS
VDS = 24.0 V, VGS = 0 V
10.0
µA
Gate Leakage Current
IGSS
VGS = ±12.0 V, VDS = 0 V
±10.0
µA
VGS(off)
VDS = 10.0 V, ID = 1.0 mA
1.5
V
Gate Cut-off Voltage
Forward Transfer Admittance
Note
Drain to Source On-state Resistance
Note
0.5
0. 7
| yfs |
VDS = 10.0 V, ID = 4.0 A
3
RDS(on)1
VGS = 4.5 V, ID = 4.0 A
12.0
17.5
21.5
mΩ
RDS(on)2
VGS = 4.0 V, ID = 4.0 A
12.5
18.5
22.5
mΩ
RDS(on)3
VGS = 3.1 V, ID = 4.0 A
15.8
21.0
26.5
mΩ
RDS(on)4
VGS = 2.5 V, ID = 4.0 A
16.8
25.0
30.0
mΩ
S
Input Capacitance
Ciss
VDS = 10.0 V
390
pF
Output Capacitance
Coss
VGS = 0 V
130
pF
Reverse Transfer Capacitance
Crss
f = 1.0 MHz
90
pF
Turn-on Delay Time
td(on)
VDD = 20.0 V
20
ns
ID = 4.0 A
120
ns
td(off)
VGS = 4.0 V
180
ns
tf
RG = 6.0 Ω
210
ns
Rise Time
tr
Turn-off Delay Time
Fall Time
Total Gate Charge
QG
VDD = 20.0 V
6.5
nC
Gate to Source Charge
QGS
VGS = 4.0 V
1.0
nC
QGD
ID = 7.8 A
3.0
nC
VF(S-D)
IF = 7.8 A, VGS = 0 V
0.8
V
Reverse Recovery Time
trr
IF = 7.8 A, VGS = 0 V
210
ns
Reverse Recovery Charge
Qrr
di/dt = 100 A/µs
330
nC
Gate to Drain Charge
Body Diode Forward Voltage
Note
Note Pulsed: PW ≤ 350 µs, Duty Cycle ≤ 2%
TEST CIRCUIT 1 SWITCHING TIME
TEST CIRCUIT 2 GATE CHARGE
D.U.T.
D.U.T.
VGS
RL
VGS
RG
PG.
Wave Form
VDD
0
VGS
10%
PG.
90%
τ
τ = 1 µs
Duty Cycle ≤ 1%
2
90%
VDS
VDS
10%
0
10%
Wave Form
td(on)
tr
ton
RL
50 Ω
VDD
90%
VDS
VGS
0
IG = 2 mA
td(off)
tf
toff
Data Sheet G16272EJ1V0DS
µ PA2452
TOTAL POWER DISSIPATION vs.
AMBIENT TEMPERATURE
120
3
PT - Total Power Dissipation - W
dT - Percentage of Rated Power - %
DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA
100
80
60
40
20
Mounted on ceramic board of
50 cm2 x 1.1 mm, 2 units
2.5
2
Mounted on FR-4 board of
50 cm2 x 1.6 mm, 2 units
1.5
1
0.5
0
0
0
25
50
75
100
125
150
0
175
25
50
75
100
125
150
175
TA - Ambient Temperature - °C
TA - Ambient Temperature - °C
FORWARD BIAS SAFE OPERATING AREA
1000
100
100 µs
10
ID(DC)
1 ms
1
10 ms
DC (2 units)
0.1
100 ms
Single pulse
Mounted on ceramic board of
50 cm2 x 1.1 mm
0.01
0.1
1
10
100
VDS - Drain to Source Voltage - V
TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH
rth(ch-A) - Transient Thermal Resistance - °C/W
ID - Drain Current - A
PW = 10 µs
ID(pulse)
RDS(on) Limited
(at VGS = 4.5 V)
1000
Mounted on FR-4 board of
50 cm2 x 1.6 mm
100
Mounted on ceramic board of
50 cm2 x 1.1 mm
10
1
Single pulse
PD (FET1) : PD (FET2) = 1:1
0.1
1m
10 m
100 m
1
10
100
1000
PW - Pulse Width - s
Data Sheet G16272EJ1V0DS
3
µ PA2452
DRAIN CURRENT vs.
DRAIN TO SOURCE VOLTAGE
FORWARD TRANSFER CHARACTERISTICS
50
100
VDS =10.0 V
Pulsed
VGS = 4.5 V
4.0 V
40
10
ID - Drain Current - A
ID - Drain Current - A
Pulsed
3.1 V
30
2.5 V
20
10
1
TA = 125°C
75°C
25°C
−25°C
0.1
0.01
0.001
0.0001
0
0
0.4
0.8
1.2
0
1.6
GATE CUT-OFF VOLTAGE vs.
CHANNEL TEMPERATURE
| yfs | - Forward Transfer Admittance - S
VGS(off) - Gate Cut-off Voltage - V
VDS = 10.0 V
ID = 1.0 mA
0.8
0.6
0.4
0.2
0
50
100
150
VDS = 10.0 V
Pulsed
1
TA = −25°C
25°C
75°C
125°C
0.1
0.01
0.01
0.1
Pulsed
VGS = 2.5 V
3.1 V
4.0 V
4.5 V
20
10
0.1
1
10
100
10
50
ID = 4.0 A
Pulsed
40
30
20
10
0
0
2
4
6
8
10
VGS - Gate to Source Voltage - V
ID - Drain Current - A
4
1
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
GATE TO SOURCE VOLTAGE
RDS(on) - Drain to Source On-state Resistance - mΩ
RDS(on) - Drain to Source On-state Resistance - mΩ
50
0
0.01
2.5
ID - Drain Current - A
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
DRAIN CURRENT
30
2
10
Tch - Channel Temperature - °C
40
1.5
FORWARD TRANSFER ADMITTANCE vs.
DRAIN CURRENT
1
0
1
VGS - Gate to Source Voltage - V
VDS - Drain to Source Voltage - V
-50
0.5
Data Sheet G16272EJ1V0DS
12
µ PA2452
CAPACITANCE vs. DRAIN TO SOURCE VOLTAGE
1000
50
ID = 4.0 A
Pulsed
40
Ciss, Coss, Crss - Capacitance - pF
RDS(on) - Drain to Source On-state Resistance - mΩ
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
CHANNEL TEMPERATURE
VGS = 2.5 V
3.1 V
4.0 V
4.5 V
30
20
10
0
Ciss
100
Coss
Crss
VGS = 0 V
f = 1.0 MHz
10
-50
0
50
100
150
0.1
Tch - Channel Temperature - °C
10
100
VDS - Drain to Source Voltage - V
SWITCHING CHARACTERISTICS
DYNAMIC INPUT CHARACTERISTICS
1000
4
VDD = 20.0 V
VGS = 4.0 V
RG = 6.0 Ω
VGS - Gate to Source Voltage - V
td(on), tr, td(off), tf - Switching Time - ns
1
tr
tf
100
td(off)
td(on)
ID = 7.8 A
3
VDD = 5.0 V
12.0 V
20.0 V
2
1
0
10
0.1
1
10
100
0
2
4
6
8
QG - Gate Charge - nC
ID - Drain Current - A
SOURCE TO DRAIN DIODE
FORWARD VOLTAGE
IF - Diode Forward Current - A
100
VGS = 0 V
Pulsed
10
1
0.1
0.01
0.2
0.4
0.6
0.8
1.0
1.2
VF(S-D) - Source to Drain Voltage - V
Data Sheet G16272EJ1V0DS
5
µ PA2452
<Notes for using this device safely>
When you use this device, in order to prevent a customer’s hazard and damage, use it with understanding
the following contents. If used exceeding recommended conditions, there is a possibility of causing failure of
the device and characteristic degradation.
1. When you mount the device on a substrate, carry out within our recommended soldering conditions of infrared
reflow. If mounted exceeding the conditions, the characteristic of a device may be degraded and it may result failure.
2. When you wash the device mounted the substrate, carry out within our recommended conditions. If washed
exceeding the conditions, the characteristic of a device may be degraded and it may result in failure.
3. When you use ultrasonic wave to substrate after the device mounting, prevent from touching a resonance generator
directly. If it touches, the characteristic of a device may be degraded and it may result in failure.
4. Please refer to Figure 1 as an example of the land pattern. Optimize the land pattern in consideration of density,
appearance of solder fillets, common difference, etc in an actual design.
Figure 1. Example of the land pattern
Unit: mm
3.86
0.30
1.16
0.50
2.04
0.83
6
Data Sheet G16272EJ1V0DS
µ PA2452
5. This device is very thin device and should be handled with caution for mechanical stress. The rate of distortion
applied to the device should become below 2000 µε.Note1 If the rate of distortion exceeds 2000 µε, the
characteristic of a device may be degraded and it may result in failure.
Figure 2. Direction of substrate and stress
The substrate that mounted the device is on a stand with a support width of 24 mm.
The device is turned downward. The stress is applied from a top.
Substrate: 33 x 6 mm, t = 0.5 mm, FR-4
The direction of a device:
Stress
Bend
Measurement position
Support width 24 mm
Device
Figure 3. Example of the bend and the rate of distortion
Note2
The rate of distortion - µ ε
6000
5000
4000
3000
2000
Recommended condition
1000
0
0
0.5
1
Bend - mm
Note 1. Definition (written as ε in this document)
ε = (l − l0)/l0
l0: Distance for two arbitrary points before receiving stress.
l: Distance above-mentioned when receiving stress.
2. The relation of the distortion and the bend changes with several conditions, such as a size of substrate and
so on.
Data Sheet G16272EJ1V0DS
7
µ PA2452
• The information in this document is current as of October, 2003. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
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purposes in semiconductor product operation and application examples. The incorporation of these
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responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
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The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
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defined above).
M8E 02. 11-1