NEC UPA2700GR

DATA SHEET
MOS FIELD EFFECT TRANSISTOR
µ PA2700GR
SWITCHING
N-CHANNEL POWER MOS FET
DESCRIPTION
PACKAGE DRAWING (Unit: mm)
The µPA2700GR is N-Channel MOS Field Effect Transistor
8
designed for DC/DC converters and power management
5
1, 2, 3
; Source
4
; Gate
5, 6, 7, 8 ; Drain
applications of notebook computers.
FEATURES
PART NUMBER
PACKAGE
µPA2700GR
Power SOP8
4.4
5.37 MAX.
0.15
0.05 MIN.
ORDERING INFORMATION
6.0 ±0.3
4
0.8
+0.10
–0.05
1.44
1
1.8 MAX.
• Low on-state resistance
RDS(on)1 = 5.3 mΩ MAX. (VGS = 10 V, ID = 9.0 A)
RDS(on)2 = 7.3 mΩ MAX. (VGS = 4.5 V, ID = 9.0 A)
• Low Ciss: Ciss = 2600 pF TYP. (VDS = 10 V, VGS = 0 V)
• Small and surface mount package (Power SOP8)
0.5 ±0.2
0.10
1.27 0.78 MAX.
0.40
+0.10
–0.05
0.12 M
ABSOLUTE MAXIMUM RATINGS (TA = 25°C, All terminals are connected.)
Drain to Source Voltage (VGS = 0 V)
VDSS
30
V
Gate to Source Voltage (VDS = 0 V)
VGSS
±20
V
Drain Current (DC)
ID(DC)
±17
A
ID(pulse)
±68
A
PT
2.0
W
Tch
150
°C
Tstg
–55 to + 150
°C
IAS
17
A
EAS
28.9
mJ
Drain Current (pulse)
Note1
Total Power Dissipation (TA = 25°C)
Channel Temperature
Storage Temperature
Single Avalanche Current
Note3
Single Avalanche Energy
Note3
Note2
EQUIVALENT CIRCUIT
Drain
Body
Diode
Gate
Source
Notes 1. PW ≤ 10 µs, Duty Cycle ≤ 1%
2
2. Mounted on ceramic substrate of 1200 mm x 2.2 mm
3. Starting Tch = 25°C, VDD = 15 V, RG = 25 Ω, L = 100 µH, VGS = 20 → 0 V
Remark
Strong electric field, when exposed to this device, can cause destruction of the gate oxide and ultimately
degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible,
and quickly dissipate it once, when it has occurred.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. G15672EJ2V0DS00 (2nd edition)
Date Published May 2002 NS CP(K)
Printed in Japan
The mark ★ shows major revised points.
©
2002
µPA2700GR
ELECTRICAL CHARACTERISTICS (TA = 25°C, All terminals are connected.)
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
Zero Gate Voltage Drain Current
IDSS
VDS = 30 V, VGS = 0 V
Gate Leakage Current
IGSS
VGS = ±20 V, VDS = 0 V
Gate Cut-off Voltage
Forward Transfer Admittance
Drain to Source On-state Resistance
MIN.
TYP.
MAX.
UNIT
10
µA
±100
nA
2.5
V
VGS(off)
VDS = 10 V, ID = 1 mA
1.5
2.0
| yfs |
VDS = 10 V, ID = 9.0 A
11
21.5
RDS(on)1
VGS = 10 V, ID = 9.0 A
4.2
5.3
mΩ
RDS(on)2
VGS = 4.5 V, ID = 9.0 A
5.5
7.3
mΩ
RDS(on)3
VGS = 4.0 V, ID = 9.0 A
6.3
8.4
mΩ
S
Input Capacitance
Ciss
VDS = 10 V
2600
pF
Output Capacitance
Coss
VGS = 0 V
1000
pF
Reverse Transfer Capacitance
Crss
f = 1 MHz
340
pF
Turn-on Delay Time
td(on)
VDD = 15 V, ID = 9.0 A
20
ns
tr
VGS = 10 V
24
ns
td(off)
RG = 10 Ω
75
ns
22
ns
Rise Time
Turn-off Delay Time
Fall Time
tf
Total Gate Charge
QG
VDD = 15 V
26
nC
Gate to Source Charge
QGS
VGS = 5 V
7
nC
Gate to Drain Charge
QGD
ID = 17 A
11
nC
VF(S-D)
IF = 17 A, VGS = 0 V
0.8
Reverse Recovery Time
trr
IF = 17 A, VGS = 0 V
50
ns
Reverse Recovery Charge
Qrr
di/dt = 100 A/ µs
51
nC
Body Diode Forward Voltage
TEST CIRCUIT 1 AVALANCHE CAPABILITY
D.U.T.
RG = 25 Ω
PG.
VGS = 20 → 0 V
V
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
L
50 Ω
1.2
VGS
RL
Wave Form
RG
PG.
VDD
VGS
0
VGS
10%
90%
VDD
VDS
90%
BVDSS
IAS
VDS
VDS
ID
Starting Tch
τ
τ = 1 µs
Duty Cycle ≤ 1%
TEST CIRCUIT 3 GATE CHARGE
2
10%
0
10%
Wave Form
VDD
PG.
90%
VDS
VGS
0
D.U.T.
IG = 2 mA
RL
50 Ω
VDD
Data Sheet G15672EJ2V0DS
td(on)
tr
ton
td(off)
tf
toff
µPA2700GR
TYPICAL CHARACTERISTICS (TA = 25°C)
★
DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA
TOTAL POWER DISSIPATION vs.
AMBIENT TEMPERATURE
2.8
PT - Total Power Dissipation - W
dT - Percentage of Rated Power - %
120
100
80
60
40
20
0
20
40
60
80
100
120 140
Mounted on ceramic
substrate of
1200 mm2 ×2.2 mm
2.4
2.0
1.6
1.2
0.8
0.4
0
160
0
TA - Ambient Temperature - ˚C
20
40
60
80
100 120 140
160
TA - Ambient Temperature - ˚C
FORWARD BIAS SAFE OPERATING AREA
100
ID(pulse) = 68 A
PW
10
d
ite )
im V
) L 10
n
o
S( S =
RD (VG
PW
PW
=
Po
Lim we
ite r Di
d s
=
=
1
m
s
10
m
s
10
0
Remark Mounted on ceramic substrate of
m
2
s
sip
1
1200 mm x 2.2 mm
at
ion
0.1
TA = 25˚C
Single Pulse
0.01
0.01
0.1
1
10
100
VDS - Drain to Source Voltage - V
TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH
100
rth(t) - Transient Thermal Resistance - ˚C/ W
ID - Drain Current - A
ID(DC) = 17 A
Rth(ch-A) = 62.5˚C/W
10
1
0.1
0.001
Mounted on ceramic substrate of
1200 mm 2 × 2.2 mm
Single Pulse
Channel to Ambient
0.01
0.1
1
10
PW - Pulse Width - s
Data Sheet G15672EJ2V0DS
100
1000
3
µPA2700GR
DRAIN CURRENT vs.
DRAIN TO SOURCE VOLTAGE
FORWARD TRANSFER CHARACTERISTICS
100
80
Pulsed
Pulsed
70
ID - Drain Current - A
ID - Drain Current - A
VGS = 10 V
10
TA = 150˚C
75˚C
25˚C
−25˚C
1
0.1
60
4.5 V
50
4.0 V
40
30
20
10
0.01
0
1
2
VDS = 10 V
4
5
3
0
0.0
100
VDS = 10 V
Pulsed
TA = −25˚C
25˚C
75˚C
150˚C
10
1
0.1
0.1
1
10
100
RDS(on) - Drain to Source On-state Resistance - mΩ
ID - Drain Current - A
4
15
10
5
ID = 9.0 A
0
0
Pulsed
12
10
8
VGS = 4.0 V
6
4.5 V
10 V
2
0
0.1
1
10
5
10
15
20
VGS - Gate to Source Voltage - V
GATE TO SOURCE CUT-OFF VOLTAGE vs.
CHANNEL TEMPERATURE
14
4
0.2
0.4
0.6
VDS - Drain to Source Voltage - V
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
GATE TO SOURCE VOLTAGE
20
Pulsed
DRAIN TO SOURCE ON-STATE
RESISTANCE vs. DRAIN CURRENT
100
VGS(off) - Gate to Source Cut-off Voltage - V
| yfs | - Forward Transfer Admittance - S
FORWARD TRANSFER ADMITTANCE vs.
DRAIN CURRENT
RDS(on) - Drain to Source On-state Resistance - mΩ
VGS - Gate to Source Voltage - V
3
VDS = 10 V
ID = 1 mA
2
1
0
−50 −25
ID - Drain Current - A
0
25
50
75
100 125 150
Tch - Channel Temperature - ˚C
Data Sheet G15672EJ2V0DS
µPA2700GR
SOURCE TO DRAIN DIODE
FORWARD VOLTAGE
20
100
ISD - Diode Forward Current - A
Pulsed
15
10
VGS = 4 V
4.5 V
10 V
5
0
−50
Pulsed
VGS = 0 V
10
1
0.1
0.01
−25
0
25
50
75
100 125
0
150
0.2
CAPACITANCE vs.
DRAIN TO SOURCE VOLTAGE
1.0
0.8
1.2
1.4
SWITCHING CHARACTERISTICS
td(on), tr, td(off), tf - Switching Time - ns
Ciss
1000
Coss
Crss
100
VGS = 0 V
f = 1 MHz
10
0.1
1
10
td(off)
100
tr
tf
td(on)
10
VDD = 15 V
VGS = 10 V
RG = 10 Ω
1
0.1
100
DYNAMIC INPUT/OUTPUT CHARACTERISTICS
10
1
10
100
40
VDS - Drain to Source Voltage - V
di/dt = 100 A/ µ s
VGS = 0 V
100
1
0.1
100
ID - Drain Current - A
REVERSE RECOVERY TIME vs.
DRAIN CURRENT
1000
10
1
VDS - Drain to Source Voltage - V
trr - Reverse Recovery Time - ns
0.6
1000
10000
Ciss, Coss, Crss - Capacitance - pF
0.4
VSD - Source to Drain Voltage - V
Tch - Channel Temperature - ˚C
8
35
7
VGS
VDD = 24 V
15 V
6V
30
25
6
5
20
4
15
3
10
2
VDS
5
1
ID = 17 A
0
0
ID - Drain Current - A
4
8
12
16
20
24
28
32
36
VGS - Gate to Source Voltage - V
RDS(on) - Drain to Source On-state Resistance - mΩ
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
CHANNEL TEMPERATURE
0
40
QG - Gate Charge - nC
Data Sheet G15672EJ2V0DS
5
µPA2700GR
[MEMO]
6
Data Sheet G15672EJ2V0DS
µPA2700GR
[MEMO]
Data Sheet G15672EJ2V0DS
7
µPA2700GR
• The information in this document is current as of May, 2002. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
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third parties by or arising from the use of NEC semiconductor products listed in this document or any other
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• Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
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responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
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agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
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M8E 00. 4