DATA SHEET MOS FIELD EFFECT TRANSISTOR µPA1728 SWITCHING N-CHANNEL POWER MOS FET DESCRIPTION PACKAGE DRAWING (Unit: mm) The µPA1728 is N-Channel MOS Field Effect Transistor designed for high current switching applications. 8 5 1, 2, 3 ; Source 4 ; Gate 5, 6, 7, 8 ; Drain FEATURES • Single chip type • Low on-state resistance RDS(on)1 = 19 mΩ TYP. (VGS = 10 V, ID = 4.5 A) RDS(on)2 = 23 mΩ TYP. (VGS = 4.5 V, ID = 4.5 A) RDS(on)3 = 24 mΩ TYP. (VGS = 4.0 V, ID = 4.5 A) • Low Ciss: Ciss = 1700 pF TYP. • Built-in G-S protection diode • Small and surface mount package (Power SOP8) 6.0 ±0.3 4 4.4 5.37 Max. 0.8 0.05 Min. 0.15 +0.10 –0.05 1.8 Max. 1.44 1 1.27 0.40 0.5 ±0.2 0.10 0.78 Max. +0.10 –0.05 0.12 M ★ ORDERING INFORMATION PART NUMBER PACKAGE µPA1728G Power SOP8 ABSOLUTE MAXIMUM RATINGS (TA = 25°C, All terminals are connected.) Drain to Source Voltage (VGS = 0 V) VDSS 60 V Gate to Source Voltage (VDS = 0 V) VGSS ±20 V Drain Current (DC) ID(DC) ±9 A ID(pulse) ±36 A PT 2.0 W Drain Current (Pulse) Note1 Total Power Dissipation (TA = 25°C) Channel Temperature Storage Temperature Note2 Tch 150 °C Tstg –55 to + 150 °C Single Avalanche Current Note3 IAS 9 A Single Avalanche Energy Note3 EAS 81 mJ EQUIVALENT CIRCUIT Drain Body Diode Gate Gate Protection Diode Source Notes 1. PW ≤ 10 µs, Duty cycle ≤ 1% 2 2. Mounted on ceramic substrate of 1200 mm x 2.2 mm 3. Starting Tch = 25°C, VDD = 30 V, RG = 25 Ω, TGS = 20 → 0 V Remark The diode connected between the gate and source of the transistor serves as a protector against ESD. When this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated voltage may be applied to this device. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. G14321EJ3V0DS00 (3rd edition) Date Published March 2002 NS CP(K) Printed in Japan The mark ★ shows major revised points. © 1999,2000,2001 µPA1728 ELECTRICAL CHARACTERISTICS (TA = 25°C, All terminals are connected.) CHARACTERISTICS SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Zero Gate Voltage Drain Current IDSS VDS = 60 V, VGS = 0 V 10 µA Gate Leakage Current IGSS VGS = ±20 V, VDS = 0 V ±10 µA VGS(off) VDS = 10 V, ID = 1 mA 1.5 2.0 2.5 V 6.0 12 Gate Cut-off Voltage Forward Transfer Admittance Drain to Source On-state Resistance | yfs | VDS = 10 V, ID = 4.5 A RDS(on)1 VGS = 10 V, ID = 4.5 A 19 26 mΩ S RDS(on)2 VGS = 4.5 V, ID = 4.5 A 23 29 mΩ RDS(on)3 VGS = 4.0 V, ID = 4.5 A 24 34 mΩ Input Capacitance Ciss VDS = 10 V 1700 pF Output Capacitance Coss VGS = 0 V 270 pF Reverse Transfer Capacitance Crss f = 1 MHz 130 pF Turn-on Delay Time td(on) VDD = 30 V, ID = 4.5 A 17 ns tr VGS = 10 V 69 ns td(off) RG = 10 Ω 77 ns 31 ns Rise Time Turn-off Delay Time Fall Time tf Total Gate Charge QG VDD = 48 V 31 nC Gate to Source Charge QGS VGS = 10 V 4.4 nC Gate to Drain Charge QGD ID = 9 A 9.1 nC VF(S-D) IF = 9 A, VGS = 0 V 0.82 V Reverse Recovery Time trr IF = 9 A, VGS = 0 V 41 ns Reverse Recovery Charge Qrr di/dt = 100 A/ µs 76 nC Body Diode Forward Voltage TEST CIRCUIT 1 AVALANCHE CAPABILITY TEST CIRCUIT 2 SWITCHING TIME D.U.T. RG = 25 Ω D.U.T. L RL PG. 50 Ω VDD VGS = 20 → 0 V RG PG. VGS VGS Wave Form 0 90% ID VGS 0 ID Starting Tch τ = 1 µs Duty Cycle ≤ 1% TEST CIRCUIT 3 GATE CHARGE D.U.T. 2 IG = 2 mA RL 50 Ω VDD 10% 0 10% Wave Form τ VDD PG. 90% BVDSS VDS ID 90% VDD ID IAS VGS 10% Data Sheet G14321EJ3V0DS tr td(off) td(on) ton tf toff µPA1728 TYPICAL CHARACTERISTICS (TA = 25°C ) DERATING FACTOR OF FORWARD BIAS SAFE OPERATING AREA TOTAL POWER DISSIPATION vs. AMBIENT TEMPERATURE PT - Total Power Dissipation - W dT - Percentage of Rated Power - % 2.8 100 80 60 40 20 0 20 40 60 80 100 120 140 160 Mounted on ceramic substrate of 1200 mm2 × 2.2 mm 2.4 2.0 1.6 1.2 0.8 0.4 0 20 TA - Ambient Temperature - ˚C 40 60 80 100 120 140 160 TA - Ambient Temperature - ˚C FORWARD BIAS SAFE OPERATING AREA 100 d ite ) Lim V ID(pulse) PW 10 1 0.1 0.01 0.1 R tV (a ID(DC) 10 ms 10 0m s 1m s =1 00 µs Po we DC rD iss ipa tio nL im ite d Remark TA = 25˚C Single Pulse 2 Mounted on ceramic substrate of 1200 mm x 2.2 mm 1 10 100 VDS - Drain to Source Voltage - V TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH 1000 rth(t) - Transient Thermal Resistance - ˚C/W ID - Drain Current - A 0 n) (o = 1 DS GS Rth(ch-A) = 62.5˚C/W 100 10 1 0.1 0.01 Mounted on ceramic substrate of 1200 mm2 x 2.2 mm Single Pulse 0.001 10µ 100µ 1m 10 m 100 m 1 10 100 1000 PW - Pulse Width - s Data Sheet G14321EJ3V0DS 3 µPA1728 DRAIN CURRENT vs. DRAIN TO SOURCE VOLTAGE FORWARD TRANSFER CHARACTERISTICS 4.5 V ID - Drain Current - A 10 1 TA = −25˚C 25˚C 75˚C 150˚C 0.1 0.01 | yfs | - Forward Transfer Admittance - S 40 0 1 2 3 VDS = 10 V 4 VGS =10 V 5 20 10 Pulsed 0.4 0.2 0.8 0.6 1.0 VDS - Drain to Source Voltage - V FORWARD TRANSFER ADMITTANCE vs. DRAIN CURRENT DRAIN TO SOURCE ON-STATE RESISTANCE vs. GATE TO SOURCE VOLTAGE 100 VDS = 10 V Pulsed 10 TA = 150˚C 75˚C 25˚C −25˚C 1 0.1 0.01 0.01 0.1 1 10 100 50 Pulsed 40 30 ID = 9 A 20 10 0 0 5 DRAIN TO SOURCE ON-STATE RESISTANCE vs. DRAIN CURRENT 50 3.0 VGS(off) - Gate Cut-off Voltage - V Pulsed 30 VGS =4 V 4.5 V 20 10 V 10 1 10 15 GATE CUT-OFF VOLTAGE vs. CHANNEL TEMPERATURE 40 0 0.1 10 VGS - Gate to Source Voltage - V 100 VDS = 10 V ID = 1 mA 2.5 2.0 1.5 1.0 0.5 0 −50 ID - Drain Current - A 4 4.0 V VGS - Gate to Source Voltage - V ID - Drain Current - A RDS(on) - Drain to Source On-state Resistance - mΩ 30 0 RDS(on) - Drain to Source On-state Resistance - mΩ ID - Drain Current - A 100 Pulsed 0 50 100 Tch - Channel Temperature - ˚C Data Sheet G14321EJ3V0DS 150 SOURCE TO DRAIN DIODE FORWARD VOLTAGE DRAIN TO SOURCE ON-STATE RESISTANCE vs. CHANNEL TEMPERATURE 50 100 Pulsed 40 VGS = 4.0 V 4.5 V 30 VGS = 10 V 20 10 10 VGS = 0 V 1 0.1 ID = 4.5 A 0 −50 0 50 100 Pulsed VGS = 10 V ISD - Diode Forward Current - A RDS(on) - Drain to Source On-state Resistance - mΩ µPA1728 0.01 0 150 VSD - Source to Drain Voltage - V Tch - Channel Temperature - ˚C CAPACITANCE vs. DRAIN TO SOURCE VOLTAGE SWITCHING CHARACTERISTICS 1000 VGS = 0 V f = 1 MHz Ciss 1000 Coss 100 Crss 10 0.1 1 10 td(on), tr, td(off), tf - Switching Time - ns Ciss, Coss, Crss - Capacitance - pF 10000 VDD = 30 V VGS = 10 V RG = 10 Ω tr td(off) 100 tf td(on) 10 1 0.1 100 REVERSE RECOVERY TIME vs. DRAIN CURRENT di/dt = 100 A/ µ s VGS = 0 V 10 12 60 VDS - Drain to Source Voltage - V trr - Reverse Recovery Time - ns 100 DYNAMIC INPUT/OUTPUT CHARACTERISTICS 100 1 0.1 10 1 ID - Drain Current - A VDS - Drain to Source Voltage - V 1000 1.5 1.0 0.5 10 VDD = 48 V 30 V 12 V 40 VGS 6 4 20 2 VDS ID = 9 A 0 1.0 10 100 8 0 5 10 15 20 25 30 35 40 0 QG - Gate Charge - nC IF - Drain Current - A Data Sheet G14321EJ3V0DS 5 µPA1728 SINGLE AVALANCHE ENERGY DERATING FACTOR SINGLE AVALANCHE CURRENT vs. INDUCTIVE LOAD 160 IAS = 9 A EAS 10 = 81 mJ 1 VDD = 30 V RG = 25 Ω VGS = 20 → 0 V 0.1 10 µ 100 µ 120 100 80 60 40 20 1m L - Inductive Load - H 6 VDD = 30 V RG = 25 Ω VGS = 20 → 0 V IAS ≤ 9 A 140 Energy Derating Factor - % IAS - Single Avalanche Current - A 100 10 m 0 25 50 75 100 125 150 Starting Tch - Starting Channel Temperature - ˚C Data Sheet G14321EJ3V0DS µPA1728 [MEMO] Data Sheet G14321EJ3V0DS 7 µPA1728 • The information in this document is current as of March, 2002. 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