DATA SHEET MOS FIELD EFFECT TRANSISTOR µPA1727 SWITCHING N-CHANNEL POWER MOS FET DESCRIPTION PACKAGE DRAWING (Unit: mm) The µPA1727 is N-Channel MOS Field Effect Transistor designed for high current switching applications. 8 5 1, 2, 3 ; Source 4 ; Gate 5, 6, 7, 8 ; Drain FEATURES • Single chip type • Low on-state resistance RDS(on)1 = 14 mΩ TYP. (VGS = 10 V, ID = 5.0 A) RDS(on)2 = 17 mΩ TYP. (VGS = 4.5 V, ID = 5.0 A) RDS(on)3 = 19 mΩ TYP. (VGS = 4.0 V, ID = 5.0 A) • Low Ciss: Ciss = 2400 pF TYP. • Built-in G-S protection diode • Small and surface mount package (Power SOP8) 1.44 PACKAGE µPA1727G Power SOP8 4.4 5.37 Max. 0.15 ORDERING INFORMATION PART NUMBER 6.0 ±0.3 4 0.8 +0.10 –0.05 1.8 Max. 0.05 Min. ★ 1 1.27 0.40 0.5 ±0.2 0.10 0.78 Max. +0.10 –0.05 0.12 M ABSOLUTE MAXIMUM RATINGS (TA = 25°C, All terminals are connected.) Drain to Source Voltage (VGS = 0 V) VDSS 60 V Gate to Source Voltage (VDS = 0 V) VGSS ±20 V Drain Current (DC) ID(DC) ±10 A ID(pulse) ±40 A PT 2.0 W Tch 150 °C Drain Current (Pulse) Note1 Total Power Dissipation (TA = 25°C) Channel Temperature Storage Temperature Note2 Tstg –55 to + 150 °C Single Avalanche Current Note3 IAS 10 A Single Avalanche Energy Note3 EAS 200 mJ EQUIVALENT CIRCUIT Drain Body Diode Gate Gate Protection Diode Source Notes 1. PW ≤ 10 µs, Duty Cycle ≤ 1% 2 2. Mounted on ceramic substrate of 1200 mm x 2.2 mm ch DD G 3. Starting T = 25°C, V = 30 V, R = 25 Ω, VGS = 20 → 0 V Remark The diode connected between the gate and source of the transistor serves as a protector against ESD. When this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated voltage may be applied to this device. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. G14330EJ3V0DS00 (3rd edition) Date Published March 2002 NS CP(K) Printed in Japan The mark ★ shows major revised points. © 1999, 2000, 2001 µPA1727 ELECTRICAL CHARACTERISTICS (TA = 25°C, All terminals are connected.) CHARACTERISTICS SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Zero Gate Voltage Drain Current IDSS VDS = 60 V, VGS = 0 V 10 µA Gate Leakage Current IGSS VGS = ±20 V, VDS = 0 V ±10 µA VGS(off) VDS = 10 V, ID = 1 mA 1.5 2.0 2.5 V | yfs | VDS = 10 V, ID = 5.0 A 8.0 14 RDS(on)1 VGS = 10 V, ID = 5.0 A 14 19 mΩ RDS(on)2 VGS = 4.5 V, ID = 5.0 A 17 22 mΩ RDS(on)3 VGS = 4.0 V, ID = 5.0 A 19 25 mΩ Gate Cut-off Voltage Forward Transfer Admittance Drain to Source On-state Resistance S Input Capacitance Ciss VDS = 10 V 2400 pF Output Capacitance Coss VGS = 0 V 400 pF Reverse Transfer Capacitance Crss f = 1 MHz 200 pF Turn-on Delay Time td(on) VDD = 30 V, ID = 5.0 A 24 ns tr VGS = 10 V 120 ns td(off) RG = 10 Ω 120 ns 70 ns Rise Time Turn-off Delay Time Fall Time tf Total Gate Charge QG VDD = 48 V 45 nC Gate to Source Charge QGS VGS = 10 V 6 nC Gate to Drain Charge QGD ID = 10 A 13 nC VF(S-D) IF = 10 A, VGS = 0 V 0.8 V Reverse Recovery Time trr IF = 10 A, VGS = 0 V 45 ns Reverse Recovery Charge Qrr di/dt = 100 A/ µs 84 nC Body Diode Forward Voltage TEST CIRCUIT 1 AVALANCHE CAPABILITY TEST CIRCUIT 2 SWITCHING TIME D.U.T. RG = 25 Ω D.U.T. L RL PG. 50 Ω VDD VGS = 20 → 0 V RG PG. VGS VGS Wave Form 0 90% ID VGS 0 ID Starting Tch τ = 1 µs Duty Cycle ≤ 1% TEST CIRCUIT 3 GATE CHARGE D.U.T. 2 IG = 2 mA RL 50 Ω VDD 10% 0 10% Wave Form τ VDD PG. 90% BVDSS VDS ID 90% VDD ID IAS VGS 10% Data Sheet G14330EJ3V0DS tr td(off) td(on) ton tf toff µPA1727 TYPICAL CHARACTERISTICS (TA = 25°C, All terminals are connected.) TOTAL POWER DISSIPATION vs. CASE TEMPERATURE 2.8 PT - Total Power Dissipation - W dT - Percentage of Rated Power - % DERATING FACTOR OF FORWARD BIAS SAFE OPERATING AREA 100 80 60 40 20 Mounted on ceramic substrate of 1200 mm2 x 2.2 mm 2.4 2.0 1.6 1.2 0.8 0.4 0 0 20 40 60 80 0 100 120 140 160 20 TC - Case Temperature - °C 40 60 80 100 120 140 160 TC - Case Temperature - °C FORWARD BIAS SAFE OPERATING AREA 100 ) (on 10 R VG (at 1 PW ID(pulse) 10 ms ID(DC) 1m s =1 00 µs 10 0m s DC Po Lim wer ite Diss d ipa tio n 0.1 0.01 0.1 Remark TA = 25˚C Single Pulse 2 1 10 Mounted on ceramic substrate of 1200 mm × 2.2 mm 100 VDS - Drain to Source Voltage - V TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH rth(t) - Transient Thermal Resistance - ˚C/W ID - Drain Current - A DS d ite ) Lim 10 V = S 1000 100 Rth(ch-A) = 62.5˚C/W 10 1 0.1 0.01 10µ Mounted on ceramic substrate of 1200 mm2 x 2.2 mm Single Pulse, TA = 25˚C 100µ 1m 10m 100m 1 10 100 1000 PW - Pulse Width - s Data Sheet G14330EJ3V0DS 3 µPA1727 FORWARD TRANSFER CHARACTERISTICS DRAIN CURRENT vs. DRAIN TO SOURCE VOLTAGE 100 Pulsed 10 ID - Drain Current - A ID - Drain Current - A 50 TA = 150˚C 75˚C 25˚C −25˚C 1 0.1 VGS = 4.5V 40 VGS = 10 V 30 VGS = 4V 20 10 0 2 3 RDS(on) - Drain to Source On-state Resistance - mΩ 0 0.6 0.8 1.0 FORWARD TRANSFER ADMITTANCE vs. DRAIN CURRENT DRAIN TO SOURCE ON-STATE RESISTANCE vs. GATE TO SOURCE VOLTAGE 10 TA = 150˚C 75˚C 25˚C −25˚C 1 0.1 0.01 0.01 0.1 1 10 100 40 40 30 VGS = 4 V VGS = 4.5 V 1 VGS = 10 V 10 ID = 10 A 20 10 0 0 5 10 15 VGS - Gate to Source Voltage - V GATE TO SOURCE CUT-OFF VOLTAGE vs. CHANNEL TEMPERATURE Pulsed 20 Pulsed 30 DRAIN TO SOURCE ON-STATE RESISTANCE vs. DRAIN CURRENT 0 0.1 0.4 VDS - Drain to Source Voltage - V VDS = 10 V Pulsed 10 0.2 VGS - Gate to Source Voltage - V ID - Drain Current - A 4 0 RDS(on) - Drain to Source On-state Resistance - mΩ 100 1 100 VGS(off) - Gate to Source Cut-off Voltage - V | yfs | - Forward Transfer Admittance - S 0.01 Pulsed VDS = 10 V 4 5 3.0 VDS = 10 V ID = 1 mA 2.5 2.0 1.5 1.0 0.5 0 −50 ID - Drain Current - A 0 50 100 Tch - Channel Temperature - ˚C Data Sheet G14330EJ3V0DS 150 DRAIN TO SOURCE ON-STATE RESISTANCE vs. CHANNEL TEMPERATURE 100 VGS = 4.5 V 30 VGS = 4.0 V 20 VGS = 10 V 10 0 ID = 5 A −50 0 50 100 VGS = 0 V 1 0.1 1.5 1.0 0.5 Tch - Channel Temperature - ˚C VSD - Source to Drain Voltage - V CAPACITANCE vs. DRAIN TO SOURCE VOLTAGE SWITCHING CHARACTERISTICS VGS = 0 V f = 1 MHz Ciss Coss 100 Crss 1 10 1000 tr td(off) 100 tf td(on) 10 VDD = 30 V VGS = 10 V RG = 10 Ω 1 0.1 100 1 10 100 VDS - Drain to Source Voltage - V ID - Drain Current - A REVERSE RECOVERY TIME vs. DRAIN CURRENT DYNAMIC INPUT/OUTPUT CHARACTERISTICS 1000 di/dt = 100 A / µ s VGS = 0 V 100 10 1 0.1 10 0.01 0 150 1000 10 0.1 Pulsed VGS = 10 V 1 10 100 60 12 50 10 VGS 40 VDD = 48 V 30 V 12 V 30 8 6 20 4 10 2 VDS ID = 10 A 0 VGS - Gate to Source Voltage - V 40 td(on), tr, td(off), tf - Switching Time - ns Ciss, Coss, Crss - Capacitance - pF ISD - Diode Forward Current - A 50 10000 trr - Reverse Recovery Time - ns SOURCE TO DRAIN DIODE FORWARD VOLTAGE VDS - Drain to Source Voltage - V RDS(on) - Drain to Source On-state Resistance - mΩ µPA1727 0 0 IF - Drain Current - A 10 20 30 40 50 60 QG - Gate Charge - nC Data Sheet G14330EJ3V0DS 5 µPA1727 SINGLE AVALANCHE ENERGY DERATING FACTOR SINGLE AVALANCHE CURRENT vs. INDUCTIVE LOAD 10 160 EAS IAS = 10 A =2 00 m J 1 0.1 10 µ RG = 25 Ω VDD = 30 V VGS = 20 → 0 V 100 µ VDD = 30 V RG = 25 Ω VGS = 20 → 0 V IAS ≤ 10 A 140 120 100 80 60 40 20 1m L - Inductive Load - H 6 Energy Derating Factor - % IAS - Single Avalanche Current - A 100 10 m 0 25 50 75 100 125 150 Starting Tch - Starting Channel Temperature - ˚C Data Sheet G14330EJ3V0DS µPA1727 [MEMO] Data Sheet G14330EJ3V0DS 7 µPA1727 • The information in this document is current as of March, 2002. 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