N-Channel Logic Level Enhancement Mode Field Effect Transistor NIKO-SEM P01N02LJA J-LEAD8 ( Preliminary) D PRODUCT SUMMARY V(BR)DSS RDS(ON) ID 25V 70mΩ 1.2A 4 :GATE 5,6,7,8 :DRAIN 1,2,3 :SOURCE G S ABSOLUTE MAXIMUM RATINGS (TC = 25 °C Unless Otherwise Noted) PARAMETERS/TEST CONDITIONS Gate-Source Voltage TC = 25 °C Continuous Drain Current Pulsed Drain Current SYMBOL LIMITS UNITS VGS ±15 V 1.2 ID TC = 100 °C 1 1.0 IDM TC = 25 °C Power Dissipation 12 0.6 PD TC = 100 °C Operating Junction & Storage Temperature Range 1 Lead Temperature ( /16” from case for 10 sec.) A W 0.5 Tj, Tstg -55 to 150 TL 275 °C THERMAL RESISTANCE RATINGS THERMAL RESISTANCE SYMBOL TYPICAL MAXIMUM Junction-to-Case RθJC 65 Junction-to-Ambient RθJA 230 UNITS °C / W 1 Pulse width limited by maximum junction temperature. ELECTRICAL CHARACTERISTICS (TC = 25 °C, Unless Otherwise Noted) PARAMETER SYMBOL TEST CONDITIONS LIMITS UNIT MIN TYP MAX STATIC V(BR)DSS VGS = 0V, ID = 250 µA 25 VGS(th) VDS = VGS, ID = 250 µA 0.7 Gate-Body Leakage IGSS VDS = 0V, VGS = ±15V ±250 Zero Gate Voltage Drain Current IDSS VDS = 20V, VGS = 0V 25 VDS = 20V, VGS = 0V, TJ = 125 °C 250 On-State Drain Current1 ID(ON) Drain-Source Breakdown Voltage Gate Threshold Voltage Drain-Source On-State Resistance1 Forward Transconductance1 VDS = 10V, VGS = 10V RDS(ON) gfs 1 1.0 2.5 1.2 V nA µA A VGS = 7V, ID = 1.2A 120 180 VGS = 10V, ID = 1.2A 70 120 VDS = 20V, ID = 1.2A 16 mΩ S AUG-30-2002 N-Channel Logic Level Enhancement Mode Field Effect Transistor NIKO-SEM P01N02LJA J-LEAD8 ( Preliminary) DYNAMIC Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss 85 Qg 11 Total Gate Charge 2 Gate-Source Charge Gate-Drain Charge 2 2 Turn-On Delay Time 2 Rise Time2 Turn-Off Delay Time2 Fall Time2 120 VGS = 0V, VDS = 15V, f = 1MHz pF 100 Qgs VDS = 0.5V(BR)DSS, VGS = 10V, 3.0 Qgd ID = 1A 5.8 td(on) nC 7 tr VDS = 15V, RL = 1Ω 20 td(off) ID ≅ 1A, VGS = 10V, RGS = 50Ω 13 tf nS 19 SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (TC = 25 °C) Continuous Current IS 1.2 Pulsed Current3 ISM 12 Forward Voltage1 VSD Reverse Recovery Time trr Reverse Recovery Charge Qrr IF = IS, VGS = 0V IF = IS, dlF/dt = 100A / µS A 1.3 V 70 nS 0.22 µC 1 Pulse test : Pulse Width ≤ 300 µsec, Duty Cycle ≤ 2％. Independent of operating temperature. 3 Pulse width limited by maximum junction temperature. 2 REMARK: THE PRODUCT MARKED WITH “102B” 2 AUG-30-2002 NIKO-SEM N-Channel Logic Level Enhancement Mode Field Effect Transistor P01N02LJA J-LEAD8 ( Preliminary) J-LEAD8 MECHANICAL DATA Dimension mm Min. A Typ. Max. Dimension 0.50 H mm Min. Typ. 0.10 Max. 0.20 B 0.15 0.3 I C 1.65 1.85 J 0 D 2.00 2.20 2.40 K 0.35 0.45 0.55 E 1.80 2.00 2.20 L 1.80 2.10 2.40 F 0.70 0.90 1.00 M 1.10 N G 3 0.048 0.1 AUG-30-2002