IXYS IXTU01N100D

High Voltage MOSFET
N-Channel, Depletion Mode
IXTP 01N100D
IXTU 01N100D
IXTY 01N100D
VDSS = 1000
V
ID25 = 100 mA
Ω
RDS(on) = 110
Preliminary Data Sheet
Symbol
Test Conditions
Maximum Ratings
VDSX
TJ = 25°C to 150°C
1000
V
VDGX
TJ = 25°C to 150°C
1000
V
VGS
Continuous
± 20
V
VGSM
Transient
± 30
V
IDSS
TC = 25°C; TJ = 25°C to 150°C
100
mA
IDM
TC = 25°C, pulse width limited by TJ
400
mA
PD
TC = 25°C
TA = 25°C
25
1.1
W
W
-55 ... +150
°C
TJM
150
°C
Tstg
-55 ... +150
°C
TJ
TL
1.6 mm (0.063 in.) from case for 10 s
300
°C
TISOL
Plastic case for 10 s (IXTU)
300
°C
Md
Mounting torque
TO-220
1.3 / 10
Nm/lb.
TO-220
TO-251
TO-252
4
0.8
0.8
g
g
g
Weight
TO-220 (IXTP)
G
D (TAB)
DS
TO-251 (IXTU)
G
D
D (TAB)
S
TO-252 (IXTY)
G
S
D (TAB)
Pins: 1 - Gate
2 - Drain
3 - Source TAB - Drain
Symbol
Test Conditions
(TJ = 25°C, unless otherwise specified)
Characteristic Values
min. typ. max.
VDSX
VGS = -10 V, ID = 25 μA
1000
VGS(off)
VDS = 25V, ID = 25 μA
-2.5
IGSS
VGS = ± 20 VDC, VDS = 0
IDSX(off)
VDS = VDSX, VGS = -10 V
RDS(on)
VGS = 0 V, ID = 50 mA
ID(on)
VGS = 0 V, VDS = 25V
© 2006 IXYS All rights reserved
V
TJ = 125°C
Note 1
Note 1
90
100
Features
z
Normally ON mode
z
-5
V
z
±100
nA
z
10
250
μA
μA
110
Ω
mA
Low RDS (on) HDMOSTM process
Rugged polysilicon gate cell structure
Fast switching speed
Applications
z
Level shifting
z
Triggers
z
Solid state relays
z
Current regulators
98809B (01/06)
IXTP 01N100D
Symbol
Test Conditions
Characteristic Values
(TJ = 25°C, unless otherwise specified)
min. typ. max.
gfs
VDS = 50 V; ID = 100 mA
Note1
100
Ciss
Coss
VGS = -10 V, VDS = 25 V, f = 1 MHz
Crss
150
mS
120
pF
25
pF
5
pF
td(on)
VDS = 100 V V, ID = 50 mA
8
ns
tr
VGS = 0 V to -10
6
ns
td(off)
RG
30
ns
51
ns
= 30Ω (External)
tf
RthJC
5
RthCS
TO-220
0.25
Source-Drain Diode
K/W
Pins: 1 - Gate
3 - Source
2 - Drain
TAB - Drain
K/W
Symbol
Test Conditions
Characteristic Values
(TJ = 25°C, unless otherwise specified)
min. typ. max.
VSD
VGS = -10 V, IF = 100 mA
Note1
trr
IF = 0.75 A, -di/dt = 10 A/μs,
VDS = 25 V, VGS = -10V
1.0
TO-220 AD Outline
1.5
V
1.5
μs
TO-251 AA Outline
Note1: Pulse test, t ≤ 300 μs, duty cycle d ≤ 2 %
TO-252 AA Outline
Dim.
Pins: 1 - Gate
3 - Source
A
A1
A2
b
b1
b2
c
c1
D
D1
E
E1
e
e1
H
L
L1
L2
L3
2 - Drain
TAB - Drain
Millimeter
Min. Max.
Inches
Min.
Max.
2.19 2.38
0.89 1.14
0 0.13
0.64 0.89
0.76 1.14
5.21 5.46
0.46 0.58
0.46 0.58
5.97 6.22
4.32 5.21
6.35 6.73
4.32 5.21
2.28 BSC
4.57 BSC
9.40 10.42
0.51 1.02
0.64 1.02
0.89 1.27
2.54 2.92
0.086 0.094
0.035 0.045
0 0.005
0.025 0.035
0.030 0.045
0.205 0.215
0.018 0.023
0.018 0.023
0.235 0.245
0.170 0.205
0.250 0.265
0.170 0.205
0.090 BSC
0.180 BSC
0.370 0.410
0.020 0.040
0.025 0.040
0.035 0.050
0.100 0.115
Pins: 1 - Gate
3 - Source
2 - Drain
TAB - Drain
Dim.
Millimeter
Min.
Max.
Inches
Min. Max.
A
A1
2.19
0.89
2.38
1.14
.086
0.35
.094
.045
b
b1
b2
0.64
0.76
5.21
0.89
1.14
5.46
.025
.030
.205
.035
.045
.215
c
c1
0.46
0.46
0.58
0.58
.018
.018
.023
.023
D
5.97
6.22
.235
.245
E
e
e1
6.35
2.28
4.57
6.73
BSC
BSC
.250
.090
.180
.265
BSC
BSC
H
17.02
17.78
.670
.700
L
L1
L2
L3
8.89
1.91
0.89
1.15
9.65
2.28
1.27
1.52
.350
.075
.035
.045
.380
.090
.050
.060
IXYS reserves the right to change limits, test conditions, and dimensions.
IXYS MOSFETs and IGBTs are covered by
one or moreof the following U.S. patents:
4,835,592
4,850,072
4,881,106
4,931,844
5,017,508
5,034,796
5,049,961
5,063,307
5,187,117
5,237,481
5,381,025
5,486,715
6,162,665
6,259,123 B1
6,306,728 B1
6,404,065 B1
6,534,343
6,583,505
6,683,344
6,710,405B2
6,710,463
6,727,585
6,759,692