ETC 2SK3430-ZJ

DATA SHEET
MOS FIELD EFFECT TRANSISTOR
2SK3430
SWITCHING
N-CHANNEL POWER MOS FET
INDUSTRIAL USE
★
DESCRIPTION
ORDERING INFORMATION
The 2SK3430 is N-channel MOS Field Effect Transistor
PART NUMBER
PACKAGE
2SK3430
TO-220AB
2SK3430-S
TO-262
2SK3430-ZJ
TO-263
designed for high current switching applications.
FEATURES
• Super low on-state resistance:
2SK3430-Z
RDS(on)1 = 7.3 mΩ MAX. (VGS = 10 V, ID = 40 A)
TO--220SMD
Note
Note TO-220SMD package is produced only
RDS(on)2 = 15 mΩ MAX. (VGS = 4 V, ID = 40 A)
in Japan.
• Low Ciss: Ciss = 2800 pF TYP.
(TO-220AB)
• Built-in gate protection diode
ABSOLUTE MAXIMUM RATINGS (T A = 25°C)
Drain to Source Voltage (VGS = 0 V)
VDSS
40
V
Gate to Source Voltage (VDS = 0 V)
VGSS
±20
V
Drain Current (DC) (TC = 25°C)
ID(DC)
±80
A
ID(pulse)
Note1
±200
A
Total Power Dissipation (TC = 25°C)
PT
84
W
Total Power Dissipation (TA = 25°C)
PT
1.5
W
Channel Temperature
Tch
150
°C
Tstg
–55 to +150
°C
IAS
37
A
EAS
137
mJ
Drain Current (pulse)
Storage Temperature
Single Avalanche Current
Single Avalanche Energy
Note2
Note2
(TO-262)
(TO-263 ,TO-220SMD)
Notes 1. PW ≤ 10 µ s, Duty cycle ≤ 1%
2. Starting Tch = 25°C, VDD = 20 V, RG = 25 Ω, VGS = 20 → 0 V
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No.
D14599EJ2V0DS00 (2nd edition)
Date Published April 2001 NS CP(K)
Printed in Japan
The mark ★ shows major revised points.
©
1999,2000
2SK3430
ELECTRICAL CHARACTERISTICS (T A = 25 °C)
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Zero Gate Vortage Drain Current
IDSS
VDS = 40 V, VGS = 0 V
10
µA
Gate Leakage Current
IGSS
VGS = ±20 V, VDS = 0 V
±10
µA
Gate Cut-off Voltage
VGS(off)
VDS = 10 V, ID = 1 mA
1.5
2.0
2.5
V
| yfs |
VDS = 10 V, ID = 40 A
20
40
RDS(on)1
VGS = 10 V, ID = 40 A
5.9
7.3
mΩ
RDS(on)2
VGS = 4 V, ID = 40 A
10.5
15
mΩ
Forward Transfer Admittance
Drain to Source On-state Resistance
S
Input Capacitance
Ciss
VDS = 10 V,
2800
pF
Output Capacitance
Coss
VGS = 0 V,
730
pF
Reverse Transfer Capacitance
Crss
f = 1 MHz
320
pF
Turn-on Delay Time
td(on)
VDD = 20 V,ID = 40 A
110
ns
VGS(on) = 10 V
1800
ns
RG = 10 Ω
170
ns
350
ns
Rise Time
tr
Turn-off Delay Time
td(off)
Fall Time
tf
Total Gate Charge
QG
VDD = 32 V
50
nC
Gate to Source Charge
QGS
VGS = 10 V
10
nC
Gate to Drain Charge
QGD
ID = 80 A
14
nC
VF(S-D)
IF = 80 A, VGS = 0 V
1.0
V
Reverse Recovery Time
trr
IF = 80 A, VGS = 0 V,
50
ns
Reverse Recovery Charge
Qrr
di/dt = 100 A/µ s
77
nC
Body Diode Forward Voltage
TEST CIRCUIT 1 AVALANCHE CAPABILITY
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
RG = 25 Ω
D.U.T.
L
RL
PG.
50 Ω
VDD
VGS = 20 → 0 V
RG
PG.
VGS
VGS
Wave Form
0
90%
ID
VGS
0
ID
Starting Tch
τ = 1 µs
Duty Cycle ≤ 1%
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
2
IG = 2 mA
RL
50 Ω
VDD
10%
0 10%
Wave Form
τ
VDD
PG.
90%
BVDSS
VDS
ID
90%
VDD
ID
IAS
VGS(on)
10%
D14599EJ2V0DS
tr td(off)
td(on)
ton
tf
toff
2SK3430
TYPICAL CHARACTERISTICS (T A = 25 °C )
DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA
TOTAL POWER DISSIPATION vs.
CASE TEMPERATURE
PT - Total Power Dissipation - W
dT - Percentage of Rated Power - %
140
100
80
60
40
20
0
0
20
40
60
80
100
120 140
120
100
80
60
40
20
0
0
160
20
Tch - Channel Temperature - ˚C
40
60
80
100
120 140
160
TC - Case Temperature - ˚C
FORWARD BIAS SAFE OPERATING AREA
ID - Drain Current - A
1000
ID(pulse)
d
ite )
Lim 10 V
n)
o
=
S(
ID(DC)
S
RD t VG
(a
100
PW
1m
s
10
0µ
s
=1
0µ
s
10
ms
Po
D
Lim wer C
ite Dis
d
sip
ati
on
10
1
0.1
0.1
TC = 25˚C
Single Pulse
1
10
100
VDS - Drain to Source Voltage - V
TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH
rth(t) - Transient Thermal Resistance - ˚C/W
1000
100
Rth(ch-A) = 83.3˚C/W
10
Rth(ch-C) = 1.49˚C/W
1
0.1
0.01
10 µ
Single Pulse
100 µ
1m
10 m
100 m
1
10
100
1000
PW - Pulse Width - s
D14599EJ2V0DS
3
2SK3430
DRAIN CURRENT vs.
DRAIN TO SOURCE VOLTAGE
FORWARD TRANSFER CHARACTERISTICS
300
1000 Pulsed
ID - Drain Current - A
ID - Drain Current - A
250
100
TA = −40˚C
25˚C
75˚C
150˚C
10
1
VGS =10 V
200
150
4.0 V
100
50
0.1
1
2
3
Pulsed
VDS = 10 V
5
6
4
0
TA = 150˚C
75˚C
25˚C
−40˚C
0.1
0.1
1
10
100
RDS(on) - Drain to Source On-state Resistance - mΩ
ID - Drain Current - A
4
DRAIN TO SOURCE ON-STATE
RESISTANCE vs. DRAIN CURRENT
25
Pulsed
20
15
VGS = 4.0 V
10
10 V
5
0
1
10
100
1000
RDS(on) - Drain to Source On-state Resistance - mΩ
10
VGS(th) - Gate to Source Threshold Voltage - V
| yfs | - Forward Transfer Admittance - S
100 VDS = 10 V
Pulsed
0.01
0.01
4
3
VDS - Drain to Source Voltage - V
FORWARD TRANSFER ADMITTANCE vs.
DRAIN CURRENT
1
2
1
VGS - Gate to Source Voltage - V
ID - Drain Current - A
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
GATE TO SOURCE VOLTAGE
20
Pulsed
10
ID = 40 A
0
4
0
8
12
16
20
VGS - Gate to Source Voltage - V
GATE TO SOURCE THRESHOLD VOLTAGE vs.
CHANNEL TEMPERATURE
3.0
VDS = 10 V
ID = 1 mA
2.5
2.0
1.5
1.0
0.5
0
−50
0
50
100
150
Tch - Channel Temperature - ˚C
D14599EJ2V0DS
2SK3430
1000
Pulsed
20
16
VGS = 4.0 V
12
8
VGS = 10 V
4
ID = 40 A
0
−50
50
0
100
Pulsed
VGS = 10 V
100
VGS = 0 V
10
1
0.1
0
150
VSD - Source to Drain Voltage - V
Tch - Channel Temperature - ˚C
CAPACITANCE vs. DRAIN TO
SOURCE VOLTAGE
SWITCHING CHARACTERISTICS
10000
VGS = 0 V
f = 1 MHz
td(on), tr, td(off), tf - Switching Time - ns
Ciss, Coss, Crss - Capacitance - pF
100000
10000
Ciss
1000
100
0.1
Coss
Crss
1
10
tr
1000
td(off)
100
tf
td(on)
10
0.1
100
100
10
10
VDS - Drain to Source Voltage - V
trr - Reverse Recovery Time - ns
DYNAMIC INPUT/OUTPUT CHARACTERISTICS
di/dt = 100 A/µs
VGS = 0 V
1.0
100
ID - Drain Current - A
REVERSE RECOVERY TIME vs.
DRAIN CURRENT
1
0.1
10
1
VDS - Drain to Source Voltage - V
1000
1.5
1.0
0.5
80
16
70
14
50
IF - Drain Current - A
VDD = 32 V
20 V
8V
VGS
10
40
8
30
6
20
4
10
0
0
100
12
60
2
VDS
10
20
ID = 80 A
30
40
50
60
70
VGS - Gate to Source Voltage - V
24
SOURCE TO DRAIN DIODE
FORWARD VOLTAGE
ISD - Diode Forward Current - A
RDS(on) - Drain to Source On-state Resistance - mΩ
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
CHANNEL TEMPERATURE
80
QG - Gate Charge - nC
D14599EJ2V0DS
5
2SK3430
SINGLE AVALANCHE ENERGY
DERATING FACTOR
SINGLE AVALANCHE CURRENT vs.
INDUCTIVE LOAD
160
IAS = 37 A
EAS
10
=1
37
mJ
1
VDD = 20 V
RG = 25 Ω
VGS = 20 → 0 V
0.1
10 µ
100 µ
120
100
80
60
40
20
1m
0
25
10 m
50
75
100
125
150
Starting Tch - Starting Channel Temperature - ˚C
L - Inductive Load - H
6
VDD = 20 V
RG = 25 Ω
VGS = 20 V → 0 V
IAS ≤ 37 A
140
Energy Derating Factor - %
IAS - Single Avalanche Current - A
100
D14599EJ2V0DS
2SK3430
PACKAGE DRAWINGS (Unit: mm)
2) TO-262(MP-25 Fin Cut)
1.0±0.5
TO-220AB(MP-25)
4.8 MAX.
10.6 MAX.
(10)
φ 3.6±0.2
1.3±0.2
4.8 MAX.
1.3±0.2
15.5 MAX.
5.9 MIN.
4
1
1 2 3
3
12.7 MIN.
6.0 MAX.
1.3±0.2
1.3±0.2
2.54 TYP.
2.8±0.2
1.Gate
2.Drain
3.Source
4.Fin (Drain)
2.54 TYP.
1.Gate
2.Drain
3.Source
4.Fin (Drain)
3)
TO-263 (MP-25ZJ)
4) TO-220SMD(MP-25Z)
Note
4.8 MAX.
(10)
4.8 MAX.
(10)
1.3±0.2
1.3±0.2
4
0.7±0.2
(0
)
.8R
1.0±0.3
0.5±0.2
2.54 TYP. 1
1.Gate
2.Drain
3.Source
4.Fin (Drain)
Drain
2
3.0±0.5
)
.5R R)
.8
(0
(0
0.5±0.2
3 2.54 TYP.
1.Gate
2.Drain
3.Source
4.Fin (Drain)
Note This Package is produced only in Japan.
EQUIVALENT CIRCUIT
.
8.5±0.2
1.0±0.5
3 2.54 TYP.
2.8±0.2
2
1.4±0.2
)
.5R
(0
1.1±0.4
1.4±0.2
2.8±0.2
5.7±0.4
8.5±0.2
1.0±0.5
4
2.54 TYP. 1
2.8±0.2
0.5±0.2
0.75±0.3
2.54 TYP.
0.5±0.2
0.75±0.1
2.54 TYP.
2
8.5±0.2
4
10.0
12.7 MIN.
3.0±0.3
1)
Remark
The diode connected between the gate and source of
the transistor serves as a protector against ESD. When
Body
Diode
Gate
this device actually used, an additional protection circuit
is externally required if a voltage exceeding the rated
Gate
Protection
Diode
voltage may be applied to this device.
Source
D14599EJ2V0DS
7
2SK3430
• The information in this document is current as of April, 2001. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
• NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
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patents, copyrights or other intellectual property rights of NEC or others.
• Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
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parties arising from the use of these circuits, software and information.
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M8E 00. 4